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dsp.cc
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1 /*
2  * Copyright (c) 2007 MIPS Technologies, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include "arch/mips/dsp.hh"
30 
31 #include "arch/mips/isa_traits.hh"
32 #include "base/bitfield.hh"
33 #include "base/logging.hh"
34 #include "cpu/static_inst.hh"
35 #include "sim/serialize.hh"
36 
37 using namespace MipsISA;
38 
39 int32_t
40 MipsISA::bitrev(int32_t value)
41 {
42  int32_t result = 0;
43  int shift;
44 
45  for (int i = 0; i < 16; i++) {
46  shift = 2 * i - 15;
47 
48  if (shift < 0)
49  result |= (value & 1 << i) << -shift;
50  else
51  result |= (value & 1 << i) >> shift;
52  }
53 
54  return result;
55 }
56 
57 uint64_t
58 MipsISA::dspSaturate(uint64_t value, int32_t fmt, int32_t sign,
59  uint32_t *overflow)
60 {
61  int64_t svalue = (int64_t)value;
62 
63  switch (sign) {
64  case SIGNED:
65  if (svalue > (int64_t)FIXED_SMAX[fmt]) {
66  *overflow = 1;
67  svalue = (int64_t)FIXED_SMAX[fmt];
68  } else if (svalue < (int64_t)FIXED_SMIN[fmt]) {
69  *overflow = 1;
70  svalue = (int64_t)FIXED_SMIN[fmt];
71  }
72  break;
73  case UNSIGNED:
74  if (svalue > (int64_t)FIXED_UMAX[fmt]) {
75  *overflow = 1;
76  svalue = FIXED_UMAX[fmt];
77  } else if (svalue < (int64_t)FIXED_UMIN[fmt]) {
78  *overflow = 1;
79  svalue = FIXED_UMIN[fmt];
80  }
81  break;
82  }
83 
84  return (uint64_t)svalue;
85 }
86 
87 uint64_t
88 MipsISA::checkOverflow(uint64_t value, int32_t fmt, int32_t sign,
89  uint32_t *overflow)
90 {
91  int64_t svalue = (int64_t)value;
92 
93  switch (sign)
94  {
95  case SIGNED:
96  if (svalue > (int64_t)FIXED_SMAX[fmt] ||
97  svalue < (int64_t)FIXED_SMIN[fmt])
98  *overflow = 1;
99  break;
100  case UNSIGNED:
101  if (svalue > (int64_t)FIXED_UMAX[fmt] ||
102  svalue < (int64_t)FIXED_UMIN[fmt])
103  *overflow = 1;
104  break;
105  }
106 
107  return (uint64_t)svalue;
108 }
109 
110 uint64_t
111 MipsISA::signExtend(uint64_t value, int32_t fmt)
112 {
113  int32_t signpos = SIMD_NBITS[fmt];
114  uint64_t sign = uint64_t(1) << (signpos - 1);
115  uint64_t ones = ~(0ULL);
116 
117  if (value & sign)
118  value |= (ones << signpos); // extend with ones
119  else
120  value &= (ones >> (64 - signpos)); // extend with zeros
121 
122  return value;
123 }
124 
125 uint64_t
126 MipsISA::addHalfLsb(uint64_t value, int32_t lsbpos)
127 {
128  return value += ULL(1) << (lsbpos - 1);
129 }
130 
131 int32_t
132 MipsISA::dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl)
133 {
134  int nvals = SIMD_NVALS[fmt];
135  int32_t result;
136  int64_t svalue;
137  uint32_t ouflag = 0;
138  uint64_t a_values[SIMD_MAX_VALS];
139 
140  simdUnpack(a, a_values, fmt, SIGNED);
141 
142  for (int i = 0; i < nvals; i++) {
143  svalue = (int64_t)a_values[i];
144 
145  if (a_values[i] == FIXED_SMIN[fmt]) {
146  a_values[i] = FIXED_SMAX[fmt];
147  ouflag = 1;
148  } else if (svalue < 0) {
149  a_values[i] = uint64_t(0 - svalue);
150  }
151  }
152 
153  simdPack(a_values, &result, fmt);
154 
155  if (ouflag)
156  writeDSPControl(dspctl, (ouflag << 4) << DSP_CTL_POS[DSP_OUFLAG],
157  1 << DSP_OUFLAG);
158 
159  return result;
160 }
161 
162 int32_t
163 MipsISA::dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
164  int32_t sign, uint32_t *dspctl)
165 {
166  int nvals = SIMD_NVALS[fmt];
167  int32_t result;
168  uint32_t ouflag = 0;
169  uint64_t a_values[SIMD_MAX_VALS];
170  uint64_t b_values[SIMD_MAX_VALS];
171 
172  simdUnpack(a, a_values, fmt, sign);
173  simdUnpack(b, b_values, fmt, sign);
174 
175  for (int i = 0; i < nvals; i++)
176  {
177  if (saturate)
178  a_values[i] = dspSaturate(a_values[i] + b_values[i], fmt, sign,
179  &ouflag);
180  else
181  a_values[i] = checkOverflow(a_values[i] + b_values[i], fmt, sign,
182  &ouflag);
183  }
184 
185  simdPack(a_values, &result, fmt);
186 
187  if (ouflag)
188  writeDSPControl(dspctl, (ouflag << 4) << DSP_CTL_POS[DSP_OUFLAG],
189  1 << DSP_OUFLAG);
190 
191  return result;
192 }
193 
194 int32_t
195 MipsISA::dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round,
196  int32_t sign)
197 {
198  int nvals = SIMD_NVALS[fmt];
199  int32_t result;
200  uint64_t a_values[SIMD_MAX_VALS];
201  uint64_t b_values[SIMD_MAX_VALS];
202 
203  simdUnpack(a, a_values, fmt, sign);
204  simdUnpack(b, b_values, fmt, sign);
205 
206  for (int i = 0; i < nvals; i++) {
207  if (round)
208  a_values[i] = addHalfLsb(a_values[i] + b_values[i], 1) >> 1;
209  else
210  a_values[i] = (a_values[i] + b_values[i]) >> 1;
211  }
212 
213  simdPack(a_values, &result, fmt);
214 
215  return result;
216 }
217 
218 int32_t
219 MipsISA::dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
220  int32_t sign, uint32_t *dspctl)
221 {
222  int nvals = SIMD_NVALS[fmt];
223  int32_t result;
224  uint32_t ouflag = 0;
225  uint64_t a_values[SIMD_MAX_VALS];
226  uint64_t b_values[SIMD_MAX_VALS];
227 
228  simdUnpack(a, a_values, fmt, sign);
229  simdUnpack(b, b_values, fmt, sign);
230 
231  for (int i = 0; i < nvals; i++) {
232  if (saturate)
233  a_values[i] = dspSaturate(a_values[i] - b_values[i], fmt, sign,
234  &ouflag);
235  else
236  a_values[i] = checkOverflow(a_values[i] - b_values[i], fmt, sign,
237  &ouflag);
238  }
239 
240  simdPack(a_values, &result, fmt);
241 
242  if (ouflag)
243  writeDSPControl(dspctl, (ouflag << 4) << DSP_CTL_POS[DSP_OUFLAG],
244  1 << DSP_OUFLAG);
245 
246  return result;
247 }
248 
249 int32_t
250 MipsISA::dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round,
251  int32_t sign)
252 {
253  int nvals = SIMD_NVALS[fmt];
254  int32_t result;
255  uint64_t a_values[SIMD_MAX_VALS];
256  uint64_t b_values[SIMD_MAX_VALS];
257 
258  simdUnpack(a, a_values, fmt, sign);
259  simdUnpack(b, b_values, fmt, sign);
260 
261  for (int i = 0; i < nvals; i++)
262  {
263  if (round)
264  a_values[i] = addHalfLsb(a_values[i] - b_values[i], 1) >> 1;
265  else
266  a_values[i] = (a_values[i] - b_values[i]) >> 1;
267  }
268 
269  simdPack(a_values, &result, fmt);
270 
271  return result;
272 }
273 
274 int32_t
275 MipsISA::dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate,
276  int32_t sign, uint32_t *dspctl)
277 {
278  int nvals = SIMD_NVALS[fmt];
279  int32_t result;
280  uint32_t ouflag = 0;
281  uint64_t a_values[SIMD_MAX_VALS];
282 
283  sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0);
284  simdUnpack(a, a_values, fmt, sign);
285 
286  for (int i = 0; i < nvals; i++)
287  {
288  if (saturate)
289  a_values[i] = dspSaturate(a_values[i] << sa, fmt, sign, &ouflag);
290  else
291  a_values[i] = checkOverflow(a_values[i] << sa, fmt, sign, &ouflag);
292  }
293 
294  simdPack(a_values, &result, fmt);
295 
296  if (ouflag)
297  writeDSPControl(dspctl, (ouflag << 6) << DSP_CTL_POS[DSP_OUFLAG],
298  1 << DSP_OUFLAG);
299 
300  return result;
301 }
302 
303 int32_t
304 MipsISA::dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign)
305 {
306  int nvals = SIMD_NVALS[fmt];
307  int32_t result;
308  uint64_t a_values[SIMD_MAX_VALS];
309 
310  sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0);
311 
312  simdUnpack(a, a_values, fmt, UNSIGNED);
313 
314  for (int i = 0; i < nvals; i++)
315  a_values[i] = a_values[i] >> sa;
316 
317  simdPack(a_values, &result, fmt);
318 
319  return result;
320 }
321 
322 int32_t
323 MipsISA::dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round,
324  int32_t sign, uint32_t *dspctl)
325 {
326  int nvals = SIMD_NVALS[fmt];
327  int32_t result;
328  uint64_t a_values[SIMD_MAX_VALS];
329 
330  sa = bits(sa, SIMD_LOG2N[fmt] - 1, 0);
331 
332  simdUnpack(a, a_values, fmt, SIGNED);
333 
334  for (int i = 0; i < nvals; i++) {
335  if (round)
336  a_values[i] = addHalfLsb(a_values[i], sa) >> sa;
337  else
338  a_values[i] = a_values[i] >> sa;
339  }
340 
341  simdPack(a_values, &result, fmt);
342 
343  return result;
344 }
345 
346 int32_t
347 MipsISA::dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
348  int32_t round, uint32_t *dspctl)
349 {
350  int nvals = SIMD_NVALS[fmt];
351  int sa = SIMD_NBITS[fmt];
352  int32_t result;
353  uint32_t ouflag = 0;
354  uint64_t a_values[SIMD_MAX_VALS];
355  uint64_t b_values[SIMD_MAX_VALS];
356  int64_t temp;
357 
358  simdUnpack(a, a_values, fmt, SIGNED);
359  simdUnpack(b, b_values, fmt, SIGNED);
360 
361  for (int i = 0; i < nvals; i++) {
362  if (round)
363  temp =
364  (int64_t)addHalfLsb(a_values[i] * b_values[i] << 1, sa) >> sa;
365  else
366  temp = (int64_t)(a_values[i] * b_values[i]) >> (sa - 1);
367 
368  if (a_values[i] == FIXED_SMIN[fmt] && b_values[i] == FIXED_SMIN[fmt]) {
369  ouflag = 1;
370 
371  if (saturate)
372  temp = FIXED_SMAX[fmt];
373  }
374 
375  a_values[i] = temp;
376  }
377 
378  simdPack(a_values, &result, fmt);
379 
380  if (ouflag)
381  writeDSPControl(dspctl, (ouflag << 5) << DSP_CTL_POS[DSP_OUFLAG],
382  1 << DSP_OUFLAG);
383 
384  return result;
385 }
386 
387 int32_t
388 MipsISA::dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
389  uint32_t *dspctl)
390 {
391  int nvals = SIMD_NVALS[fmt];
392  int32_t result;
393  uint32_t ouflag = 0;
394  uint64_t a_values[SIMD_MAX_VALS];
395  uint64_t b_values[SIMD_MAX_VALS];
396 
397  simdUnpack(a, a_values, fmt, SIGNED);
398  simdUnpack(b, b_values, fmt, SIGNED);
399 
400  for (int i = 0; i < nvals; i++)
401  {
402  if (saturate)
403  a_values[i] = dspSaturate(a_values[i] * b_values[i], fmt, SIGNED,
404  &ouflag);
405  else
406  a_values[i] = checkOverflow(a_values[i] * b_values[i], fmt, SIGNED,
407  &ouflag);
408  }
409 
410  simdPack(a_values, &result, fmt);
411 
412  if (ouflag)
413  writeDSPControl(dspctl, (ouflag << 5) << DSP_CTL_POS[DSP_OUFLAG],
414  1 << DSP_OUFLAG);
415 
416  return result;
417 }
418 
419 int32_t
420 MipsISA::dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
421 {
422  int nvals = SIMD_NVALS[SIMD_FMT_PH];
423  int32_t result;
424  uint32_t ouflag = 0;
425  uint64_t a_values[SIMD_MAX_VALS];
426  uint64_t b_values[SIMD_MAX_VALS];
427 
428  simdUnpack(a, a_values, SIMD_FMT_QB, UNSIGNED);
429  simdUnpack(b, b_values, SIMD_FMT_PH, UNSIGNED);
430 
431  switch (mode) {
432  case MODE_L:
433  for (int i = 0; i < nvals; i++)
434  b_values[i] = dspSaturate(a_values[i + 2] * b_values[i],
435  SIMD_FMT_PH, UNSIGNED, &ouflag);
436  break;
437  case MODE_R:
438  for (int i = 0; i < nvals; i++)
439  b_values[i] = dspSaturate(a_values[i] * b_values[i], SIMD_FMT_PH,
440  UNSIGNED, &ouflag);
441  break;
442  }
443 
444  simdPack(b_values, &result, SIMD_FMT_PH);
445 
446  if (ouflag)
447  writeDSPControl(dspctl, (ouflag << 5) << DSP_CTL_POS[DSP_OUFLAG],
448  1 << DSP_OUFLAG);
449 
450  return result;
451 }
452 
453 int32_t
454 MipsISA::dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
455 {
456  int nvals = SIMD_NVALS[SIMD_FMT_W];
457  int32_t result;
458  uint32_t ouflag = 0;
459  uint64_t a_values[SIMD_MAX_VALS];
460  uint64_t b_values[SIMD_MAX_VALS];
461  uint64_t c_values[SIMD_MAX_VALS];
462 
463  memset(c_values, 0, sizeof(c_values));
464 
465  simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED);
466  simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED);
467 
468  switch (mode) {
469  case MODE_L:
470  for (int i = 0; i < nvals; i++)
471  c_values[i] = dspSaturate(a_values[i + 1] * b_values[i + 1] << 1,
472  SIMD_FMT_W, SIGNED, &ouflag);
473  break;
474  case MODE_R:
475  for (int i = 0; i < nvals; i++)
476  c_values[i] = dspSaturate(a_values[i] * b_values[i] << 1,
477  SIMD_FMT_W, SIGNED, &ouflag);
478  break;
479  }
480 
481  simdPack(c_values, &result, SIMD_FMT_W);
482 
483  if (ouflag)
484  writeDSPControl(dspctl, (ouflag << 5) << DSP_CTL_POS[DSP_OUFLAG],
485  1 << DSP_OUFLAG);
486 
487  return result;
488 }
489 
490 int64_t
491 MipsISA::dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
492  int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
493  uint32_t *dspctl)
494 {
495  int nvals = SIMD_NVALS[infmt];
496  int64_t result = 0;
497  int64_t temp = 0;
498  uint32_t ouflag = 0;
499  uint64_t a_values[SIMD_MAX_VALS];
500  uint64_t b_values[SIMD_MAX_VALS];
501 
502  simdUnpack(a, a_values, infmt, SIGNED);
503  simdUnpack(b, b_values, infmt, SIGNED);
504 
505  for (int i = 0; i < nvals; i++) {
506  switch (mode) {
507  case MODE_X:
508  if (a_values[nvals - 1 - i] == FIXED_SMIN[infmt] &&
509  b_values[i] == FIXED_SMIN[infmt]) {
510  result += FIXED_SMAX[outfmt];
511  ouflag = 1;
512  }
513  else
514  result += a_values[nvals - 1 - i] * b_values[i] << 1;
515  break;
516  default:
517  if (a_values[i] == FIXED_SMIN[infmt] &&
518  b_values[i] == FIXED_SMIN[infmt]) {
519  result += FIXED_SMAX[outfmt];
520  ouflag = 1;
521  } else {
522  result += a_values[i] * b_values[i] << 1;
523  }
524  break;
525  }
526  }
527 
528  if (postsat) {
529  if (outfmt == SIMD_FMT_L) {
530  int signa = bits(dspac, 63, 63);
531  int signb = bits(result, 63, 63);
532 
533  temp = dspac + result;
534 
535  if (signa == signb && bits(temp, 63, 63) != signa) {
536  ouflag = 1;
537  if (signa)
538  dspac = FIXED_SMIN[outfmt];
539  else
540  dspac = FIXED_SMAX[outfmt];
541  } else {
542  dspac = temp;
543  }
544  } else {
545  dspac = dspSaturate(dspac + result, outfmt, SIGNED, &ouflag);
546  }
547  } else {
548  dspac += result;
549  }
550 
551  if (ouflag)
552  *dspctl = insertBits(*dspctl, 16 + ac, 16 + ac, 1);
553 
554  return dspac;
555 }
556 
557 int64_t
558 MipsISA::dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
559  int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
560  uint32_t *dspctl)
561 {
562  int nvals = SIMD_NVALS[infmt];
563  int64_t result = 0;
564  int64_t temp = 0;
565  uint32_t ouflag = 0;
566  uint64_t a_values[SIMD_MAX_VALS];
567  uint64_t b_values[SIMD_MAX_VALS];
568 
569  simdUnpack(a, a_values, infmt, SIGNED);
570  simdUnpack(b, b_values, infmt, SIGNED);
571 
572  for (int i = 0; i < nvals; i++) {
573  switch (mode) {
574  case MODE_X:
575  if (a_values[nvals - 1 - i] == FIXED_SMIN[infmt] &&
576  b_values[i] == FIXED_SMIN[infmt]) {
577  result += FIXED_SMAX[outfmt];
578  ouflag = 1;
579  } else {
580  result += a_values[nvals - 1 - i] * b_values[i] << 1;
581  }
582  break;
583  default:
584  if (a_values[i] == FIXED_SMIN[infmt] &&
585  b_values[i] == FIXED_SMIN[infmt]) {
586  result += FIXED_SMAX[outfmt];
587  ouflag = 1;
588  } else {
589  result += a_values[i] * b_values[i] << 1;
590  }
591  break;
592  }
593  }
594 
595  if (postsat) {
596  if (outfmt == SIMD_FMT_L) {
597  int signa = bits(dspac, 63, 63);
598  int signb = bits(-result, 63, 63);
599 
600  temp = dspac - result;
601 
602  if (signa == signb && bits(temp, 63, 63) != signa) {
603  ouflag = 1;
604  if (signa)
605  dspac = FIXED_SMIN[outfmt];
606  else
607  dspac = FIXED_SMAX[outfmt];
608  } else {
609  dspac = temp;
610  }
611  } else {
612  dspac = dspSaturate(dspac - result, outfmt, SIGNED, &ouflag);
613  }
614  } else {
615  dspac -= result;
616  }
617 
618  if (ouflag)
619  *dspctl = insertBits(*dspctl, 16 + ac, 16 + ac, 1);
620 
621  return dspac;
622 }
623 
624 int64_t
625 MipsISA::dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac,
626  int32_t fmt, int32_t sign, int32_t mode)
627 {
628  int nvals = SIMD_NVALS[fmt];
629  uint64_t a_values[SIMD_MAX_VALS];
630  uint64_t b_values[SIMD_MAX_VALS];
631 
632  simdUnpack(a, a_values, fmt, sign);
633  simdUnpack(b, b_values, fmt, sign);
634 
635  for (int i = 0; i < 2; i++) {
636  switch (mode) {
637  case MODE_L:
638  dspac += a_values[nvals - 1 - i] * b_values[nvals - 1 - i];
639  break;
640  case MODE_R:
641  dspac += a_values[nvals - 3 - i] * b_values[nvals - 3 - i];
642  break;
643  case MODE_X:
644  dspac += a_values[nvals - 1 - i] * b_values[i];
645  break;
646  }
647  }
648 
649  return dspac;
650 }
651 
652 int64_t
653 MipsISA::dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac,
654  int32_t fmt, int32_t sign, int32_t mode)
655 {
656  int nvals = SIMD_NVALS[fmt];
657  uint64_t a_values[SIMD_MAX_VALS];
658  uint64_t b_values[SIMD_MAX_VALS];
659 
660  simdUnpack(a, a_values, fmt, sign);
661  simdUnpack(b, b_values, fmt, sign);
662 
663  for (int i = 0; i < 2; i++) {
664  switch (mode) {
665  case MODE_L:
666  dspac -= a_values[nvals - 1 - i] * b_values[nvals - 1 - i];
667  break;
668  case MODE_R:
669  dspac -= a_values[nvals - 3 - i] * b_values[nvals - 3 - i];
670  break;
671  case MODE_X:
672  dspac -= a_values[nvals - 1 - i] * b_values[i];
673  break;
674  }
675  }
676 
677  return dspac;
678 }
679 
680 int64_t
681 MipsISA::dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
682  int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)
683 {
684  int nvals = SIMD_NVALS[fmt - 1];
685  uint64_t a_values[SIMD_MAX_VALS];
686  uint64_t b_values[SIMD_MAX_VALS];
687  int64_t temp = 0;
688  uint32_t ouflag = 0;
689 
690  simdUnpack(a, a_values, fmt, SIGNED);
691  simdUnpack(b, b_values, fmt, SIGNED);
692 
693  for (int i = 0; i < nvals; i++) {
694  switch (mode) {
695  case MODE_L:
696  temp = a_values[i + 1] * b_values[i + 1] << 1;
697  if (a_values[i + 1] == FIXED_SMIN[fmt] &&
698  b_values[i + 1] == FIXED_SMIN[fmt]) {
699  temp = (int64_t)FIXED_SMAX[fmt - 1];
700  ouflag = 1;
701  }
702  break;
703  case MODE_R:
704  temp = a_values[i] * b_values[i] << 1;
705  if (a_values[i] == FIXED_SMIN[fmt] &&
706  b_values[i] == FIXED_SMIN[fmt]) {
707  temp = (int64_t)FIXED_SMAX[fmt - 1];
708  ouflag = 1;
709  }
710  break;
711  }
712 
713  temp += dspac;
714 
715  if (saturate)
716  temp = dspSaturate(temp, fmt - 1, SIGNED, &ouflag);
717  if (ouflag)
718  *dspctl = insertBits(*dspctl, 16 + ac, 16 + ac, 1);
719  }
720 
721  return temp;
722 }
723 
724 int64_t
725 MipsISA::dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)
726 {
727  uint64_t a_values[SIMD_MAX_VALS];
728  uint64_t b_values[SIMD_MAX_VALS];
729 
730  simdUnpack(a, a_values, fmt, SIGNED);
731  simdUnpack(b, b_values, fmt, SIGNED);
732 
733  dspac += a_values[1] * b_values[1] - a_values[0] * b_values[0];
734 
735  return dspac;
736 }
737 
738 int64_t
739 MipsISA::dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
740  int32_t fmt, uint32_t *dspctl)
741 {
742  int nvals = SIMD_NVALS[fmt];
743  uint64_t a_values[SIMD_MAX_VALS];
744  uint64_t b_values[SIMD_MAX_VALS];
745  int64_t temp[2] = {0, 0};
746  uint32_t ouflag = 0;
747 
748  simdUnpack(a, a_values, fmt, SIGNED);
749  simdUnpack(b, b_values, fmt, SIGNED);
750 
751  for (int i = nvals - 1; i > -1; i--) {
752  temp[i] = a_values[i] * b_values[i] << 1;
753  if (a_values[i] == FIXED_SMIN[fmt] && b_values[i] == FIXED_SMIN[fmt]) {
754  temp[i] = FIXED_SMAX[fmt - 1];
755  ouflag = 1;
756  }
757  }
758 
759  dspac += temp[1] - temp[0];
760 
761  if (ouflag)
762  *dspctl = insertBits(*dspctl, 16 + ac, 16 + ac, 1);
763 
764  return dspac;
765 }
766 
767 void
768 MipsISA::dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
769  uint32_t *dspctl)
770 {
771  int nvals = SIMD_NVALS[fmt];
772  int ccond = 0;
773  uint64_t a_values[SIMD_MAX_VALS];
774  uint64_t b_values[SIMD_MAX_VALS];
775 
776  simdUnpack(a, a_values, fmt, sign);
777  simdUnpack(b, b_values, fmt, sign);
778 
779  for (int i = 0; i < nvals; i++) {
780  int cc = 0;
781 
782  switch (op) {
783  case CMP_EQ:
784  cc = (a_values[i] == b_values[i]);
785  break;
786  case CMP_LT:
787  cc = (a_values[i] < b_values[i]);
788  break;
789  case CMP_LE:
790  cc = (a_values[i] <= b_values[i]);
791  break;
792  }
793 
794  ccond |= cc << (DSP_CTL_POS[DSP_CCOND] + i);
795  }
796 
797  writeDSPControl(dspctl, ccond, 1 << DSP_CCOND);
798 }
799 
800 int32_t
801 MipsISA::dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)
802 {
803  int nvals = SIMD_NVALS[fmt];
804  int32_t result = 0;
805  uint64_t a_values[SIMD_MAX_VALS];
806  uint64_t b_values[SIMD_MAX_VALS];
807 
808  simdUnpack(a, a_values, fmt, sign);
809  simdUnpack(b, b_values, fmt, sign);
810 
811  for (int i = 0; i < nvals; i++) {
812  int cc = 0;
813 
814  switch (op) {
815  case CMP_EQ:
816  cc = (a_values[i] == b_values[i]);
817  break;
818  case CMP_LT:
819  cc = (a_values[i] < b_values[i]);
820  break;
821  case CMP_LE:
822  cc = (a_values[i] <= b_values[i]);
823  break;
824  }
825 
826  result |= cc << i;
827  }
828 
829  return result;
830 }
831 
832 int32_t
833 MipsISA::dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
834  uint32_t *dspctl)
835 {
836  int nvals = SIMD_NVALS[fmt];
837  int32_t result = 0;
838  int ccond = 0;
839  uint64_t a_values[SIMD_MAX_VALS];
840  uint64_t b_values[SIMD_MAX_VALS];
841 
842  simdUnpack(a, a_values, fmt, sign);
843  simdUnpack(b, b_values, fmt, sign);
844 
845  for (int i = 0; i < nvals; i++) {
846  int cc = 0;
847 
848  switch (op) {
849  case CMP_EQ:
850  cc = (a_values[i] == b_values[i]);
851  break;
852  case CMP_LT:
853  cc = (a_values[i] < b_values[i]);
854  break;
855  case CMP_LE:
856  cc = (a_values[i] <= b_values[i]);
857  break;
858  }
859 
860  result |= cc << i;
861  ccond |= cc << (DSP_CTL_POS[DSP_CCOND] + i);
862  }
863 
864  writeDSPControl(dspctl, ccond, 1 << DSP_CCOND);
865 
866  return result;
867 }
868 
869 int32_t
870 MipsISA::dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt,
871  int32_t outsign, int32_t mode)
872 {
873  int sa = 0;
874  int ninvals = SIMD_NVALS[infmt];
875  int noutvals = SIMD_NVALS[outfmt];
876  int32_t result;
877  uint64_t in_values[SIMD_MAX_VALS];
878  uint64_t out_values[SIMD_MAX_VALS];
879 
880  if (insign == SIGNED && outsign == SIGNED)
881  sa = SIMD_NBITS[infmt];
882  else if (insign == UNSIGNED && outsign == SIGNED)
883  sa = SIMD_NBITS[infmt] - 1;
884  else if (insign == UNSIGNED && outsign == UNSIGNED)
885  sa = 0;
886 
887  simdUnpack(a, in_values, infmt, insign);
888 
889  for (int i = 0; i<noutvals; i++) {
890  switch (mode) {
891  case MODE_L:
892  out_values[i] = in_values[i + (ninvals >> 1)] << sa;
893  break;
894  case MODE_R:
895  out_values[i] = in_values[i] << sa;
896  break;
897  case MODE_LA:
898  out_values[i] = in_values[(i << 1) + 1] << sa;
899  break;
900  case MODE_RA:
901  out_values[i] = in_values[i << 1] << sa;
902  break;
903  }
904  }
905 
906  simdPack(out_values, &result, outfmt);
907 
908  return result;
909 }
910 
911 int32_t
912 MipsISA::dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
913 {
914  uint64_t a_values[SIMD_MAX_VALS];
915  uint64_t b_values[SIMD_MAX_VALS];
916  uint64_t r_values[SIMD_MAX_VALS];
917  uint32_t ouflag = 0;
918  int32_t result = 0;
919 
920  simdUnpack(a, a_values, SIMD_FMT_PH, SIGNED);
921  simdUnpack(b, b_values, SIMD_FMT_PH, SIGNED);
922 
923  for (int i = 0; i<2; i++) {
924  r_values[i] =
925  dspSaturate((int64_t)b_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
926  SIMD_FMT_QB, UNSIGNED, &ouflag);
927  r_values[i + 2] =
928  dspSaturate((int64_t)a_values[i] >> (SIMD_NBITS[SIMD_FMT_QB] - 1),
929  SIMD_FMT_QB, UNSIGNED, &ouflag);
930  }
931 
932  simdPack(r_values, &result, SIMD_FMT_QB);
933 
934  if (ouflag)
935  *dspctl = insertBits(*dspctl, 22, 22, 1);
936 
937  return result;
938 }
939 
940 int32_t
941 MipsISA::dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
942 {
943  uint64_t a_values[SIMD_MAX_VALS];
944  uint64_t b_values[SIMD_MAX_VALS];
945  uint64_t r_values[SIMD_MAX_VALS];
946  uint32_t ouflag = 0;
947  int32_t result;
948 
949  simdUnpack(a, a_values, fmt, SIGNED);
950  simdUnpack(b, b_values, fmt, SIGNED);
951 
952  r_values[1] = dspSaturate((int64_t)addHalfLsb(a_values[0], 16) >> 16,
953  fmt + 1, SIGNED, &ouflag);
954  r_values[0] = dspSaturate((int64_t)addHalfLsb(b_values[0], 16) >> 16,
955  fmt + 1, SIGNED, &ouflag);
956 
957  simdPack(r_values, &result, fmt + 1);
958 
959  if (ouflag)
960  *dspctl = insertBits(*dspctl, 22, 22, 1);
961 
962  return result;
963 }
964 
965 int32_t
966 MipsISA::dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt,
967  int32_t round)
968 {
969  int nvals = SIMD_NVALS[fmt];
970  uint64_t a_values[SIMD_MAX_VALS];
971  uint64_t b_values[SIMD_MAX_VALS];
972  uint64_t c_values[SIMD_MAX_VALS];
973  int32_t result = 0;
974 
975  simdUnpack(a, a_values, fmt, SIGNED);
976  simdUnpack(b, b_values, fmt, SIGNED);
977 
978  for (int i = 0; i < nvals; i++) {
979  if (round) {
980  c_values[i] = addHalfLsb(b_values[i], sa) >> sa;
981  c_values[i + 1] = addHalfLsb(a_values[i], sa) >> sa;
982  } else {
983  c_values[i] = b_values[i] >> sa;
984  c_values[i + 1] = a_values[i] >> sa;
985  }
986  }
987 
988  simdPack(c_values, &result, fmt + 1);
989 
990  return result;
991 }
992 
993 int32_t
994 MipsISA::dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
995 {
996  int nvals = SIMD_NVALS[fmt];
997  int32_t result;
998  uint64_t a_values[SIMD_MAX_VALS];
999  uint64_t b_values[SIMD_MAX_VALS];
1000  uint64_t c_values[SIMD_MAX_VALS];
1001 
1002  simdUnpack(a, a_values, fmt, UNSIGNED);
1003  simdUnpack(b, b_values, fmt, UNSIGNED);
1004 
1005  for (int i = 0; i < nvals; i++) {
1006  int condbit = DSP_CTL_POS[DSP_CCOND] + i;
1007  if (bits(*dspctl, condbit, condbit) == 1)
1008  c_values[i] = a_values[i];
1009  else
1010  c_values[i] = b_values[i];
1011  }
1012 
1013  simdPack(c_values, &result, fmt);
1014 
1015  return result;
1016 }
1017 
1018 int32_t
1019 MipsISA::dspPack(int32_t a, int32_t b, int32_t fmt)
1020 {
1021  int32_t result;
1022  uint64_t a_values[SIMD_MAX_VALS];
1023  uint64_t b_values[SIMD_MAX_VALS];
1024  uint64_t c_values[SIMD_MAX_VALS];
1025 
1026  simdUnpack(a, a_values, fmt, UNSIGNED);
1027  simdUnpack(b, b_values, fmt, UNSIGNED);
1028 
1029  c_values[0] = b_values[1];
1030  c_values[1] = a_values[0];
1031 
1032  simdPack(c_values, &result, fmt);
1033 
1034  return result;
1035 }
1036 
1037 int32_t
1038 MipsISA::dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
1039  int32_t saturate, uint32_t *dspctl)
1040 {
1041  int32_t result = 0;
1042  uint32_t ouflag = 0;
1043  int64_t temp = 0;
1044 
1045  sa = bits(sa, 4, 0);
1046 
1047  if (sa > 0) {
1048  if (round) {
1049  temp = (int64_t)addHalfLsb(dspac, sa);
1050 
1051  if (dspac > 0 && temp < 0) {
1052  ouflag = 1;
1053  if (saturate)
1054  temp = FIXED_SMAX[SIMD_FMT_L];
1055  }
1056  temp = temp >> sa;
1057  } else {
1058  temp = dspac >> sa;
1059  }
1060  } else {
1061  temp = dspac;
1062  }
1063 
1064  dspac = checkOverflow(dspac, fmt, SIGNED, &ouflag);
1065 
1066  if (ouflag) {
1067  *dspctl = insertBits(*dspctl, 23, 23, ouflag);
1068 
1069  if (saturate)
1070  result = (int32_t)dspSaturate(temp, fmt, SIGNED, &ouflag);
1071  else
1072  result = (int32_t)temp;
1073  } else {
1074  result = (int32_t)temp;
1075  }
1076 
1077  return result;
1078 }
1079 
1080 int32_t
1081 MipsISA::dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl)
1082 {
1083  int32_t pos = 0;
1084  int32_t result = 0;
1085 
1086  pos = bits(*dspctl, 5, 0);
1087  size = bits(size, 4, 0);
1088 
1089  if (pos - (size + 1) >= -1) {
1090  result = bits(dspac, pos, pos - size);
1091  *dspctl = insertBits(*dspctl, 14, 14, 0);
1092  } else {
1093  result = 0;
1094  *dspctl = insertBits(*dspctl, 14, 14, 1);
1095  }
1096 
1097  return result;
1098 }
1099 
1100 int32_t
1101 MipsISA::dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl)
1102 {
1103  int32_t pos = 0;
1104  int32_t result = 0;
1105 
1106  pos = bits(*dspctl, 5, 0);
1107  size = bits(size, 4, 0);
1108 
1109  if (pos - (size + 1) >= -1) {
1110  result = bits(dspac, pos, pos - size);
1111  *dspctl = insertBits(*dspctl, 14, 14, 0);
1112  if (pos - (size + 1) >= 0)
1113  *dspctl = insertBits(*dspctl, 5, 0, pos - (size + 1));
1114  else if ((pos - (size + 1)) == -1)
1115  *dspctl = insertBits(*dspctl, 5, 0, 63);
1116  } else {
1117  result = 0;
1118  *dspctl = insertBits(*dspctl, 14, 14, 1);
1119  }
1120 
1121  return result;
1122 }
1123 
1124 void
1125 MipsISA::simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt)
1126 {
1127  int nvals = SIMD_NVALS[fmt];
1128  int nbits = SIMD_NBITS[fmt];
1129 
1130  *reg = 0;
1131 
1132  for (int i = 0; i < nvals; i++)
1133  *reg |= (int32_t)bits(values_ptr[i], nbits - 1, 0) << nbits * i;
1134 }
1135 
1136 void
1137 MipsISA::simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)
1138 {
1139  int nvals = SIMD_NVALS[fmt];
1140  int nbits = SIMD_NBITS[fmt];
1141 
1142  switch (sign) {
1143  case SIGNED:
1144  for (int i = 0; i < nvals; i++) {
1145  uint64_t tmp = (uint64_t)bits(reg, nbits * (i + 1) - 1, nbits * i);
1146  values_ptr[i] = signExtend(tmp, fmt);
1147  }
1148  break;
1149  case UNSIGNED:
1150  for (int i = 0; i < nvals; i++) {
1151  values_ptr[i] =
1152  (uint64_t)bits(reg, nbits * (i + 1) - 1, nbits * i);
1153  }
1154  break;
1155  }
1156 }
1157 
1158 void
1159 MipsISA::writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask)
1160 {
1161  uint32_t fmask = 0;
1162 
1163  if (mask & 0x01) fmask |= DSP_CTL_MASK[DSP_POS];
1164  if (mask & 0x02) fmask |= DSP_CTL_MASK[DSP_SCOUNT];
1165  if (mask & 0x04) fmask |= DSP_CTL_MASK[DSP_C];
1166  if (mask & 0x08) fmask |= DSP_CTL_MASK[DSP_OUFLAG];
1167  if (mask & 0x10) fmask |= DSP_CTL_MASK[DSP_CCOND];
1168  if (mask & 0x20) fmask |= DSP_CTL_MASK[DSP_EFI];
1169 
1170  *dspctl &= ~fmask;
1171  value &= fmask;
1172  *dspctl |= value;
1173 }
1174 
1175 uint32_t
1176 MipsISA::readDSPControl(uint32_t *dspctl, uint32_t mask)
1177 {
1178  uint32_t fmask = 0;
1179 
1180  if (mask & 0x01) fmask |= DSP_CTL_MASK[DSP_POS];
1181  if (mask & 0x02) fmask |= DSP_CTL_MASK[DSP_SCOUNT];
1182  if (mask & 0x04) fmask |= DSP_CTL_MASK[DSP_C];
1183  if (mask & 0x08) fmask |= DSP_CTL_MASK[DSP_OUFLAG];
1184  if (mask & 0x10) fmask |= DSP_CTL_MASK[DSP_CCOND];
1185  if (mask & 0x20) fmask |= DSP_CTL_MASK[DSP_EFI];
1186 
1187  return *dspctl & fmask;
1188 }
MipsISA::MODE_L
@ MODE_L
Definition: dsp.hh:70
MipsISA::dspDpsq
int64_t dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:558
MipsISA::SIMD_LOG2N
const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS]
Definition: dsp.hh:99
MipsISA::dspAddh
int32_t dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
Definition: dsp.cc:195
MipsISA::dspSaturate
uint64_t dspSaturate(uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
Definition: dsp.cc:58
MipsISA::dspExtp
int32_t dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl)
Definition: dsp.cc:1081
insertBits
constexpr T insertBits(T val, unsigned first, unsigned last, B bit_val)
Returns val with bits first to last set to the LSBs of bit_val.
Definition: bitfield.hh:143
MipsISA::MODE_RA
@ MODE_RA
Definition: dsp.hh:73
serialize.hh
MipsISA::DSP_SCOUNT
@ DSP_SCOUNT
Definition: dsp.hh:53
MipsISA::SIMD_NVALS
const uint32_t SIMD_NVALS[SIMD_NUM_FMTS]
Definition: dsp.hh:95
X86ISA::ac
Bitfield< 18 > ac
Definition: misc.hh:561
MipsISA::dspMulq
int32_t dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl)
Definition: dsp.cc:347
sc_dt::overflow
static void overflow(double &c, const scfx_params &params, bool &o_flag)
Definition: sc_fxnum.cc:459
MipsISA::signExtend
uint64_t signExtend(uint64_t value, int32_t signpos)
Definition: dsp.cc:111
X86ISA::op
Bitfield< 4 > op
Definition: types.hh:79
MipsISA::mask
mask
Definition: pra_constants.hh:70
MipsISA::DSP_CCOND
@ DSP_CCOND
Definition: dsp.hh:56
MipsISA::DSP_CTL_POS
const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS]
Definition: dsp.hh:83
MipsISA::dspPrecrSra
int32_t dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round)
Definition: dsp.cc:966
MipsISA::dspAbs
int32_t dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:132
MipsISA::DSP_EFI
@ DSP_EFI
Definition: dsp.hh:57
MipsISA::dspPrece
int32_t dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode)
Definition: dsp.cc:870
MipsISA::DSP_CTL_MASK
const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS]
Definition: dsp.hh:84
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:88
MipsISA::dspMul
int32_t dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl)
Definition: dsp.cc:388
MipsISA
Definition: decoder.cc:31
MipsISA::checkOverflow
uint64_t checkOverflow(uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
Definition: dsp.cc:88
MipsISA::dspMaq
int64_t dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)
Definition: dsp.cc:681
MipsISA::dspSub
int32_t dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:219
MipsISA::dspPrecrq
int32_t dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:941
MipsISA::readDSPControl
uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask)
Definition: dsp.cc:1176
MipsISA::SIMD_FMT_PH
@ SIMD_FMT_PH
Definition: dsp.hh:45
bitfield.hh
MipsISA::dspShra
int32_t dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:323
ArmISA::shift
Bitfield< 6, 5 > shift
Definition: types.hh:126
MipsISA::dspShrl
int32_t dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign)
Definition: dsp.cc:304
MipsISA::FIXED_SMIN
const uint64_t FIXED_SMIN[SIMD_NUM_FMTS]
Definition: dsp.hh:125
MipsISA::dspDpaq
int64_t dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:491
MipsISA::dspExtpd
int32_t dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl)
Definition: dsp.cc:1101
MipsISA::MODE_R
@ MODE_R
Definition: dsp.hh:71
MipsISA::UNSIGNED
@ UNSIGNED
Definition: dsp.hh:78
MipsISA::CMP_LT
@ CMP_LT
Definition: dsp.hh:64
MipsISA::MODE_LA
@ MODE_LA
Definition: dsp.hh:72
MipsISA::simdPack
void simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt)
Definition: dsp.cc:1125
MipsISA::DSP_OUFLAG
@ DSP_OUFLAG
Definition: dsp.hh:55
MipsISA::SIMD_NBITS
const uint32_t SIMD_NBITS[SIMD_NUM_FMTS]
Definition: dsp.hh:97
static_inst.hh
MipsISA::sa
Bitfield< 3, 0 > sa
Definition: pra_constants.hh:256
MipsISA::dspCmpg
int32_t dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)
Definition: dsp.cc:801
dsp.hh
MipsISA::simdUnpack
void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)
Definition: dsp.cc:1137
MipsISA::dspPrecrqu
int32_t dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
Definition: dsp.cc:912
MipsISA::mode
Bitfield< 11, 7 > mode
Definition: dt_constants.hh:95
MipsISA::dspCmpgd
int32_t dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
Definition: dsp.cc:833
MipsISA::SIMD_FMT_L
@ SIMD_FMT_L
Definition: dsp.hh:43
MipsISA::FIXED_UMAX
const uint64_t FIXED_UMAX[SIMD_NUM_FMTS]
Definition: dsp.hh:113
MipsISA::dspAdd
int32_t dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:163
MipsISA::DSP_POS
@ DSP_POS
Definition: dsp.hh:52
MipsISA::dspMuleq
int32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:454
MipsISA::addHalfLsb
uint64_t addHalfLsb(uint64_t value, int32_t lsbpos)
Definition: dsp.cc:126
MipsISA::SIGNED
@ SIGNED
Definition: dsp.hh:78
MipsISA::FIXED_SMAX
const uint64_t FIXED_SMAX[SIMD_NUM_FMTS]
Definition: dsp.hh:111
MipsISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:276
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
MipsISA::bitrev
int32_t bitrev(int32_t value)
Definition: dsp.cc:40
MipsISA::writeDSPControl
void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask)
Definition: dsp.cc:1159
MipsISA::dspMulsa
int64_t dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)
Definition: dsp.cc:725
MipsISA::FIXED_UMIN
const uint64_t FIXED_UMIN[SIMD_NUM_FMTS]
Definition: dsp.hh:127
logging.hh
isa_traits.hh
MipsISA::a
Bitfield< 13 > a
Definition: mt_constants.hh:89
bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:73
MipsISA::SIMD_FMT_W
@ SIMD_FMT_W
Definition: dsp.hh:44
MipsISA::SIMD_MAX_VALS
const uint32_t SIMD_MAX_VALS
Definition: dsp.hh:93
MipsISA::dspExtr
int32_t dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round, int32_t saturate, uint32_t *dspctl)
Definition: dsp.cc:1038
MipsISA::CMP_EQ
@ CMP_EQ
Definition: dsp.hh:63
MipsISA::dspCmp
void dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
Definition: dsp.cc:768
MipsISA::dspMulsaq
int64_t dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:739
MipsISA::dspMuleu
int32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:420
MipsISA::dspShll
int32_t dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:275
MipsISA::SIMD_FMT_QB
@ SIMD_FMT_QB
Definition: dsp.hh:46
MipsISA::dspDpa
int64_t dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
Definition: dsp.cc:625
MipsISA::dspPack
int32_t dspPack(int32_t a, int32_t b, int32_t fmt)
Definition: dsp.cc:1019
ULL
#define ULL(N)
uint64_t constant
Definition: types.hh:46
MipsISA::dspPick
int32_t dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:994
MipsISA::MODE_X
@ MODE_X
Definition: dsp.hh:74
MipsISA::DSP_C
@ DSP_C
Definition: dsp.hh:54
MipsISA::dspSubh
int32_t dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
Definition: dsp.cc:250
MipsISA::CMP_LE
@ CMP_LE
Definition: dsp.hh:65
MipsISA::dspDps
int64_t dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
Definition: dsp.cc:653
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