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gem5_to_tlm.cc
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1 /*
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32  * modification, are permitted provided that the following conditions are
33  * met:
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35  * 1. Redistributions of source code must retain the above copyright notice,
36  * this list of conditions and the following disclaimer.
37  *
38  * 2. Redistributions in binary form must reproduce the above copyright
39  * notice, this list of conditions and the following disclaimer in the
40  * documentation and/or other materials provided with the distribution.
41  *
42  * 3. Neither the name of the copyright holder nor the names of its
43  * contributors may be used to endorse or promote products derived from
44  * this software without specific prior written permission.
45  *
46  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
47  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
48  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
49  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
50  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
51  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
52  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
53  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
56  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57  */
58 
60 
61 #include <utility>
62 
63 #include "params/Gem5ToTlmBridge32.hh"
64 #include "params/Gem5ToTlmBridge64.hh"
65 #include "sim/system.hh"
68 
69 namespace sc_gem5
70 {
71 
77 
78 namespace
79 {
83 std::vector<PacketToPayloadConversionStep> extraPacketToPayloadSteps;
84 } // namespace
85 
93 void
95 {
96  extraPacketToPayloadSteps.push_back(std::move(step));
97 }
98 
105 {
107  trans->acquire();
108 
109  trans->set_address(packet->getAddr());
110 
111  /* Check if this transaction was allocated by mm */
112  sc_assert(trans->has_mm());
113 
114  unsigned int size = packet->getSize();
115  unsigned char *data = packet->getPtr<unsigned char>();
116 
117  trans->set_data_length(size);
118  trans->set_streaming_width(size);
119  trans->set_data_ptr(data);
120 
121  if ((packet->req->getFlags() & Request::NO_ACCESS) != 0) {
122  /* Do nothing */
124  } else if (packet->isRead()) {
126  } else if (packet->isWrite()) {
128  } else {
130  }
131 
132  // Attach the packet pointer to the TLM transaction to keep track.
133  auto *extension = new Gem5SystemC::Gem5Extension(packet);
134  trans->set_auto_extension(extension);
135 
136  // Apply all conversion steps necessary in this specific setup.
137  for (auto &step : extraPacketToPayloadSteps) {
138  step(packet, *trans);
139  }
140 
141  return trans;
142 }
143 
144 template <unsigned int BITWIDTH>
145 void
147  tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase)
148 {
149  sc_core::sc_time delay;
150 
151  if (phase == tlm::END_REQ ||
152  (&trans == blockingRequest && phase == tlm::BEGIN_RESP)) {
153  sc_assert(&trans == blockingRequest);
154  blockingRequest = nullptr;
155 
156  // Did another request arrive while blocked, schedule a retry.
157  if (needToSendRequestRetry) {
158  needToSendRequestRetry = false;
159  bridgeResponsePort.sendRetryReq();
160  }
161  }
162  if (phase == tlm::BEGIN_RESP) {
163  auto &extension = Gem5SystemC::Gem5Extension::getExtension(trans);
164  auto packet = extension.getPacket();
165 
166  sc_assert(!blockingResponse);
167 
168  bool need_retry = false;
169 
170  // If there is another gem5 model under the receiver side, and already
171  // make a response packet back, we can simply send it back. Otherwise,
172  // we make a response packet before sending it back to the initiator
173  // side gem5 module.
174  if (packet->needsResponse()) {
175  packet->makeResponse();
176  }
177  if (packet->isResponse()) {
178  need_retry = !bridgeResponsePort.sendTimingResp(packet);
179  }
180 
181  if (need_retry) {
182  blockingResponse = &trans;
183  } else {
184  if (phase == tlm::BEGIN_RESP) {
185  // Send END_RESP and we're finished:
186  tlm::tlm_phase fw_phase = tlm::END_RESP;
188  socket->nb_transport_fw(trans, fw_phase, delay);
189  // Release the transaction with all the extensions.
190  trans.release();
191  }
192  }
193  }
194 }
195 
196 template <unsigned int BITWIDTH>
199 {
200  sc_dt::uint64 start = trans.get_address();
201  sc_dt::uint64 end = start + trans.get_data_length();
202 
203  // Check for a back door we already know about.
204  AddrRange r(start, end);
205  auto it = backdoorMap.contains(r);
206  if (it != backdoorMap.end())
207  return it->second;
208 
209  // If not, ask the target for one.
210  tlm::tlm_dmi dmi_data;
211  if (!socket->get_direct_mem_ptr(trans, dmi_data))
212  return nullptr;
213 
214  // If the target gave us one, translate it to a gem5 MemBackdoor and
215  // store it in our cache.
216  AddrRange dmi_r(dmi_data.get_start_address(), dmi_data.get_end_address());
217  auto backdoor = new MemBackdoor(
218  dmi_r, dmi_data.get_dmi_ptr(), MemBackdoor::NoAccess);
219  backdoor->readable(dmi_data.is_read_allowed());
220  backdoor->writeable(dmi_data.is_write_allowed());
221 
222  backdoorMap.insert(dmi_r, backdoor);
223 
224  return backdoor;
225 }
226 
227 // Similar to TLM's blocking transport (LT)
228 template <unsigned int BITWIDTH>
229 Tick
231 {
232  panic_if(packet->cacheResponding(),
233  "Should not see packets where cache is responding");
234 
235  // Prepare the transaction.
236  auto *trans = packet2payload(packet);
237 
239 
240  if (trans->get_command() != tlm::TLM_IGNORE_COMMAND) {
241  // Execute b_transport:
242  socket->b_transport(*trans, delay);
243  }
244 
245  if (packet->needsResponse())
246  packet->makeResponse();
247 
248  trans->release();
249 
250  return delay.value();
251 }
252 
253 template <unsigned int BITWIDTH>
254 Tick
256  PacketPtr packet, MemBackdoorPtr &backdoor)
257 {
258  panic_if(packet->cacheResponding(),
259  "Should not see packets where cache is responding");
260 
262 
263  // Prepare the transaction.
264  auto *trans = packet2payload(packet);
265 
266  if (trans->get_command() != tlm::TLM_IGNORE_COMMAND) {
267  // Execute b_transport:
268  socket->b_transport(*trans, delay);
269  // If the hint said we could use DMI, set that up.
270  if (trans->is_dmi_allowed())
271  backdoor = getBackdoor(*trans);
272  } else {
273  // There's no transaction to piggy back on, so just request the
274  // backdoor normally.
275  backdoor = getBackdoor(*trans);
276  }
277 
278  if (packet->needsResponse())
279  packet->makeResponse();
280 
281  trans->release();
282 
283  return delay.value();
284 }
285 
286 template <unsigned int BITWIDTH>
287 void
289 {
290  // Snooping should be implemented with tlm_dbg_transport.
291  SC_REPORT_FATAL("Gem5ToTlmBridge",
292  "unimplemented func.: recvFunctionalSnoop");
293 }
294 
295 // Similar to TLM's non-blocking transport (AT).
296 template <unsigned int BITWIDTH>
297 bool
299 {
300  panic_if(packet->cacheResponding(),
301  "Should not see packets where cache is responding");
302 
303  // We should never get a second request after noting that a retry is
304  // required.
305  sc_assert(!needToSendRequestRetry);
306 
307  // Remember if a request comes in while we're blocked so that a retry
308  // can be sent to gem5.
309  if (blockingRequest) {
310  needToSendRequestRetry = true;
311  return false;
312  }
313 
314  /*
315  * NOTE: normal tlm is blocking here. But in our case we return false
316  * and tell gem5 when a retry can be done. This is the main difference
317  * in the protocol:
318  * if (requestInProgress)
319  * {
320  * wait(endRequestEvent);
321  * }
322  * requestInProgress = trans;
323  */
324 
325  // Prepare the transaction.
326  auto *trans = packet2payload(packet);
327 
328  /*
329  * Pay for annotated transport delays.
330  *
331  * The header delay marks the point in time, when the packet first is seen
332  * by the transactor. This is the point in time when the transactor needs
333  * to send the BEGIN_REQ to the SystemC world.
334  *
335  * NOTE: We drop the payload delay here. Normally, the receiver would be
336  * responsible for handling the payload delay. In this case, however,
337  * the receiver is a SystemC module and has no notion of the gem5
338  * transport protocol and we cannot simply forward the
339  * payload delay to the receiving module. Instead, we expect the
340  * receiving SystemC module to model the payload delay by deferring
341  * the END_REQ. This could lead to incorrect delays, if the XBar
342  * payload delay is longer than the time the receiver needs to accept
343  * the request (time between BEGIN_REQ and END_REQ).
344  *
345  * TODO: We could detect the case described above by remembering the
346  * payload delay and comparing it to the time between BEGIN_REQ and
347  * END_REQ. Then, a warning should be printed.
348  */
349  auto delay = sc_core::sc_time::from_value(packet->payloadDelay);
350  // Reset the delays
351  packet->payloadDelay = 0;
352  packet->headerDelay = 0;
353 
354  // Starting TLM non-blocking sequence (AT) Refer to IEEE1666-2011 SystemC
355  // Standard Page 507 for a visualisation of the procedure.
358  status = socket->nb_transport_fw(*trans, phase, delay);
359  // Check returned value:
360  if (status == tlm::TLM_ACCEPTED) {
361  sc_assert(phase == tlm::BEGIN_REQ);
362  // Accepted but is now blocking until END_REQ (exclusion rule).
363  blockingRequest = trans;
364  } else if (status == tlm::TLM_UPDATED) {
365  // The Timing annotation must be honored:
366  sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
367  // Accepted but is now blocking until END_REQ (exclusion rule).
368  blockingRequest = trans;
369  auto cb = [this, trans, phase]() { pec(*trans, phase); };
370  system->schedule(new EventFunctionWrapper(cb, "pec", true),
371  curTick() + delay.value());
372  } else if (status == tlm::TLM_COMPLETED) {
373  // Transaction is over nothing has do be done.
374  sc_assert(phase == tlm::END_RESP);
375  trans->release();
376  }
377 
378  return true;
379 }
380 
381 template <unsigned int BITWIDTH>
382 bool
384 {
385  // Snooping should be implemented with tlm_dbg_transport.
386  SC_REPORT_FATAL("Gem5ToTlmBridge",
387  "unimplemented func.: recvTimingSnoopResp");
388  return false;
389 }
390 
391 template <unsigned int BITWIDTH>
392 bool
394 {
395  panic("tryTiming(PacketPtr) isn't implemented.");
396 }
397 
398 template <unsigned int BITWIDTH>
399 void
401 {
402  /* Retry a response */
403  sc_assert(blockingResponse);
404 
405  tlm::tlm_generic_payload *trans = blockingResponse;
406  blockingResponse = nullptr;
407  PacketPtr packet =
409 
410  bool need_retry = !bridgeResponsePort.sendTimingResp(packet);
411 
412  sc_assert(!need_retry);
413 
416  socket->nb_transport_fw(*trans, phase, delay);
417  // Release transaction with all the extensions
418  trans->release();
419 }
420 
421 // Similar to TLM's debug transport.
422 template <unsigned int BITWIDTH>
423 void
425 {
426  // Prepare the transaction.
427  auto *trans = packet2payload(packet);
428 
429  /* Execute Debug Transport: */
430  unsigned int bytes = socket->transport_dbg(*trans);
431  if (bytes != trans->get_data_length()) {
432  SC_REPORT_FATAL("Gem5ToTlmBridge",
433  "debug transport was not completed");
434  }
435 
436  trans->release();
437 }
438 
439 template <unsigned int BITWIDTH>
442  tlm::tlm_phase &phase, sc_core::sc_time &delay)
443 {
444  auto cb = [this, &trans, phase]() { pec(trans, phase); };
445  system->schedule(new EventFunctionWrapper(cb, "pec", true),
446  curTick() + delay.value());
447  return tlm::TLM_ACCEPTED;
448 }
449 
450 template <unsigned int BITWIDTH>
451 void
453  sc_dt::uint64 start_range, sc_dt::uint64 end_range)
454 {
455  AddrRange r(start_range, end_range);
456 
457  for (;;) {
458  auto it = backdoorMap.intersects(r);
459  if (it == backdoorMap.end())
460  break;
461 
462  it->second->invalidate();
463  delete it->second;
464  backdoorMap.erase(it);
465  };
466 }
467 
468 template <unsigned int BITWIDTH>
470  const Params &params, const sc_core::sc_module_name &mn) :
472  bridgeResponsePort(std::string(name()) + ".gem5", *this),
473  socket("tlm_socket"),
474  wrapper(socket, std::string(name()) + ".tlm", InvalidPortID),
475  system(params.system), blockingRequest(nullptr),
476  needToSendRequestRetry(false), blockingResponse(nullptr),
477  addrRanges(params.addr_ranges.begin(), params.addr_ranges.end())
478 {
479 }
480 
481 template <unsigned int BITWIDTH>
482 ::Port &
483 Gem5ToTlmBridge<BITWIDTH>::gem5_getPort(const std::string &if_name, int idx)
484 {
485  if (if_name == "gem5")
486  return bridgeResponsePort;
487  else if (if_name == "tlm")
488  return wrapper;
489 
490  return sc_core::sc_module::gem5_getPort(if_name, idx);
491 }
492 
493 template <unsigned int BITWIDTH>
494 void
496 {
497  bridgeResponsePort.sendRangeChange();
498 
499  socket.register_nb_transport_bw(this, &Gem5ToTlmBridge::nb_transport_bw);
500  socket.register_invalidate_direct_mem_ptr(
503 }
504 
505 } // namespace sc_gem5
506 
508 Gem5ToTlmBridge32Params::create() const
509 {
510  return new sc_gem5::Gem5ToTlmBridge<32>(
511  *this, sc_core::sc_module_name(name.c_str()));
512 }
513 
515 Gem5ToTlmBridge64Params::create() const
516 {
517  return new sc_gem5::Gem5ToTlmBridge<64>(
518  *this, sc_core::sc_module_name(name.c_str()));
519 }
ArmISA::status
Bitfield< 5, 0 > status
Definition: miscregs_types.hh:417
sc_core::sc_time::from_value
static sc_time from_value(sc_dt::uint64)
Definition: sc_time.cc:210
tlm::tlm_generic_payload::set_data_length
void set_data_length(const unsigned int length)
Definition: gp.hh:210
MemBackdoor
Definition: backdoor.hh:38
system.hh
Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:620
data
const char data[]
Definition: circlebuf.test.cc:47
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:755
Gem5SystemC::MemoryManager
Definition: sc_mm.hh:45
tlm::tlm_phase
Definition: phase.hh:47
sc_gem5::Gem5ToTlmBridge::before_end_of_elaboration
void before_end_of_elaboration() override
Definition: gem5_to_tlm.cc:495
Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:413
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:244
sc_gem5::Gem5ToTlmBridge::recvAtomic
Tick recvAtomic(PacketPtr packet)
Definition: gem5_to_tlm.cc:230
sc_gem5::addPacketToPayloadConversionStep
void addPacketToPayloadConversionStep(PacketToPayloadConversionStep step)
Notify the Gem5ToTlm bridge that we need an extra step to properly convert a gem5 packet to tlm paylo...
Definition: gem5_to_tlm.cc:94
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
gem5_to_tlm.hh
tlm::tlm_dmi
Definition: dmi.hh:46
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
tlm::TLM_UPDATED
@ TLM_UPDATED
Definition: fw_bw_ifs.hh:65
sc_gem5::packet2payload
tlm::tlm_generic_payload * packet2payload(PacketPtr packet)
Convert a gem5 packet to a TLM payload by copying all the relevant information to new tlm payload.
Definition: gem5_to_tlm.cc:104
Packet::isRead
bool isRead() const
Definition: packet.hh:557
sc_ext.hh
tlm::END_REQ
@ END_REQ
Definition: phase.hh:42
MemBackdoor::NoAccess
@ NoAccess
Definition: backdoor.hh:48
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:59
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
SC_REPORT_FATAL
#define SC_REPORT_FATAL(msg_type, msg)
Definition: sc_report_handler.hh:131
sc_gem5::Gem5ToTlmBridge::recvTimingSnoopResp
bool recvTimingSnoopResp(PacketPtr packet)
Definition: gem5_to_tlm.cc:383
Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:341
std::vector
STL vector class.
Definition: stl.hh:37
Gem5SystemC::Gem5Extension::getPacket
PacketPtr getPacket()
Definition: sc_ext.cc:62
Packet::getSize
unsigned getSize() const
Definition: packet.hh:765
tlm::tlm_generic_payload::release
void release()
Definition: gp.hh:147
sc_gem5::Gem5ToTlmBridge::recvRespRetry
void recvRespRetry()
Definition: gem5_to_tlm.cc:400
sc_gem5::Gem5ToTlmBridge::Gem5ToTlmBridge
Gem5ToTlmBridge(const Params &p, const sc_core::sc_module_name &mn)
Definition: gem5_to_tlm.cc:469
sc_assert
#define sc_assert(expr)
Definition: sc_report_handler.hh:135
Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:395
EventFunctionWrapper
Definition: eventq.hh:1112
sc_gem5::PacketToPayloadConversionStep
std::function< void(PacketPtr pkt, tlm::tlm_generic_payload &trans)> PacketToPayloadConversionStep
Definition: gem5_to_tlm.hh:78
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
sc_gem5::Gem5ToTlmBridge::gem5_getPort
::Port & gem5_getPort(const std::string &if_name, int idx=-1) override
Definition: gem5_to_tlm.cc:483
sc_core::sc_module::gem5_getPort
virtual ::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
tlm::tlm_generic_payload::set_command
void set_command(const tlm_command command)
Definition: gp.hh:198
tlm::tlm_dmi::is_read_allowed
bool is_read_allowed() const
Definition: dmi.hh:100
tlm::tlm_generic_payload::get_data_length
unsigned int get_data_length() const
Definition: gp.hh:209
AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:68
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:571
MipsISA::r
r
Definition: pra_constants.hh:95
sc_core::sc_time
Definition: sc_time.hh:49
sc_core::sc_time::value
sc_dt::uint64 value() const
Definition: sc_time.cc:115
tlm::tlm_dmi::get_end_address
sc_dt::uint64 get_end_address() const
Definition: dmi.hh:94
tlm::TLM_READ_COMMAND
@ TLM_READ_COMMAND
Definition: gp.hh:101
tlm::tlm_dmi::is_write_allowed
bool is_write_allowed() const
Definition: dmi.hh:105
tlm::tlm_dmi::get_start_address
sc_dt::uint64 get_start_address() const
Definition: dmi.hh:93
sc_core::sc_module_name
Definition: sc_module_name.hh:41
mm
Definition: mm.h:8
sc_gem5::Gem5ToTlmBridge::Params
Gem5ToTlmBridgeBaseParams Params
Definition: gem5_to_tlm.hh:197
tlm::tlm_generic_payload::acquire
void acquire()
Definition: gp.hh:140
tlm::tlm_generic_payload::set_streaming_width
void set_streaming_width(const unsigned int streaming_width)
Definition: gp.hh:230
sc_gem5::Gem5ToTlmBridge
Definition: gem5_to_tlm.hh:91
sc_gem5::Gem5ToTlmBridge::nb_transport_bw
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &t)
Definition: gem5_to_tlm.cc:441
tlm::END_RESP
@ END_RESP
Definition: phase.hh:44
Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1005
tlm::TLM_IGNORE_COMMAND
@ TLM_IGNORE_COMMAND
Definition: gp.hh:103
name
const std::string & name()
Definition: trace.cc:48
tlm::tlm_dmi::get_dmi_ptr
unsigned char * get_dmi_ptr() const
Definition: dmi.hh:92
mm::allocate
gp_t * allocate()
Definition: mm.h:55
sc_gem5::Gem5ToTlmBridge::recvAtomicBackdoor
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor)
Definition: gem5_to_tlm.cc:255
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:139
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
tlm::tlm_generic_payload
Definition: gp.hh:133
Gem5SystemC::Gem5Extension::getExtension
static Gem5Extension & getExtension(const tlm::tlm_generic_payload *payload)
Definition: sc_ext.cc:47
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:258
sc_mm.hh
sc_core::sc_module::before_end_of_elaboration
virtual void before_end_of_elaboration()
Definition: sc_module.hh:248
sc_gem5::Gem5ToTlmBridge::recvFunctional
void recvFunctional(PacketPtr packet)
Definition: gem5_to_tlm.cc:424
tlm::tlm_generic_payload::set_address
void set_address(const sc_dt::uint64 address)
Definition: gp.hh:202
sc_gem5::Gem5ToTlmBridge::recvFunctionalSnoop
void recvFunctionalSnoop(PacketPtr packet)
Definition: gem5_to_tlm.cc:288
sc_gem5::Gem5ToTlmBridge::recvTimingReq
bool recvTimingReq(PacketPtr packet)
Definition: gem5_to_tlm.cc:298
tlm::tlm_generic_payload::has_mm
bool has_mm() const
Definition: gp.hh:157
Packet::isWrite
bool isWrite() const
Definition: packet.hh:558
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
sc_gem5::Port
Definition: port.hh:50
Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1158
tlm::tlm_generic_payload::set_auto_extension
T * set_auto_extension(T *ext)
Definition: gp.hh:370
sc_gem5::Gem5ToTlmBridge::getBackdoor
MemBackdoorPtr getBackdoor(tlm::tlm_generic_payload &trans)
Definition: gem5_to_tlm.cc:198
sc_gem5::Gem5ToTlmBridge::invalidate_direct_mem_ptr
void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range)
Definition: gem5_to_tlm.cc:452
sc_gem5
Definition: sc_clock.cc:42
curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:43
Gem5SystemC::Gem5Extension
Definition: sc_ext.hh:43
sc_gem5::mm
Gem5SystemC::MemoryManager mm
Instantiate a tlm memory manager that takes care about all the tlm transactions in the system.
Definition: gem5_to_tlm.cc:76
sc_gem5::Gem5ToTlmBridge::tryTiming
bool tryTiming(PacketPtr packet)
Definition: gem5_to_tlm.cc:393
tlm::tlm_generic_payload::get_address
sc_dt::uint64 get_address() const
Definition: gp.hh:201
sc_gem5::Gem5ToTlmBridge::pec
void pec(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase)
Definition: gem5_to_tlm.cc:146
sc_gem5::Gem5ToTlmBridgeBase
Definition: gem5_to_tlm.hh:84
tlm::BEGIN_RESP
@ BEGIN_RESP
Definition: phase.hh:43
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
tlm::tlm_generic_payload::set_data_ptr
void set_data_ptr(unsigned char *data)
Definition: gp.hh:206
tlm::TLM_ACCEPTED
@ TLM_ACCEPTED
Definition: fw_bw_ifs.hh:65

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