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cpu
testers
traffic_gen
idle_gen.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2012-2013, 2017-2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed here under. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
15
* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
18
* redistributions in binary form must reproduce the above copyright
19
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
*/
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43
#ifndef __CPU_TRAFFIC_GEN_IDLE_GEN_HH__
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#define __CPU_TRAFFIC_GEN_IDLE_GEN_HH__
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#include "
base/bitfield.hh
"
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#include "
base/intmath.hh
"
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#include "
base_gen.hh
"
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#include "
mem/packet.hh
"
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54
class
IdleGen
:
public
BaseGen
55
{
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57
public
:
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59
IdleGen
(
SimObject
&obj,
RequestorID
requestor_id,
Tick
_duration)
60
:
BaseGen
(obj, requestor_id, _duration)
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{ }
62
63
void
enter
();
64
65
PacketPtr
getNextPacket
();
66
67
Tick
nextPacketTick
(
bool
elastic,
Tick
delay)
const
;
68
};
69
70
#endif
BaseGen
Base class for all generators, with the shared functionality and virtual functions for entering,...
Definition:
base_gen.hh:61
IdleGen
The idle generator does nothing.
Definition:
idle_gen.hh:54
IdleGen::nextPacketTick
Tick nextPacketTick(bool elastic, Tick delay) const
Determine the tick when the next packet is available.
Definition:
idle_gen.cc:56
Tick
uint64_t Tick
Tick count type.
Definition:
types.hh:59
packet.hh
RequestorID
uint16_t RequestorID
Definition:
request.hh:89
bitfield.hh
IdleGen::getNextPacket
PacketPtr getNextPacket()
Get the next generated packet.
Definition:
idle_gen.cc:50
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition:
packet.hh:258
intmath.hh
IdleGen::enter
void enter()
Enter this generator state.
Definition:
idle_gen.cc:47
base_gen.hh
IdleGen::IdleGen
IdleGen(SimObject &obj, RequestorID requestor_id, Tick _duration)
Definition:
idle_gen.hh:59
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:141
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