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malta_cchip.cc
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
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28 
33 #include "dev/mips/malta_cchip.hh"
34 
35 #include <deque>
36 #include <string>
37 #include <vector>
38 
39 #include "base/trace.hh"
40 #include "cpu/intr_control.hh"
41 #include "cpu/thread_context.hh"
42 #include "debug/Malta.hh"
43 #include "dev/mips/malta.hh"
44 #include "dev/mips/maltareg.h"
45 #include "mem/packet.hh"
46 #include "mem/packet_access.hh"
47 #include "mem/port.hh"
48 #include "params/MaltaCChip.hh"
49 #include "sim/system.hh"
50 
52  : BasicPioDevice(p, 0xfffffff), malta(p.malta)
53 {
54  warn("MaltaCCHIP::MaltaCChip() not implemented.");
55 
56  //Put back pointer in malta
57  malta->cchip = this;
58 
59 }
60 
61 Tick
63 {
64  panic("MaltaCCHIP::read() not implemented.");
65  return pioDelay;
66 }
67 
68 Tick
70 {
71  panic("MaltaCCHIP::write() not implemented.");
72  return pioDelay;
73 }
74 
75 void
76 MaltaCChip::clearIPI(uint64_t ipintr)
77 {
78  panic("MaltaCCHIP::clear() not implemented.");
79 }
80 
81 void
82 MaltaCChip::clearITI(uint64_t itintr)
83 {
84  panic("MaltaCCHIP::clearITI() not implemented.");
85 }
86 
87 void
88 MaltaCChip::reqIPI(uint64_t ipreq)
89 {
90  panic("MaltaCCHIP::reqIPI() not implemented.");
91 }
92 
93 
94 void
96 {
97  panic("MaltaCCHIP::postRTC() not implemented.");
98 }
99 
100 void
101 MaltaCChip::postIntr(uint32_t interrupt)
102 {
103  uint64_t size = sys->threads.size();
104  assert(size <= Malta::Max_CPUs);
105 
106  for (int i=0; i < size; i++) {
107  //Note: Malta does not use index, but this was added to use the
108  //pre-existing implementation
109  malta->intrctrl->post(i, interrupt, 0);
110  DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n",
111  i, interrupt);
112  }
113 }
114 
115 void
116 MaltaCChip::clearIntr(uint32_t interrupt)
117 {
118  uint64_t size = sys->threads.size();
119  assert(size <= Malta::Max_CPUs);
120 
121  for (int i=0; i < size; i++) {
122  //Note: Malta does not use index, but this was added to use the
123  //pre-existing implementation
124  malta->intrctrl->clear(i, interrupt, 0);
125  DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n",
126  i, interrupt);
127  }
128 }
129 
130 
131 void
133 {
134 }
135 
136 void
138 {
139 }
Malta::cchip
MaltaCChip * cchip
Pointer to the Malta CChip.
Definition: malta.hh:69
warn
#define warn(...)
Definition: logging.hh:239
IntrControl::clear
void clear(int cpu_id, int int_num, int index)
Definition: intr_control.cc:53
malta.hh
system.hh
IntrControl::post
void post(int cpu_id, int int_num, int index)
Definition: intr_control.cc:45
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
MaltaCChip::clearIntr
void clearIntr(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
Definition: malta_cchip.cc:116
MaltaCChip::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:62
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:59
malta_cchip.hh
packet.hh
PioDevice::sys
System * sys
Definition: io_device.hh:102
maltareg.h
Malta::Max_CPUs
static const int Max_CPUs
Max number of CPUs in a Malta.
Definition: malta.hh:57
MaltaCChip::postIntr
void postIntr(uint32_t interrupt)
post an interrupt to the CPU.
Definition: malta_cchip.cc:101
cp
Definition: cprintf.cc:37
MaltaCChip::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: malta_cchip.cc:69
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:237
MaltaCChip::reqIPI
void reqIPI(uint64_t ipreq)
request an interrupt be posted to the CPU.
Definition: malta_cchip.cc:88
port.hh
MaltaCChip::malta
Malta * malta
pointer to the malta object.
Definition: malta_cchip.hh:52
System::Threads::size
int size() const
Definition: system.hh:204
packet_access.hh
MaltaCChip::postRTC
void postRTC()
post an RTC interrupt to the CPU
Definition: malta_cchip.cc:95
MaltaCChip::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta_cchip.cc:132
System::threads
Threads threads
Definition: system.hh:304
MaltaCChip::clearITI
void clearITI(uint64_t itintr)
clear a timer interrupt previously posted to the CPU.
Definition: malta_cchip.cc:82
Malta
Top level class for Malta Chipset emulation.
Definition: malta.hh:53
intr_control.hh
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:258
BasicPioDevice
Definition: io_device.hh:144
Platform::intrctrl
IntrControl * intrctrl
Pointer to the interrupt controller.
Definition: platform.hh:53
BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:154
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:64
MaltaCChip::clearIPI
void clearIPI(uint64_t ipintr)
post an ipi interrupt to the CPU.
Definition: malta_cchip.cc:76
trace.hh
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
MaltaCChip::MaltaCChip
MaltaCChip(const Params &p)
Initialize the Malta CChip by setting all of the device register to 0.
Definition: malta_cchip.cc:51
CheckpointIn
Definition: serialize.hh:68
MaltaCChip::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta_cchip.cc:137
PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:131
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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