locked_mem.hh

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#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
#define __ARCH_MIPS_LOCKED_MEM_HH__
 
#include "arch/mips/registers.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "debug/LLSC.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
 
namespace MipsISA
{
template <class XC>
inline void
handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
{
    if (!xc->readMiscReg(MISCREG_LLFLAG))
        return;
 
    Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
    Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
 
    if (locked_addr == snoop_addr)
        xc->setMiscReg(MISCREG_LLFLAG, false);
}
 
 
template <class XC>
inline void
handleLockedRead(XC *xc, const RequestPtr &req)
{
    xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
    xc->setMiscReg(MISCREG_LLFLAG, true);
    DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
                  " Address set to %x.\n",
            req->contextId(), req->getPaddr() & ~0xf);
}
 
template <class XC>
inline void
handleLockedSnoopHit(XC *xc)
{
}
 
template <class XC>
inline bool
handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
{
    if (req->isUncacheable()) {
        // Funky Turbolaser mailbox access...don't update
        // result register (see stq_c in decoder.isa)
        req->setExtraData(2);
    } else {
        // standard store conditional
        bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
        Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
 
        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
            // Lock flag not set or addr mismatch in CPU;
            // don't even bother sending to memory system
            req->setExtraData(0);
            xc->setMiscReg(MISCREG_LLFLAG, false);
 
            // the rest of this code is not architectural;
            // it's just a debugging aid to help detect
            // livelock by warning on long sequences of failed
            // store conditionals
            int stCondFailures = xc->readStCondFailures();
            stCondFailures++;
            xc->setStCondFailures(stCondFailures);
            if (stCondFailures % 100000 == 0) {
                warn("%i: context %d: %d consecutive "
                     "store conditional failures\n",
                     curTick(), xc->contextId(), stCondFailures);
            }
 
            if (!lock_flag){
                DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, "
                              "Store Conditional Failed.\n",
                        req->contextId());
            } else if ((req->getPaddr() & ~0xf) != lock_addr) {
                DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, "
                              "Store Conditional Failed.\n",
                        req->contextId());
            }
            // store conditional failed already, so don't issue it to mem
            return false;
        }
    }
 
    return true;
}
 
template <class XC>
inline void
globalClearExclusive(XC *xc)
{
    xc->getCpuPtr()->wakeup(xc->threadId());
}
 
} // namespace MipsISA
 
#endif