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param.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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21 
22  param.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
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29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38  /***************************************/
39  /* Interface Filename: param.h */
40  /***************************************/
41 
42 #include "common.h"
43 
44 SC_MODULE( param )
45 {
46  SC_HAS_PROCESS( param );
47 
48  sc_in_clk clk;
49 
50  // Inputs
51  const sc_signal<bool>& reset;
52  const signal_bool_vector& a;
53  const signal_bool_vector& b;
54  const sc_signal<bool>& cin;
55  const sc_signal<bool>& ready;
56  // Outputs
57  signal_bool_vector& sum;
58  sc_signal<bool>& co;
59  sc_signal<bool>& done;
60  // Parameters
61  const int data_width;
62 
63  // Constructor
64  param (sc_module_name NAME,
65  sc_clock& TICK,
66  const sc_signal<bool>& RESET,
67  const signal_bool_vector& A,
68  const signal_bool_vector& B,
69  const sc_signal<bool>& CIN,
70  const sc_signal<bool>& READY,
71  signal_bool_vector& SUM,
72  sc_signal<bool>& CO,
73  sc_signal<bool>& DONE,
74  const int DATA_WIDTH = 4)
75 
76  : reset (RESET),
77  a (A),
78  b (B),
79  cin (CIN),
80  ready (READY),
81  sum (SUM),
82  co (CO),
83  done (DONE),
84  data_width (DATA_WIDTH)
85 
86  {
87  clk(TICK);
88  SC_CTHREAD( entry, clk.pos() );
89  reset_signal_is(reset,false);
90  }
91 
92  void entry();
93 };
RiscvISA::sum
Bitfield< 18 > sum
Definition: registers.hh:634
Stats::reset
void reset()
Definition: statistics.cc:299
SC_MODULE
SC_MODULE(param)
Definition: param.h:44
ArmISA::a
Bitfield< 8 > a
Definition: miscregs_types.hh:62
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
signal_bool_vector
sc_signal< bool_vector > signal_bool_vector
Definition: common.h:44
ArmISA::b
Bitfield< 7 > b
Definition: miscregs_types.hh:376
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
common.h
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