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43 #include "debug/PL111.hh"
44 #include "debug/Uart.hh"
57 :
AmbaDmaDevice(
p, 0x10000), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
58 lcdTiming3(0), lcdUpbase(0), lcdLpbase(0), lcdControl(0), lcdImsc(0),
60 clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
61 clcdCrsrPalette1(0), clcdCrsrXY(0), clcdCrsrClip(0), clcdCrsrImsc(0),
62 clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0),
63 pixelClock(
p.pixel_clock),
65 vnc(
p.vnc), bmp(&
fb), pic(NULL),
66 width(LcdMaxWidth), height(LcdMaxHeight),
67 bytesPerPixel(4), startTime(0), startAddr(0), maxAddr(0), curAddr(0),
68 waterMark(0), dmaPendingNum(0),
70 fillFifoEvent([
this]{ fillFifo(); },
name()),
71 dmaDoneEventAll(maxOutstandingDma,
this),
72 dmaDoneEventFree(maxOutstandingDma),
73 intEvent([
this]{ generateInterrupt(); },
name()),
74 enableCapture(
p.enable_capture)
76 dmaBuffer =
new uint8_t[buffer_size];
78 memset(lcdPalette, 0,
sizeof(lcdPalette));
79 memset(cursorImage, 0,
sizeof(cursorImage));
80 memset(dmaBuffer, 0, buffer_size);
82 for (
int i = 0;
i < maxOutstandingDma; ++
i)
83 dmaDoneEventFree[
i] = &dmaDoneEventAll[
i];
86 vnc->setFrameBuffer(&
fb);
108 DPRINTF(PL111,
" read register %#x size=%d\n", daddr, pkt->
getSize());
142 panic(
"LCD register at offset %#x is Write-Only\n", daddr);
172 panic(
"CLCD register at offset %#x is Write-Only\n", daddr);
185 }
else if (daddr >=
CrsrImage && daddr <= 0xBFC) {
191 }
else if (daddr >=
LcdPalette && daddr <= 0x3FC) {
198 panic(
"Tried to read CLCD register at offset %#x that "
199 "doesn't exist\n", daddr);
223 DPRINTF(PL111,
" write register %#x value %#x size=%d\n", daddr,
245 DPRINTF(PL111,
"####### Upper panel base set to: %#x #######\n",
lcdUpbase);
248 warn_once(
"LCD dual screen mode not supported\n");
270 panic(
"Interrupting on vcomp not supported\n");
279 panic(
"LCD register at offset %#x is Read-Only\n", daddr);
282 panic(
"LCD register at offset %#x is Read-Only\n", daddr);
293 panic(
"LCD register at offset %#x is Read-Only\n", daddr);
296 panic(
"LCD register at offset %#x is Read-Only\n", daddr);
323 panic(
"CLCD register at offset %#x is Read-Only\n", daddr);
326 panic(
"CLCD register at offset %#x is Read-Only\n", daddr);
329 if (daddr >=
CrsrImage && daddr <= 0xBFC) {
335 }
else if (daddr >=
LcdPalette && daddr <= 0x3FC) {
342 panic(
"Tried to write PL111 register at offset %#x that "
343 "doesn't exist\n", daddr);
376 panic(
"Unimplemented video mode\n");
382 offsets[2], offsets[1], offsets[0],
388 offsets[0], offsets[1], offsets[2],
456 assert(!
event->scheduled());
480 warn(
"CLCD controller buffer underrun, took %d ticks when should"
493 DPRINTF(PL111,
"-- write out frame buffer into bmp\n");
523 DPRINTF(PL111,
"Serializing ARM PL111\n");
543 uint8_t lcdImsc_serial =
lcdImsc;
546 uint8_t lcdRis_serial =
lcdRis;
549 uint8_t lcdMis_serial =
lcdMis;
586 Tick int_event_time = 0;
587 Tick read_event_time = 0;
588 Tick fill_fifo_event_time = 0;
613 DPRINTF(PL111,
"Unserializing ARM PL111\n");
615 uint32_t lcdTiming0_serial;
619 uint32_t lcdTiming1_serial;
623 uint32_t lcdTiming2_serial;
627 uint32_t lcdTiming3_serial;
634 uint32_t lcdControl_serial;
638 uint8_t lcdImsc_serial;
642 uint8_t lcdRis_serial;
646 uint8_t lcdMis_serial;
660 uint8_t clcdCrsrImsc_serial;
664 uint8_t clcdCrsrIcr_serial;
668 uint8_t clcdCrsrRis_serial;
672 uint8_t clcdCrsrMis_serial;
688 Tick int_event_time = 0;
689 Tick read_event_time = 0;
690 Tick fill_fifo_event_time = 0;
700 if (fill_fifo_event_time)
708 if (dma_done_event_tick[
x])
726 DPRINTF(PL111,
"Generate Interrupt: lcdImsc=0x%x lcdRis=0x%x lcdMis=0x%x\n",
732 DPRINTF(PL111,
" -- Generated\n");
AddrRangeList getAddrRanges() const override
Determine the address ranges that this device responds to.
bool scheduled() const
Determine if the current event is scheduled.
InterruptReg lcdMis
Masked interrupt status register.
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
void makeAtomicResponse()
static const int ClcdCrsrPalette0
static const int LcdTiming1
static const int ClcdCrsrImsc
void unserialize(CheckpointIn &cp) override
Unserialize an object.
#define UNSERIALIZE_SCALAR(scalar)
Configurable RGB pixel converter.
static const int LcdTiming0
ARM PL111 register map.
void copyIn(const uint8_t *fb, const PixelConverter &conv)
Fill the frame buffer with pixel data from an external buffer of the same width and height as this fr...
#define UNSERIALIZE_CONTAINER(member)
virtual void clear()=0
Clear a signalled interrupt.
uint32_t clcdCrsrCtrl
Cursor control register.
static const int LcdTiming3
static const int ClcdCrsrConfig
void resize(unsigned width, unsigned height)
Resize the frame buffer.
static const int CrsrImage
void write(std::ostream &bmp) const override
Write the frame buffer data into the provided ostream.
static const int LcdTiming2
uint32_t lcdUpbase
Upper panel frame base address register.
virtual void raise()=0
Signal an interrupt.
uint64_t Tick
Tick count type.
OutputStream * create(const std::string &name, bool binary=false, bool no_gz=false)
Creates a file in this directory (optionally compressed).
VncInput * vnc
VNC server.
TimingReg1 lcdTiming1
Vertical axis panel control register.
InterruptReg clcdCrsrMis
Cursor masked interrupt status register - const.
static const int buffer_size
Tick when() const
Get the time that the event is scheduled.
InterruptReg lcdRis
Raw interrupt status register - const.
Tick pixelClock
Pixel clock.
uint32_t waterMark
DMA FIFO watermark.
void updateVideoParams()
Send updated parameters to the vnc server.
ControlReg lcdControl
Control register.
uint16_t height
Frame buffer height - lines per panel.
uint32_t lcdPalette[LcdPaletteSize]
256x16-bit color palette registers 256 palette entries organized as 128 locations of two entries per ...
void startDma()
start the dmas off after power is enabled
uint32_t clcdCrsrClip
Cursor clip position register.
void dmaDone()
DMA done event.
ArmInterruptPin *const interrupt
static const int LcdPalette
EventFunctionWrapper fillFifoEvent
Fill fifo.
void schedule(Event &event, Tick when)
EventFunctionWrapper intEvent
Wrapper to create an event out of the interrupt.
Addr maxAddr
Frame buffer max address.
uint8_t bytesPerPixel
Bytes per pixel.
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
std::ostream * stream() const
Get the output underlying output stream.
void fillFifo()
fillFIFO event
InterruptReg clcdCrsrImsc
Cursor interrupt mask set/clear register.
static const int LcdLpCurr
uint32_t clcdCrsrXY
Cursor XY position register.
uint32_t clcdCrsrConfig
Cursor configuration register.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
AddrRange RangeSize(Addr start, Addr size)
Tick startTime
Start time for frame buffer dma read.
static const int ClcdCrsrMis
TimingReg3 lcdTiming3
Line end control register.
void setUintX(uint64_t w, ByteOrder endian)
Set the value in the word w after truncating it to the length of the packet and then byteswapping it ...
bool readId(PacketPtr pkt, uint64_t amba_id, Addr pio_addr)
static const int ClcdCrsrXY
#define SERIALIZE_ARRAY(member, size)
static const int ClcdCrsrClip
AmbaDmaDeviceParams Params
static const int LcdControl
static const int LcdUpCurr
uint32_t cursorImage[CrsrImageSize]
Cursor image RAM register 256-word wide values defining images overlaid by the hw cursor mechanism.
uint32_t lcdLpbase
Lower panel frame base address register.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
std::vector< DmaDoneEvent > dmaDoneEventAll
All pre-allocated DMA done events.
uint32_t dmaPendingNum
Number of pending dma reads.
static const int ClcdCrsrIcr
const std::string & name()
#define SERIALIZE_SCALAR(scalar)
InterruptReg lcdImsc
Interrupt mask set/clear register.
static const int ClcdCrsrPalette1
Addr curAddr
Frame buffer current address.
static const int ClcdCrsrRis
static const int ClcdCrsrCtrl
void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, uint8_t *data, Tick delay, Request::Flags flag=0)
virtual const std::string name() const
void serialize(CheckpointOut &cp) const override
Serialize an object.
static const int maxOutstandingDma
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
std::vector< DmaDoneEvent * > dmaDoneEventFree
Unused DMA done events that are ready to be scheduled.
static const int CrsrImageSize
EventFunctionWrapper readEvent
DMA framebuffer read event.
EndBitUnion(ControlReg) class DmaDoneEvent TimingReg0 lcdTiming0
Event wrapper for dmaDone()
TimingReg2 lcdTiming2
Clock and signal polarity control register.
#define UNSERIALIZE_ARRAY(member, size)
Cycles ticksToCycles(Tick t) const
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
void readFramebuffer()
DMA framebuffer read.
static const uint64_t AMBA_ID
#define SERIALIZE_CONTAINER(member)
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
@ UNCACHEABLE
The request is to an uncacheable address.
static const int LcdUpBase
OutputStream * pic
Picture of what the current frame buffer looks like.
void generateInterrupt()
Function to generate interrupt.
std::ostream CheckpointOut
Tick curTick()
The universal simulation clock.
uint8_t * dmaBuffer
CLCDC supports up to 1024x768.
uint16_t width
Frame buffer width - pixels per line.
PixelConverter pixelConverter() const
InterruptReg clcdCrsrIcr
Cursor interrupt clear register.
Addr startAddr
Frame buffer base address.
uint32_t clcdCrsrPalette1
static const int LcdPaletteSize
static const int LcdLpBase
InterruptReg clcdCrsrRis
Cursor raw interrupt status register - const.
std::string csprintf(const char *format, const Args &...args)
BmpWriter bmp
Helper to write out bitmaps.
#define panic(...)
This implements a cprintf based panic() function.
uint32_t clcdCrsrPalette0
Cursor palette registers.
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