registers.hh

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/*
 * Copyright (c) 2009 The University of Edinburgh
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
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 * redistributions in binary form must reproduce the above copyright
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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#ifndef __ARCH_POWER_REGISTERS_HH__
#define __ARCH_POWER_REGISTERS_HH__
 
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/power/miscregs.hh"
#include "base/types.hh"
 
namespace PowerISA
{
 
// Not applicable to Power
using VecElem = ::DummyVecElem;
using VecReg = ::DummyVecReg;
using ConstVecReg = ::DummyConstVecReg;
using VecRegContainer = ::DummyVecRegContainer;
constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
 
// Not applicable to Power
using VecPredReg = ::DummyVecPredReg;
using ConstVecPredReg = ::DummyConstVecPredReg;
using VecPredRegContainer = ::DummyVecPredRegContainer;
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
 
// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
// and zero register, which doesn't actually exist but needs a number
const int NumIntSpecialRegs = 9;
const int NumFloatArchRegs = 32;
 
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
const int NumFloatRegs = NumFloatArchRegs;
const int NumVecRegs = 1;  // Not applicable to Power
                           // (1 to prevent warnings)
const int NumVecPredRegs = 1;  // Not applicable to Power
                               // (1 to prevent warnings)
const int NumCCRegs = 0;
const int NumMiscRegs = NUM_MISCREGS;
 
// Semantically meaningful register indices
const int ReturnValueReg = 3;
const int StackPointerReg = 1;
 
// There isn't one in Power, but we need to define one somewhere
const int ZeroReg = NumIntRegs - 1;
 
enum MiscIntRegNums {
    INTREG_CR = NumIntArchRegs,
    INTREG_XER,
    INTREG_LR,
    INTREG_CTR,
    INTREG_FPSCR,
    INTREG_RSV,
    INTREG_RSV_LEN,
    INTREG_RSV_ADDR
};
 
} // namespace PowerISA
 
#endif // __ARCH_POWER_REGISTERS_HH__