power_state.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2015-2017, 2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __SIM_POWER_STATE_HH__
#define __SIM_POWER_STATE_HH__
 
#include <set>
#include <vector>
 
#include "base/callback.hh"
#include "base/statistics.hh"
#include "enums/PwrState.hh"
#include "params/PowerState.hh"
#include "sim/core.hh"
#include "sim/sim_object.hh"
 
class PowerDomain;
 
class PowerState : public SimObject
{
  public:
    PowerState(const PowerStateParams &p);
 
    PARAMS(PowerState);
 
    virtual void addFollower(PowerState* pwr_obj) {};
    void setControlledDomain(PowerDomain* pwr_dom);
 
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
    void set(Enums::PwrState p);
 
 
    inline Enums::PwrState get() const
    {
        return _currState;
    }
 
    inline std::string getName() const
    {
        return Enums::PwrStateStrings[_currState];
    }
 
    std::vector<double> getWeights() const;
 
    void computeStats();
 
    Enums::PwrState matchPwrState(Enums::PwrState p);
 
    std::set<Enums::PwrState> getPossibleStates() const
    {
        return possibleStates;
    }
 
  protected:
 
    Enums::PwrState _currState;
 
    std::set<Enums::PwrState> possibleStates;
 
    Tick prvEvalTick = 0;
 
    PowerDomain* controlledDomain = nullptr;
 
    struct PowerStateStats : public Stats::Group
    {
        PowerStateStats(PowerState &ps);
 
        void regStats() override;
        void preDumpStats() override;
 
        PowerState &powerState;
 
        Stats::Scalar numTransitions;
        Stats::Scalar numPwrMatchStateTransitions;
        Stats::Distribution ticksClkGated;
        Stats::Vector pwrStateResidencyTicks;
    } stats;
};
 
#endif //__SIM_POWER_STATE_HH__