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smmu_v3_caches.hh
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37 
38 #ifndef __DEV_ARM_SMMU_V3_CACHES_HH__
39 #define __DEV_ARM_SMMU_V3_CACHES_HH__
40 
41 #include <stdint.h>
42 
43 #include <array>
44 #include <cstddef>
45 #include <string>
46 #include <vector>
47 
48 #include "base/random.hh"
49 #include "base/statistics.hh"
50 #include "base/types.hh"
51 
52 #define WALK_CACHE_LEVELS 4
53 
54 enum {
58 };
59 
61 {
62  protected:
64  size_t nextToReplace;
66  uint32_t useStamp;
67 
69  {
70  SMMUv3BaseCacheStats(Stats::Group *parent, const std::string &name);
71 
74 
77 
80 
82 
85 
86  static int decodePolicyName(const std::string &policy_name);
87 
88  public:
89  SMMUv3BaseCache(const std::string &policy_name, uint32_t seed,
90  Stats::Group *parent, const std::string &name);
91  virtual ~SMMUv3BaseCache() {}
92 };
93 
94 class SMMUTLB : public SMMUv3BaseCache
95 {
96  public:
97  enum AllocPolicy {
101  };
102 
103  struct Entry
104  {
105  bool valid;
107  mutable uint32_t lastUsed;
108 
109  // TAGS
110  uint32_t sid;
111  uint32_t ssid;
114 
115  // EXTRA TAGS
116  uint16_t asid;
117  uint16_t vmid;
118 
119  // OUTPUTS
121  uint8_t permissions;
122  };
123 
124  SMMUTLB(unsigned numEntries, unsigned _associativity,
125  const std::string &policy, Stats::Group *parent,
126  const std::string &name);
127  SMMUTLB(const SMMUTLB& tlb) = delete;
128  virtual ~SMMUTLB() {}
129 
130  const Entry *lookup(uint32_t sid, uint32_t ssid, Addr va,
131  bool updStats=true);
132  const Entry *lookupAnyVA(uint32_t sid, uint32_t ssid,
133  bool updStats=true);
134  void store(const Entry &incoming, AllocPolicy alloc);
135 
136  void invalidateSSID(uint32_t sid, uint32_t ssid);
137  void invalidateSID(uint32_t sid);
138  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
139  void invalidateVAA(Addr va, uint16_t vmid);
140  void invalidateASID(uint16_t asid, uint16_t vmid);
141  void invalidateVMID(uint16_t vmid);
142  void invalidateAll();
143 
144  private:
147 
149 
150  size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
151  size_t pickSetIdx(Addr va) const;
152  size_t pickEntryIdxToReplace(const Set &set, AllocPolicy alloc);
153 };
154 
156 {
157  public:
158  struct Entry
159  {
160  bool valid;
161  mutable uint32_t lastUsed;
162 
163  // TAGS
166  uint16_t asid;
167  uint16_t vmid;
168 
169  // OUTPUTS
171  uint8_t permissions;
172  };
173 
174  ARMArchTLB(unsigned numEntries, unsigned _associativity,
175  const std::string &policy, Stats::Group *parent);
176  virtual ~ARMArchTLB() {}
177 
178  const Entry *lookup(Addr va, uint16_t asid, uint16_t vmid,
179  bool updStats=true);
180 
181  void store(const Entry &incoming);
182 
183  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid);
184  void invalidateVAA(Addr va, uint16_t vmid);
185  void invalidateASID(uint16_t asid, uint16_t vmid);
186  void invalidateVMID(uint16_t vmid);
187  void invalidateAll();
188 
189  private:
192 
194 
195  size_t pickSetIdx(Addr va, uint16_t asid, uint16_t vmid) const;
196  size_t pickEntryIdxToReplace(const Set &set);
197 };
198 
199 class IPACache : public SMMUv3BaseCache
200 {
201  public:
202  struct Entry
203  {
204  bool valid;
205  mutable uint32_t lastUsed;
206 
207  // TAGS
210  uint16_t vmid;
211 
212  // OUTPUTS
214  uint8_t permissions;
215  };
216 
217  IPACache(unsigned numEntries, unsigned _associativity,
218  const std::string &policy, Stats::Group *parent);
219  virtual ~IPACache() {}
220 
221  const Entry *lookup(Addr ipa, uint16_t vmid, bool updStats=true);
222  void store(const Entry &incoming);
223 
224  void invalidateIPA(Addr ipa, uint16_t vmid);
225  void invalidateIPAA(Addr ipa);
226  void invalidateVMID(uint16_t vmid);
227  void invalidateAll();
228 
229  private:
232 
234 
235  size_t pickSetIdx(Addr ipa, uint16_t vmid) const;
236  size_t pickEntryIdxToReplace(const Set &set);
237 };
238 
240 {
241  public:
242  struct Entry
243  {
244  bool valid;
245  mutable uint32_t lastUsed;
246 
247  // TAGS
248  uint32_t sid;
249  uint32_t ssid;
250 
251  // OUTPUTS
252  bool stage1_en;
253  bool stage2_en;
257  uint16_t asid;
258  uint16_t vmid;
259  uint8_t stage1_tg;
260  uint8_t stage2_tg;
261  uint8_t t0sz;
262  uint8_t s2t0sz;
263  };
264 
265  ConfigCache(unsigned numEntries, unsigned _associativity,
266  const std::string &policy, Stats::Group *parent);
267  virtual ~ConfigCache() {}
268 
269  const Entry *lookup(uint32_t sid, uint32_t ssid, bool updStats=true);
270  void store(const Entry &incoming);
271 
272  void invalidateSSID(uint32_t sid, uint32_t ssid);
273  void invalidateSID(uint32_t sid);
274  void invalidateAll();
275 
276  private:
279 
281 
282  size_t pickSetIdx(uint32_t sid, uint32_t ssid) const;
283  size_t pickEntryIdxToReplace(const Set &set);
284 };
285 
287 {
288  public:
289  struct Entry
290  {
291  bool valid;
292  mutable uint32_t lastUsed;
293 
294  // TAGS
297  uint16_t asid;
298  uint16_t vmid;
299  unsigned stage;
300  unsigned level;
301 
302  // OUTPUTS
303  bool leaf;
305  uint8_t permissions;
306  };
307 
308  WalkCache(const std::array<unsigned, 2*WALK_CACHE_LEVELS> &_sizes,
309  unsigned _associativity, const std::string &policy,
310  Stats::Group *parent);
311  virtual ~WalkCache() {}
312 
313  const Entry *lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid,
314  unsigned stage, unsigned level, bool updStats=true);
315  void store(const Entry &incoming);
316 
317  void invalidateVA(Addr va, uint16_t asid, uint16_t vmid,
318  const bool leaf_only);
319  void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only);
320  void invalidateASID(uint16_t asid, uint16_t vmid);
321  void invalidateVMID(uint16_t vmid);
322  void invalidateAll();
323 
324  protected:
325  struct WalkCacheStats : public Stats::Group
326  {
327  WalkCacheStats(Stats::Group *parent);
328  ~WalkCacheStats();
329 
332 
335 
338 
340 
342  } walkCacheStats;
343  private:
346 
348  std::array<unsigned, 2*WALK_CACHE_LEVELS> sizes;
349  std::array<unsigned, 2*WALK_CACHE_LEVELS> offsets;
350 
351  size_t pickSetIdx(Addr va, Addr vaMask,
352  unsigned stage, unsigned level) const;
353 
354  size_t pickEntryIdxToReplace(const Set &set,
355  unsigned stage, unsigned level);
356 };
357 
358 #endif /* __DEV_ARM_SMMU_V3_CACHES_HH__ */
ConfigCache::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:277
WalkCache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:292
IPACache::invalidateIPAA
void invalidateIPAA(Addr ipa)
Definition: smmu_v3_caches.cc:723
SMMUTLB::lookup
const Entry * lookup(uint32_t sid, uint32_t ssid, Addr va, bool updStats=true)
Definition: smmu_v3_caches.cc:178
IPACache::Entry::ipaMask
Addr ipaMask
Definition: smmu_v3_caches.hh:209
ConfigCache::Entry::stage2_tg
uint8_t stage2_tg
Definition: smmu_v3_caches.hh:260
IPACache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:205
WalkCache::lookup
const Entry * lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level, bool updStats=true)
Definition: smmu_v3_caches.cc:1015
ConfigCache::invalidateSSID
void invalidateSSID(uint32_t sid, uint32_t ssid)
Definition: smmu_v3_caches.cc:889
WalkCache::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:291
WalkCache::pickSetIdx
size_t pickSetIdx(Addr va, Addr vaMask, unsigned stage, unsigned level) const
Definition: smmu_v3_caches.cc:1163
IPACache::lookup
const Entry * lookup(Addr ipa, uint16_t vmid, bool updStats=true)
Definition: smmu_v3_caches.cc:657
WalkCache::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:345
SMMUv3BaseCache::SMMUv3BaseCache
SMMUv3BaseCache(const std::string &policy_name, uint32_t seed, Stats::Group *parent, const std::string &name)
Definition: smmu_v3_caches.cc:61
WalkCache::Entry::level
unsigned level
Definition: smmu_v3_caches.hh:300
IPACache::IPACache
IPACache(unsigned numEntries, unsigned _associativity, const std::string &policy, Stats::Group *parent)
Definition: smmu_v3_caches.cc:627
IPACache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:690
SMMUv3BaseCache::~SMMUv3BaseCache
virtual ~SMMUv3BaseCache()
Definition: smmu_v3_caches.hh:91
IPACache::invalidateIPA
void invalidateIPA(Addr ipa, uint16_t vmid)
Definition: smmu_v3_caches.cc:710
SMMUTLB::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:146
WalkCache::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:344
ConfigCache::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:258
ARMArchTLB::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:167
ARMArchTLB::ARMArchTLB
ARMArchTLB(unsigned numEntries, unsigned _associativity, const std::string &policy, Stats::Group *parent)
Definition: smmu_v3_caches.cc:428
SMMUTLB::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:121
ARMArchTLB::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:160
SMMU_CACHE_REPL_RANDOM
@ SMMU_CACHE_REPL_RANDOM
Definition: smmu_v3_caches.hh:56
SMMUv3BaseCache::SMMUv3BaseCacheStats::SMMUv3BaseCacheStats
SMMUv3BaseCacheStats(Stats::Group *parent, const std::string &name)
Definition: smmu_v3_caches.cc:85
SMMUv3BaseCache
Definition: smmu_v3_caches.hh:60
random.hh
ConfigCache::Entry::httb
Addr httb
Definition: smmu_v3_caches.hh:256
WalkCache::WalkCacheStats::WalkCacheStats
WalkCacheStats(Stats::Group *parent)
Definition: smmu_v3_caches.cc:1227
ConfigCache::ConfigCache
ConfigCache(unsigned numEntries, unsigned _associativity, const std::string &policy, Stats::Group *parent)
Definition: smmu_v3_caches.cc:807
SMMUTLB::invalidateVMID
void invalidateVMID(uint16_t vmid)
Definition: smmu_v3_caches.cc:332
ConfigCache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:280
SMMUv3BaseCache::SMMUv3BaseCacheStats::totalUpdates
Stats::Scalar totalUpdates
Definition: smmu_v3_caches.hh:79
WalkCache::WalkCacheStats::insertionsByStageLevel
Stats::Vector2d insertionsByStageLevel
Definition: smmu_v3_caches.hh:341
SMMUTLB::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:117
WalkCache::Entry::pa
Addr pa
Definition: smmu_v3_caches.hh:304
WalkCache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:1056
WalkCache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:1152
ConfigCache::Entry::s2t0sz
uint8_t s2t0sz
Definition: smmu_v3_caches.hh:262
std::vector< Entry >
IPACache::~IPACache
virtual ~IPACache()
Definition: smmu_v3_caches.hh:219
SMMUTLB::SMMUTLB
SMMUTLB(unsigned numEntries, unsigned _associativity, const std::string &policy, Stats::Group *parent, const std::string &name)
Definition: smmu_v3_caches.cc:147
WalkCache::Entry
Definition: smmu_v3_caches.hh:289
ConfigCache::Entry::t0sz
uint8_t t0sz
Definition: smmu_v3_caches.hh:261
ConfigCache::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:869
SMMUTLB::pickSetIdx
size_t pickSetIdx(uint32_t sid, uint32_t ssid) const
Definition: smmu_v3_caches.cc:364
WalkCache::WalkCacheStats::totalUpdatesByStageLevel
Stats::Vector2d totalUpdatesByStageLevel
Definition: smmu_v3_caches.hh:337
SMMUv3BaseCache::useStamp
uint32_t useStamp
Definition: smmu_v3_caches.hh:66
WalkCache::sizes
std::array< unsigned, 2 *WALK_CACHE_LEVELS > sizes
Definition: smmu_v3_caches.hh:348
SMMUTLB::Entry::va
Addr va
Definition: smmu_v3_caches.hh:112
ARMArchTLB::lookup
const Entry * lookup(Addr va, uint16_t asid, uint16_t vmid, bool updStats=true)
Definition: smmu_v3_caches.cc:458
SMMUTLB::invalidateSSID
void invalidateSSID(uint32_t sid, uint32_t ssid)
Definition: smmu_v3_caches.cc:260
SMMU_CACHE_REPL_LRU
@ SMMU_CACHE_REPL_LRU
Definition: smmu_v3_caches.hh:57
WalkCache::Entry::vaMask
Addr vaMask
Definition: smmu_v3_caches.hh:296
ARMArchTLB::Entry::vaMask
Addr vaMask
Definition: smmu_v3_caches.hh:165
WalkCache::Entry::asid
uint16_t asid
Definition: smmu_v3_caches.hh:297
SMMUTLB::Entry
Definition: smmu_v3_caches.hh:103
SMMUTLB::invalidateVA
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:288
SMMUTLB::ALLOC_ANY_WAY
@ ALLOC_ANY_WAY
Definition: smmu_v3_caches.hh:98
WalkCache::invalidateVAA
void invalidateVAA(Addr va, uint16_t vmid, const bool leaf_only)
Definition: smmu_v3_caches.cc:1104
IPACache::Entry::vmid
uint16_t vmid
Definition: smmu_v3_caches.hh:210
ConfigCache::Entry::stage1_en
bool stage1_en
Definition: smmu_v3_caches.hh:252
Stats::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1933
IPACache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:233
ARMArchTLB::~ARMArchTLB
virtual ~ARMArchTLB()
Definition: smmu_v3_caches.hh:176
IPACache::Entry
Definition: smmu_v3_caches.hh:202
SMMUTLB::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:347
SMMUTLB::Entry::asid
uint16_t asid
Definition: smmu_v3_caches.hh:116
SMMUTLB::invalidateVAA
void invalidateVAA(Addr va, uint16_t vmid)
Definition: smmu_v3_caches.cc:304
SMMUTLB::AllocPolicy
AllocPolicy
Definition: smmu_v3_caches.hh:97
WalkCache::invalidateVA
void invalidateVA(Addr va, uint16_t asid, uint16_t vmid, const bool leaf_only)
Definition: smmu_v3_caches.cc:1085
ARMArchTLB::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:190
SMMUv3BaseCache::nextToReplace
size_t nextToReplace
Definition: smmu_v3_caches.hh:64
SMMUv3BaseCache::random
Random random
Definition: smmu_v3_caches.hh:65
Random
Definition: random.hh:58
ARMArchTLB::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:171
ARMArchTLB::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:161
SMMUTLB::ALLOC_ANY_BUT_LAST_WAY
@ ALLOC_ANY_BUT_LAST_WAY
Definition: smmu_v3_caches.hh:99
ConfigCache
Definition: smmu_v3_caches.hh:239
SMMUTLB::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:107
SMMUTLB::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:317
WalkCache::Entry::stage
unsigned stage
Definition: smmu_v3_caches.hh:299
SMMUTLB
Definition: smmu_v3_caches.hh:94
WalkCache::WalkCache
WalkCache(const std::array< unsigned, 2 *WALK_CACHE_LEVELS > &_sizes, unsigned _associativity, const std::string &policy, Stats::Group *parent)
Definition: smmu_v3_caches.cc:971
ConfigCache::Entry::sid
uint32_t sid
Definition: smmu_v3_caches.hh:248
statistics.hh
WalkCache::WalkCacheStats
Definition: smmu_v3_caches.hh:325
IPACache::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:214
IPACache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:753
ConfigCache::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:244
SMMUTLB::ALLOC_LAST_WAY
@ ALLOC_LAST_WAY
Definition: smmu_v3_caches.hh:100
WalkCache::WalkCacheStats::totalLookupsByStageLevel
Stats::Vector2d totalLookupsByStageLevel
Definition: smmu_v3_caches.hh:331
WalkCache::~WalkCache
virtual ~WalkCache()
Definition: smmu_v3_caches.hh:311
ConfigCache::lookup
const Entry * lookup(uint32_t sid, uint32_t ssid, bool updStats=true)
Definition: smmu_v3_caches.cc:837
SMMUTLB::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:145
ARMArchTLB::store
void store(const Entry &incoming)
Definition: smmu_v3_caches.cc:491
ConfigCache::Entry::ssid
uint32_t ssid
Definition: smmu_v3_caches.hh:249
ARMArchTLB::Entry
Definition: smmu_v3_caches.hh:158
IPACache::Set
std::vector< Entry > Set
Definition: smmu_v3_caches.hh:230
IPACache::Entry::ipa
Addr ipa
Definition: smmu_v3_caches.hh:208
ConfigCache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set)
Definition: smmu_v3_caches.cc:934
WalkCache::WalkCacheStats::~WalkCacheStats
~WalkCacheStats()
Definition: smmu_v3_caches.cc:1316
SMMUv3BaseCache::SMMUv3BaseCacheStats::averageMisses
Stats::Formula averageMisses
Definition: smmu_v3_caches.hh:75
IPACache::pickSetIdx
size_t pickSetIdx(Addr ipa, uint16_t vmid) const
Definition: smmu_v3_caches.cc:764
IPACache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set)
Definition: smmu_v3_caches.cc:770
ConfigCache::Entry::ttb1
Addr ttb1
Definition: smmu_v3_caches.hh:255
ConfigCache::Entry::ttb0
Addr ttb0
Definition: smmu_v3_caches.hh:254
WalkCache::WalkCacheStats::averageUpdatesByStageLevel
std::vector< Stats::Formula * > averageUpdatesByStageLevel
Definition: smmu_v3_caches.hh:336
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
WalkCache::Entry::permissions
uint8_t permissions
Definition: smmu_v3_caches.hh:305
WalkCache::walkCacheStats
WalkCache::WalkCacheStats walkCacheStats
name
const std::string & name()
Definition: trace.cc:48
ConfigCache::Entry::lastUsed
uint32_t lastUsed
Definition: smmu_v3_caches.hh:245
SMMUv3BaseCache::SMMUv3BaseCacheStats::insertions
Stats::Scalar insertions
Definition: smmu_v3_caches.hh:83
WalkCache::associativity
size_t associativity
Definition: smmu_v3_caches.hh:347
ARMArchTLB::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set)
Definition: smmu_v3_caches.cc:590
WalkCache::Entry::va
Addr va
Definition: smmu_v3_caches.hh:295
IPACache::invalidateVMID
void invalidateVMID(uint16_t vmid)
Definition: smmu_v3_caches.cc:738
ArmISA::asid
asid
Definition: miscregs_types.hh:611
WalkCache::pickEntryIdxToReplace
size_t pickEntryIdxToReplace(const Set &set, unsigned stage, unsigned level)
Definition: smmu_v3_caches.cc:1191
WalkCache::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:1122
SMMUv3BaseCache::SMMUv3BaseCacheStats::averageUpdates
Stats::Formula averageUpdates
Definition: smmu_v3_caches.hh:78
ConfigCache::invalidateSID
void invalidateSID(uint32_t sid)
Definition: smmu_v3_caches.cc:902
ConfigCache::sets
std::vector< Set > sets
Definition: smmu_v3_caches.hh:278
X86ISA::level
Bitfield< 20 > level
Definition: intmessage.hh:47
ARMArchTLB::invalidateASID
void invalidateASID(uint16_t asid, uint16_t vmid)
Definition: smmu_v3_caches.cc:543
ConfigCache::invalidateAll
void invalidateAll()
Definition: smmu_v3_caches.cc:917
SMMUTLB::Entry::ssid
uint32_t ssid
Definition: smmu_v3_caches.hh:111
IPACache::Entry::valid
bool valid
Definition: smmu_v3_caches.hh:204
Stats::Vector2d
A 2-Dimensional vecto of scalar stats.
Definition: statistics.hh:2058
SMMUv3BaseCache::baseCacheStats
SMMUv3BaseCache::SMMUv3BaseCacheStats baseCacheStats
ARMArchTLB::Entry::asid
uint16_t asid
Definition: smmu_v3_caches.hh:166
WalkCache
Definition: smmu_v3_caches.hh:286
SMMUv3BaseCache::SMMUv3BaseCacheStats::averageLookups
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Definition: smmu_v3_caches.hh:72
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Definition: smmu_v3_caches.cc:239
types.hh
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Definition: smmu_v3_caches.cc:273
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Definition: smmu_v3_caches.hh:63
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Definition: smmu_v3_caches.cc:71
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Definition: smmu_v3_caches.hh:106
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A formula for statistics that is calculated when printed.
Definition: statistics.hh:2538
SMMUv3BaseCache::SMMUv3BaseCacheStats::averageHitRate
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Definition: smmu_v3_caches.hh:81
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Definition: group.hh:87
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Definition: smmu_v3_caches.cc:528
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Definition: smmu_v3_caches.cc:370
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Definition: smmu_v3_caches.hh:191
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Definition: smmu_v3_caches.hh:231
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Definition: smmu_v3_caches.hh:164
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Definition: smmu_v3_caches.hh:113
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Definition: smmu_v3_caches.hh:199
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Definition: smmu_v3_caches.hh:155
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Definition: smmu_v3_caches.hh:213
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Definition: smmu_v3_caches.hh:259
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Definition: smmu_v3_caches.hh:73
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Definition: smmu_v3_caches.hh:193
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Definition: smmu_v3_caches.hh:68
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Definition: smmu_v3_caches.hh:105
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Definition: smmu_v3_caches.cc:573
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Definition: smmu_v3_caches.hh:349
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Definition: smmu_v3_caches.cc:558
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Definition: smmu_v3_caches.hh:339
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Definition: smmu_v3_caches.cc:584
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Definition: smmu_v3_caches.hh:333
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Definition: smmu_v3_caches.hh:298
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Definition: smmu_v3_caches.hh:76
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Definition: smmu_v3_caches.cc:512
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Definition: smmu_v3_caches.hh:110
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Definition: smmu_v3_caches.hh:303
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Definition: smmu_v3_caches.hh:148
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Definition: smmu_v3_caches.cc:928
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Definition: smmu_v3_caches.hh:120
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Definition: smmu_v3_caches.hh:267
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Definition: smmu_v3_caches.hh:242
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Definition: smmu_v3_caches.hh:253
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Definition: miscregs_types.hh:88
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Definition: smmu_v3_caches.hh:128
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Definition: smmu_v3_caches.hh:170
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Definition: smmu_v3_caches.hh:334
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Definition: smmu_v3_caches.hh:330
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@ SMMU_CACHE_REPL_ROUND_ROBIN
Definition: smmu_v3_caches.hh:55
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Definition: miscregs_types.hh:272
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Definition: smmu_v3_caches.cc:1137
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Definition: smmu_v3_caches.hh:257
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Definition: smmu_v3_caches.cc:212

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