gem5
v21.0.0.0
Main Page
Related Pages
Modules
Namespaces
Namespace List
Namespace Members
All
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Functions
_
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
Variables
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Typedefs
a
c
d
e
f
g
h
i
m
n
o
p
r
s
t
u
v
w
x
Enumerations
a
c
d
e
f
i
l
m
o
p
r
s
t
v
x
Enumerator
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Classes
Class List
Class Index
Class Hierarchy
Class Members
All
:
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
~
Functions
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
~
Variables
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
y
z
Typedefs
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
y
Enumerations
a
b
c
d
e
f
g
h
i
l
m
n
o
p
r
s
t
u
w
Enumerator
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Related Functions
:
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
Files
File List
File Members
All
_
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
Functions
_
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
z
Variables
_
a
b
c
d
e
f
g
h
i
j
l
m
n
o
p
r
s
t
u
v
Typedefs
_
a
b
c
d
e
f
g
h
i
l
m
n
o
p
q
r
s
t
u
v
w
Enumerations
_
a
b
c
d
e
f
g
h
i
l
m
o
p
q
r
s
t
v
Enumerator
_
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
Macros
_
a
b
c
d
e
f
g
h
i
k
l
m
n
o
p
q
r
s
t
u
v
w
x
z
•
All
Classes
Namespaces
Files
Functions
Variables
Typedefs
Enumerations
Enumerator
Friends
Macros
Modules
Pages
arch
sparc
decoder.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2012 Google
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are
7
* met: redistributions of source code must retain the above copyright
8
* notice, this list of conditions and the following disclaimer;
9
* redistributions in binary form must reproduce the above copyright
10
* notice, this list of conditions and the following disclaimer in the
11
* documentation and/or other materials provided with the distribution;
12
* neither the name of the copyright holders nor the names of its
13
* contributors may be used to endorse or promote products derived from
14
* this software without specific prior written permission.
15
*
16
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
*/
28
29
#ifndef __ARCH_SPARC_DECODER_HH__
30
#define __ARCH_SPARC_DECODER_HH__
31
32
#include "
arch/generic/decode_cache.hh
"
33
#include "
arch/generic/decoder.hh
"
34
#include "
arch/sparc/registers.hh
"
35
#include "
arch/sparc/types.hh
"
36
#include "
cpu/static_inst.hh
"
37
#include "debug/Decode.hh"
38
39
namespace
SparcISA
40
{
41
42
class
ISA;
43
class
Decoder
:
public
InstDecoder
44
{
45
protected
:
46
// The extended machine instruction being generated
47
ExtMachInst
emi
;
48
bool
instDone
;
49
RegVal
asi
;
50
51
public
:
52
Decoder
(
ISA
* isa =
nullptr
) :
instDone
(false),
asi
(0)
53
{}
54
55
void
process
() {}
56
57
void
58
reset
()
59
{
60
instDone
=
false
;
61
}
62
63
// Use this to give data to the predecoder. This should be used
64
// when there is control flow.
65
void
66
moreBytes
(
const
PCState
&
pc
,
Addr
fetchPC,
MachInst
inst)
67
{
68
emi
=
betoh
(inst);
69
// The I bit, bit 13, is used to figure out where the ASI
70
// should come from. Use that in the ExtMachInst. This is
71
// slightly redundant, but it removes the need to put a condition
72
// into all the execute functions
73
if
(
emi
& (1 << 13)) {
74
emi
|= (
static_cast<
ExtMachInst
>
(
75
asi
<< (
sizeof
(
MachInst
) * 8)));
76
}
else
{
77
emi
|= (
static_cast<
ExtMachInst
>
(
bits
(
emi
, 12, 5))
78
<< (
sizeof
(
MachInst
) * 8));
79
}
80
instDone
=
true
;
81
}
82
83
bool
84
needMoreBytes
()
85
{
86
return
true
;
87
}
88
89
bool
90
instReady
()
91
{
92
return
instDone
;
93
}
94
95
void
96
setContext
(
RegVal
_asi)
97
{
98
asi
= _asi;
99
}
100
101
void
takeOverFrom
(
Decoder
*old) {}
102
103
protected
:
105
static
GenericISA::BasicDecodeCache<Decoder, ExtMachInst>
defaultCache
;
106
107
public
:
108
StaticInstPtr
decodeInst
(
ExtMachInst
mach_inst);
109
113
StaticInstPtr
114
decode
(
ExtMachInst
mach_inst,
Addr
addr
)
115
{
116
StaticInstPtr
si
=
defaultCache
.decode(
this
, mach_inst,
addr
);
117
DPRINTF
(Decode,
"Decode: Decoded %s instruction: %#x\n"
,
118
si
->getName(), mach_inst);
119
return
si
;
120
}
121
122
StaticInstPtr
123
decode
(
SparcISA::PCState
&nextPC)
124
{
125
if
(!
instDone
)
126
return
NULL;
127
instDone
=
false
;
128
return
decode
(
emi
, nextPC.
instAddr
());
129
}
130
};
131
132
}
// namespace SparcISA
133
134
#endif // __ARCH_SPARC_DECODER_HH__
SparcISA::MachInst
uint32_t MachInst
Definition:
types.hh:38
SparcISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Definition:
decoder.hh:66
SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition:
types.hh:39
SparcISA::Decoder::reset
void reset()
Definition:
decoder.hh:58
SparcISA::Decoder::takeOverFrom
void takeOverFrom(Decoder *old)
Definition:
decoder.hh:101
SparcISA::Decoder::asi
RegVal asi
Definition:
decoder.hh:49
decode_cache.hh
SparcISA::Decoder::emi
ExtMachInst emi
Definition:
decoder.hh:47
ArmISA::si
Bitfield< 6 > si
Definition:
miscregs_types.hh:766
SparcISA::Decoder::needMoreBytes
bool needMoreBytes()
Definition:
decoder.hh:84
GenericISA::DelaySlotUPCState
Definition:
types.hh:391
GenericISA::BasicDecodeCache
Definition:
decode_cache.hh:40
SparcISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition:
decoder.hh:52
SparcISA
Definition:
asi.cc:31
decoder.hh
SparcISA::Decoder::decode
StaticInstPtr decode(SparcISA::PCState &nextPC)
Definition:
decoder.hh:123
DPRINTF
#define DPRINTF(x,...)
Definition:
trace.hh:237
MipsISA::pc
Bitfield< 4 > pc
Definition:
pra_constants.hh:240
SparcISA::Decoder::instDone
bool instDone
Definition:
decoder.hh:48
SparcISA::Decoder
Definition:
decoder.hh:43
SparcISA::Decoder::process
void process()
Definition:
decoder.hh:55
static_inst.hh
GenericISA::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition:
types.hh:80
types.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:148
betoh
T betoh(T value)
Definition:
byteswap.hh:144
X86ISA::addr
Bitfield< 3 > addr
Definition:
types.hh:80
SparcISA::Decoder::setContext
void setContext(RegVal _asi)
Definition:
decoder.hh:96
SparcISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition:
decoder.hh:105
bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition:
bitfield.hh:73
InstDecoder
Definition:
decoder.hh:34
registers.hh
RefCountingPtr< StaticInst >
SparcISA::ISA
Definition:
isa.hh:48
SparcISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition:
decoder.hh:114
SparcISA::Decoder::instReady
bool instReady()
Definition:
decoder.hh:90
RegVal
uint64_t RegVal
Definition:
types.hh:174
SparcISA::Decoder::decodeInst
StaticInstPtr decodeInst(ExtMachInst mach_inst)
Generated on Tue Mar 23 2021 19:41:18 for gem5 by
doxygen
1.8.17