gem5  v21.0.0.0
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
tlm_to_gem5.cc
Go to the documentation of this file.
1 /*
2  * Copyright 2019 Google, Inc.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are
6  * met: redistributions of source code must retain the above copyright
7  * notice, this list of conditions and the following disclaimer;
8  * redistributions in binary form must reproduce the above copyright
9  * notice, this list of conditions and the following disclaimer in the
10  * documentation and/or other materials provided with the distribution;
11  * neither the name of the copyright holders nor the names of its
12  * contributors may be used to endorse or promote products derived from
13  * this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
28  * All rights reserved.
29  *
30  * Redistribution and use in source and binary forms, with or without
31  * modification, are permitted provided that the following conditions are
32  * met:
33  *
34  * 1. Redistributions of source code must retain the above copyright notice,
35  * this list of conditions and the following disclaimer.
36  *
37  * 2. Redistributions in binary form must reproduce the above copyright
38  * notice, this list of conditions and the following disclaimer in the
39  * documentation and/or other materials provided with the distribution.
40  *
41  * 3. Neither the name of the copyright holder nor the names of its
42  * contributors may be used to endorse or promote products derived from
43  * this software without specific prior written permission.
44  *
45  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
46  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
47  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
48  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
49  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
50  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
51  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
52  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
55  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56  */
57 
59 
60 #include <utility>
61 
62 #include "params/TlmToGem5Bridge32.hh"
63 #include "params/TlmToGem5Bridge64.hh"
64 #include "sim/system.hh"
67 
68 namespace sc_gem5
69 {
70 
71 namespace
72 {
76 std::vector<PayloadToPacketConversionStep> extraPayloadToPacketSteps;
77 } // namespace
78 
86 void
88 {
89  extraPayloadToPacketSteps.push_back(std::move(step));
90 }
91 
94 {
95  MemCmd cmd;
96 
97  switch (trans.get_command()) {
99  cmd = MemCmd::ReadReq;
100  break;
102  cmd = MemCmd::WriteReq;
103  break;
105  return nullptr;
106  default:
107  SC_REPORT_FATAL("TlmToGem5Bridge",
108  "received transaction with unsupported command");
109  }
110 
111  Request::Flags flags;
112  auto req = std::make_shared<Request>(
113  trans.get_address(), trans.get_data_length(), flags, _id);
114 
115  /*
116  * Allocate a new Packet. The packet will be deleted when it returns from
117  * the gem5 world as a response.
118  */
119  auto pkt = new Packet(req, cmd);
120  pkt->dataStatic(trans.get_data_ptr());
121 
122  // Apply all conversion steps necessary in this specific setup.
123  for (auto &step : extraPayloadToPacketSteps) {
124  step(pkt, trans);
125  }
126 
127  return pkt;
128 }
129 
130 template <unsigned int BITWIDTH>
131 void
133 {
135  auto delay = sc_core::SC_ZERO_TIME;
136 
137  auto status = socket->nb_transport_bw(trans, phase, delay);
139  "Unexpected status after sending END_REQ");
140 }
141 
142 template <unsigned int BITWIDTH>
143 void
145  sc_core::sc_time &delay)
146 {
148 
150 
151  auto status = socket->nb_transport_bw(trans, phase, delay);
152 
153  if (status == tlm::TLM_COMPLETED ||
154  (status == tlm::TLM_UPDATED && phase == tlm::END_RESP)) {
155  // transaction completed -> no need to wait for tlm::END_RESP
156  responseInProgress = false;
157  } else if (status == tlm::TLM_ACCEPTED) {
158  // we need to wait for tlm::END_RESP
159  responseInProgress = true;
160  } else {
161  panic("Unexpected status after sending BEGIN_RESP");
162  }
163 }
164 
165 template <unsigned int BITWIDTH>
166 void
168 {
169  sc_assert(!waitForRetry);
170  sc_assert(pendingRequest == nullptr);
171  sc_assert(pendingPacket == nullptr);
172 
173  trans.acquire();
174 
175  PacketPtr pkt = nullptr;
176 
177  Gem5SystemC::Gem5Extension *extension = nullptr;
178  trans.get_extension(extension);
179 
180  // If there is an extension, this transaction was initiated by the gem5
181  // world and we can pipe through the original packet. Otherwise, we
182  // generate a new packet based on the transaction.
183  if (extension != nullptr) {
184  pkt = extension->getPacket();
185  } else {
186  pkt = payload2packet(_id, trans);
187  }
188 
189  auto tlmSenderState = new TlmSenderState(trans);
190  pkt->pushSenderState(tlmSenderState);
191 
192  // If the packet doesn't need a response, we should send BEGIN_RESP by
193  // ourselves.
194  bool needsResponse = pkt->needsResponse();
195  if (bmp.sendTimingReq(pkt)) { // port is free -> send END_REQ immediately
196  sendEndReq(trans);
197  if (!needsResponse) {
198  auto delay = sc_core::SC_ZERO_TIME;
199  sendBeginResp(trans, delay);
200  }
201  trans.release();
202  } else { // port is blocked -> wait for retry before sending END_REQ
203  waitForRetry = true;
204  pendingRequest = &trans;
205  pendingPacket = pkt;
206  }
207 }
208 
209 template <unsigned int BITWIDTH>
210 void
212 {
213  sc_assert(responseInProgress);
214 
215  responseInProgress = false;
216 
217  checkTransaction(trans);
218 
219  if (needToSendRetry) {
220  bmp.sendRetryResp();
221  needToSendRetry = false;
222  }
223 }
224 
225 template <unsigned int BITWIDTH>
226 void
228 {
229  delete pkt;
230 }
231 
232 template <unsigned int BITWIDTH>
233 void
235 {
236  if (trans.is_response_error()) {
237  std::stringstream ss;
238  ss << "Transaction returned with error, response status = "
239  << trans.get_response_string();
240  SC_REPORT_ERROR("TLM-2", ss.str().c_str());
241  }
242 }
243 
244 template <unsigned int BITWIDTH>
245 void
246 TlmToGem5Bridge<BITWIDTH>::invalidateDmi(const ::MemBackdoor &backdoor)
247 {
248  socket->invalidate_direct_mem_ptr(
249  backdoor.range().start(), backdoor.range().end());
250 }
251 
252 template <unsigned int BITWIDTH>
253 void
255  const tlm::tlm_phase &phase)
256 {
257  switch (phase) {
258  case tlm::BEGIN_REQ:
259  handleBeginReq(trans);
260  break;
261  case tlm::END_RESP:
262  handleEndResp(trans);
263  break;
264  default:
265  panic("unimplemented phase in callback");
266  }
267 }
268 
269 template <unsigned int BITWIDTH>
273  sc_core::sc_time &delay)
274 {
275  unsigned len = trans.get_data_length();
276  unsigned char *byteEnable = trans.get_byte_enable_ptr();
277  unsigned width = trans.get_streaming_width();
278 
279  // check the transaction attributes for unsupported features ...
280  if (byteEnable != 0) {
282  return tlm::TLM_COMPLETED;
283  }
284  if (width < len) { // is this a burst request?
286  return tlm::TLM_COMPLETED;
287  }
288 
289  // ... and queue the valid transaction
290  trans.acquire();
291  peq.notify(trans, phase, delay);
292  return tlm::TLM_ACCEPTED;
293 }
294 
295 template <unsigned int BITWIDTH>
296 void
299 {
300  Gem5SystemC::Gem5Extension *extension = nullptr;
301  trans.get_extension(extension);
302 
303  PacketPtr pkt = nullptr;
304 
305  // If there is an extension, this transaction was initiated by the gem5
306  // world and we can pipe through the original packet.
307  if (extension != nullptr) {
308  pkt = extension->getPacket();
309  } else {
310  pkt = payload2packet(_id, trans);
311  }
312 
313  MemBackdoorPtr backdoor = nullptr;
314  Tick ticks = bmp.sendAtomicBackdoor(pkt, backdoor);
315  if (backdoor)
316  trans.set_dmi_allowed(true);
317 
318  // send an atomic request to gem5
319  panic_if(pkt->needsResponse() && !pkt->isResponse(),
320  "Packet sending failed!\n");
321 
322  auto delay =
324 
325  // update time
326  t += delay;
327 
328  if (extension == nullptr)
329  destroyPacket(pkt);
330 
332 }
333 
334 template <unsigned int BITWIDTH>
335 unsigned int
337 {
338  Gem5SystemC::Gem5Extension *extension = nullptr;
339  trans.get_extension(extension);
340 
341  // If there is an extension, this transaction was initiated by the gem5
342  // world and we can pipe through the original packet.
343  if (extension != nullptr) {
344  bmp.sendFunctional(extension->getPacket());
345  } else {
346  auto pkt = payload2packet(_id, trans);
347  if (pkt) {
348  bmp.sendFunctional(pkt);
349  destroyPacket(pkt);
350  }
351  }
352 
353  return trans.get_data_length();
354 }
355 
356 template <unsigned int BITWIDTH>
357 bool
359  tlm::tlm_dmi &dmi_data)
360 {
361  Gem5SystemC::Gem5Extension *extension = nullptr;
362  trans.get_extension(extension);
363 
364  PacketPtr pkt = nullptr;
365 
366  // If there is an extension, this transaction was initiated by the gem5
367  // world and we can pipe through the original packet.
368  if (extension != nullptr) {
369  pkt = extension->getPacket();
370  } else {
371  pkt = payload2packet(_id, trans);
372  pkt->req->setFlags(Request::NO_ACCESS);
373  }
374 
375  MemBackdoorPtr backdoor = nullptr;
376  bmp.sendAtomicBackdoor(pkt, backdoor);
377  if (backdoor) {
378  trans.set_dmi_allowed(true);
379  dmi_data.set_dmi_ptr(backdoor->ptr());
380  dmi_data.set_start_address(backdoor->range().start());
381  dmi_data.set_end_address(backdoor->range().end());
382 
383  typedef tlm::tlm_dmi::dmi_access_e access_t;
384  access_t access = tlm::tlm_dmi::DMI_ACCESS_NONE;
385  if (backdoor->readable())
386  access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_READ);
387  if (backdoor->writeable())
388  access = (access_t)(access | tlm::tlm_dmi::DMI_ACCESS_WRITE);
389  dmi_data.set_granted_access(access);
390 
391  backdoor->addInvalidationCallback(
392  [this](const MemBackdoor &backdoor)
393  {
394  invalidateDmi(backdoor);
395  }
396  );
397  }
398 
399  if (extension == nullptr)
400  destroyPacket(pkt);
401 
403 
404  return backdoor != nullptr;
405 }
406 
407 template <unsigned int BITWIDTH>
408 bool
410 {
411  // exclusion rule
412  // We need to Wait for END_RESP before sending next BEGIN_RESP
413  if (responseInProgress) {
414  sc_assert(!needToSendRetry);
415  needToSendRetry = true;
416  return false;
417  }
418 
419  sc_assert(pkt->isResponse());
420 
421  /*
422  * Pay for annotated transport delays.
423  *
424  * See recvTimingReq in sc_slave_port.cc for a detailed description.
425  */
426  auto delay = sc_core::sc_time::from_value(pkt->payloadDelay);
427  // reset the delays
428  pkt->payloadDelay = 0;
429  pkt->headerDelay = 0;
430 
431  auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
432  sc_assert(tlmSenderState != nullptr);
433 
434  auto &trans = tlmSenderState->trans;
435 
436  Gem5SystemC::Gem5Extension *extension = nullptr;
437  trans.get_extension(extension);
438 
439  // clean up
440  delete tlmSenderState;
441 
442  // If there is an extension the packet was piped through and we must not
443  // delete it. The packet travels back with the transaction.
444  if (extension == nullptr)
445  destroyPacket(pkt);
446 
447  sendBeginResp(trans, delay);
448  trans.release();
449 
450  return true;
451 }
452 
453 template <unsigned int BITWIDTH>
454 void
456 {
457  sc_assert(waitForRetry);
458  sc_assert(pendingRequest != nullptr);
459  sc_assert(pendingPacket != nullptr);
460 
461  // If the packet doesn't need a response, we should send BEGIN_RESP by
462  // ourselves.
463  bool needsResponse = pendingPacket->needsResponse();
464  if (bmp.sendTimingReq(pendingPacket)) {
465  waitForRetry = false;
466  pendingPacket = nullptr;
467 
468  auto &trans = *pendingRequest;
469  sendEndReq(trans);
470  if (!needsResponse) {
471  auto delay = sc_core::SC_ZERO_TIME;
472  sendBeginResp(trans, delay);
473  }
474  trans.release();
475 
476  pendingRequest = nullptr;
477  }
478 }
479 
480 template <unsigned int BITWIDTH>
481 void
483 {
484  SC_REPORT_WARNING("TlmToGem5Bridge",
485  "received address range change but ignored it");
486 }
487 
488 template <unsigned int BITWIDTH>
489 ::Port &
490 TlmToGem5Bridge<BITWIDTH>::gem5_getPort(const std::string &if_name, int idx)
491 {
492  if (if_name == "gem5")
493  return bmp;
494  else if (if_name == "tlm")
495  return wrapper;
496 
497  return sc_core::sc_module::gem5_getPort(if_name, idx);
498 }
499 
500 template <unsigned int BITWIDTH>
502  const Params &params, const sc_core::sc_module_name &mn) :
503  TlmToGem5BridgeBase(mn), peq(this, &TlmToGem5Bridge<BITWIDTH>::peq_cb),
504  waitForRetry(false), pendingRequest(nullptr), pendingPacket(nullptr),
505  needToSendRetry(false), responseInProgress(false),
506  bmp(std::string(name()) + "master", *this), socket("tlm_socket"),
507  wrapper(socket, std::string(name()) + ".tlm", InvalidPortID),
508  system(params.system),
509  _id(params.system->getGlobalRequestorId(
510  std::string("[systemc].") + name()))
511 {
512 }
513 
514 template <unsigned int BITWIDTH>
515 void
517 {
518  /*
519  * Register the TLM non-blocking interface when using gem5 Timing mode and
520  * the TLM blocking interface when using the gem5 Atomic mode.
521  * Then the magic (TM) in simple_target_socket automatically transforms
522  * non-blocking in blocking transactions and vice versa.
523  *
524  * NOTE: The mode may change during execution.
525  */
526  if (system->isTimingMode()) {
527  SC_REPORT_INFO("TlmToGem5Bridge", "register non-blocking interface");
528  socket.register_nb_transport_fw(
530  } else if (system->isAtomicMode()) {
531  SC_REPORT_INFO("TlmToGem5Bridge", "register blocking interface");
532  socket.register_b_transport(
534  socket.register_get_direct_mem_ptr(
536  } else {
537  panic("gem5 operates neither in Timing nor in Atomic mode");
538  }
539 
540  socket.register_transport_dbg(
542 
544 }
545 
546 } // namespace sc_gem5
547 
549 TlmToGem5Bridge32Params::create() const
550 {
551  return new sc_gem5::TlmToGem5Bridge<32>(
552  *this, sc_core::sc_module_name(name.c_str()));
553 }
554 
556 TlmToGem5Bridge64Params::create() const
557 {
558  return new sc_gem5::TlmToGem5Bridge<64>(
559  *this, sc_core::sc_module_name(name.c_str()));
560 }
sc_gem5::payload2packet
PacketPtr payload2packet(RequestorID _id, tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:93
ArmISA::status
Bitfield< 5, 0 > status
Definition: miscregs_types.hh:417
sc_core::sc_time::from_value
static sc_time from_value(sc_dt::uint64)
Definition: sc_time.cc:210
Packet::isResponse
bool isResponse() const
Definition: packet.hh:561
MemBackdoor
Definition: backdoor.hh:38
system.hh
sc_gem5::TlmToGem5Bridge::recvRangeChange
void recvRangeChange()
Definition: tlm_to_gem5.cc:482
tlm_to_gem5.hh
tlm::tlm_phase
Definition: phase.hh:47
Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:413
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:244
tlm::TLM_COMPLETED
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:65
Flags< FlagsType >
tlm::tlm_generic_payload::get_streaming_width
unsigned int get_streaming_width() const
Definition: gp.hh:228
ArmISA::width
Bitfield< 4 > width
Definition: miscregs_types.hh:68
sc_module_name.hh
sc_gem5::TlmToGem5Bridge::invalidateDmi
void invalidateDmi(const ::MemBackdoor &backdoor)
Definition: tlm_to_gem5.cc:246
tlm::tlm_dmi
Definition: dmi.hh:46
tlm::TLM_WRITE_COMMAND
@ TLM_WRITE_COMMAND
Definition: gp.hh:102
tlm::TLM_UPDATED
@ TLM_UPDATED
Definition: fw_bw_ifs.hh:65
tlm::TLM_OK_RESPONSE
@ TLM_OK_RESPONSE
Definition: gp.hh:108
MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:83
tlm::END_REQ
@ END_REQ
Definition: phase.hh:42
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:59
tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE
@ TLM_BYTE_ENABLE_ERROR_RESPONSE
Definition: gp.hh:114
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
SC_REPORT_FATAL
#define SC_REPORT_FATAL(msg_type, msg)
Definition: sc_report_handler.hh:131
tlm::tlm_dmi::DMI_ACCESS_READ
@ DMI_ACCESS_READ
Definition: dmi.hh:90
AddrRange::end
Addr end() const
Get the end address of the range.
Definition: addr_range.hh:321
Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:341
std::vector
STL vector class.
Definition: stl.hh:37
Gem5SystemC::Gem5Extension::getPacket
PacketPtr getPacket()
Definition: sc_ext.cc:62
tlm::tlm_generic_payload::release
void release()
Definition: gp.hh:147
sc_gem5::TlmToGem5Bridge::TlmToGem5Bridge
TlmToGem5Bridge(const Params &p, const sc_core::sc_module_name &mn)
Definition: tlm_to_gem5.cc:501
sc_assert
#define sc_assert(expr)
Definition: sc_report_handler.hh:135
sc_gem5::TlmToGem5Bridge::Params
TlmToGem5BridgeBaseParams Params
Definition: tlm_to_gem5.hh:170
Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:395
sc_gem5::TlmToGem5Bridge::recvReqRetry
void recvReqRetry()
Definition: tlm_to_gem5.cc:455
tlm::tlm_generic_payload::set_dmi_allowed
void set_dmi_allowed(bool dmi_allowed)
Definition: gp.hh:256
tlm::tlm_generic_payload::get_response_string
std::string get_response_string() const
Definition: gp.cc:292
sc_gem5::TlmToGem5Bridge::nb_transport_fw
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &t)
Definition: tlm_to_gem5.cc:271
MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:86
X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
RequestorID
uint16_t RequestorID
Definition: request.hh:89
sc_gem5::TlmToGem5Bridge::destroyPacket
void destroyPacket(PacketPtr pkt)
Definition: tlm_to_gem5.cc:227
tlm::TLM_BURST_ERROR_RESPONSE
@ TLM_BURST_ERROR_RESPONSE
Definition: gp.hh:113
tlm::tlm_dmi::set_end_address
void set_end_address(sc_dt::uint64 addr)
Definition: dmi.hh:117
tlm::tlm_generic_payload::get_command
tlm_command get_command() const
Definition: gp.hh:197
tlm::tlm_generic_payload::get_byte_enable_ptr
unsigned char * get_byte_enable_ptr() const
Definition: gp.hh:236
sc_core::sc_module::gem5_getPort
virtual ::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
SC_REPORT_ERROR
#define SC_REPORT_ERROR(msg_type, msg)
Definition: sc_report_handler.hh:127
tlm::tlm_generic_payload::get_data_length
unsigned int get_data_length() const
Definition: gp.hh:209
sc_gem5::TlmToGem5BridgeBase
Definition: tlm_to_gem5.hh:83
sc_gem5::TlmToGem5Bridge::before_end_of_elaboration
void before_end_of_elaboration() override
Definition: tlm_to_gem5.cc:516
MemCmd
Definition: packet.hh:72
sc_gem5::PayloadToPacketConversionStep
std::function< void(PacketPtr pkt, tlm::tlm_generic_payload &trans)> PayloadToPacketConversionStep
Definition: tlm_to_gem5.hh:77
MemBackdoor::ptr
uint8_t * ptr() const
Definition: backdoor.hh:58
Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:571
sc_core::sc_time
Definition: sc_time.hh:49
sc_gem5::TlmToGem5Bridge::sendEndReq
void sendEndReq(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:132
sc_gem5::TlmToGem5Bridge::TlmSenderState
Definition: tlm_to_gem5.hh:93
tlm::TLM_READ_COMMAND
@ TLM_READ_COMMAND
Definition: gp.hh:101
MemBackdoor::range
const AddrRange & range() const
Definition: backdoor.hh:54
SimClock::Int::ps
Tick ps
picosecond
Definition: core.cc:63
sc_core::sc_module_name
Definition: sc_module_name.hh:41
tlm::tlm_generic_payload::acquire
void acquire()
Definition: gp.hh:140
sc_gem5::TlmToGem5Bridge::sendBeginResp
void sendBeginResp(tlm::tlm_generic_payload &trans, sc_core::sc_time &delay)
Definition: tlm_to_gem5.cc:144
tlm::tlm_generic_payload::get_extension
void get_extension(T *&ext) const
Definition: gp.hh:381
tlm::END_RESP
@ END_RESP
Definition: phase.hh:44
sc_gem5::TlmToGem5Bridge::checkTransaction
void checkTransaction(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:234
ProbePoints::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:103
tlm::TLM_IGNORE_COMMAND
@ TLM_IGNORE_COMMAND
Definition: gp.hh:103
sc_gem5::TlmToGem5Bridge::gem5_getPort
::Port & gem5_getPort(const std::string &if_name, int idx=-1) override
Definition: tlm_to_gem5.cc:490
sc_gem5::TlmToGem5Bridge::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Definition: tlm_to_gem5.cc:409
name
const std::string & name()
Definition: trace.cc:48
SC_REPORT_INFO
#define SC_REPORT_INFO(msg_type, msg)
Definition: sc_report_handler.hh:119
sc_gem5::addPayloadToPacketConversionStep
void addPayloadToPacketConversionStep(PayloadToPacketConversionStep step)
Notify the Tlm2Gem5 bridge that we need an extra step to properly convert a tlm payload to gem5 packe...
Definition: tlm_to_gem5.cc:87
sc_gem5::TlmToGem5Bridge::handleBeginReq
void handleBeginReq(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:167
SC_REPORT_WARNING
#define SC_REPORT_WARNING(msg_type, msg)
Definition: sc_report_handler.hh:123
tlm::BEGIN_REQ
@ BEGIN_REQ
Definition: phase.hh:41
sc_gem5::TlmToGem5Bridge::b_transport
void b_transport(tlm::tlm_generic_payload &trans, sc_core::sc_time &t)
Definition: tlm_to_gem5.cc:297
MemBackdoor::addInvalidationCallback
void addInvalidationCallback(CbFunction func)
Definition: backdoor.hh:99
MemBackdoor::readable
bool readable() const
Definition: backdoor.hh:65
Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:139
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
sc_core::SC_PS
@ SC_PS
Definition: sc_time.hh:42
Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:332
tlm::tlm_generic_payload
Definition: gp.hh:133
AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:314
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
sc_gem5::TlmToGem5Bridge
Definition: tlm_to_gem5.hh:90
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:258
Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:340
sc_core::sc_module::before_end_of_elaboration
virtual void before_end_of_elaboration()
Definition: sc_module.hh:248
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
sc_gem5::Port
Definition: port.hh:50
tlm::tlm_generic_payload::is_response_error
bool is_response_error() const
Definition: gp.hh:214
tlm::tlm_dmi::set_dmi_ptr
void set_dmi_ptr(unsigned char *p)
Definition: dmi.hh:115
tlm::tlm_dmi::DMI_ACCESS_NONE
@ DMI_ACCESS_NONE
Definition: dmi.hh:89
sc_gem5::TlmToGem5Bridge::handleEndResp
void handleEndResp(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:211
sc_gem5
Definition: sc_clock.cc:42
sc_gem5::TlmToGem5Bridge::transport_dbg
unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
Definition: tlm_to_gem5.cc:336
Gem5SystemC::Gem5Extension
Definition: sc_ext.hh:43
tlm::tlm_dmi::set_start_address
void set_start_address(sc_dt::uint64 addr)
Definition: dmi.hh:116
tlm::tlm_dmi::dmi_access_e
dmi_access_e
Definition: dmi.hh:71
sc_gem5::TlmToGem5Bridge::get_direct_mem_ptr
bool get_direct_mem_ptr(tlm::tlm_generic_payload &trans, tlm::tlm_dmi &dmi_data)
Definition: tlm_to_gem5.cc:358
sc_gem5::TlmToGem5Bridge::peq_cb
void peq_cb(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase)
Definition: tlm_to_gem5.cc:254
sc_time.hh
tlm::tlm_dmi::DMI_ACCESS_WRITE
@ DMI_ACCESS_WRITE
Definition: dmi.hh:91
tlm::tlm_generic_payload::get_address
sc_dt::uint64 get_address() const
Definition: gp.hh:201
tlm::tlm_generic_payload::get_data_ptr
unsigned char * get_data_ptr() const
Definition: gp.hh:205
MemBackdoor::writeable
bool writeable() const
Definition: backdoor.hh:75
tlm::BEGIN_RESP
@ BEGIN_RESP
Definition: phase.hh:43
tlm::tlm_dmi::set_granted_access
void set_granted_access(dmi_access_e a)
Definition: dmi.hh:120
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
tlm::tlm_generic_payload::set_response_status
void set_response_status(const tlm_response_status response_status)
Definition: gp.hh:221
tlm::TLM_ACCEPTED
@ TLM_ACCEPTED
Definition: fw_bw_ifs.hh:65

Generated on Tue Mar 23 2021 19:41:31 for gem5 by doxygen 1.8.17