#include <bac.hh>

Classes
struct	BACStats
struct	Stalls
	Source of possible stalls. More...

Public Types
enum	BACStatus { Active , Inactive }
	Overall decoupled BPU stage status. More...
enum	ThreadStatus { Idle , Running , Squashing , Blocked , FTQFull , FTQLocked , ThreadStatusMax }
	Individual thread status. More...

Public Member Functions
	BAC (CPU *_cpu, const BaseO3CPUParams &params)
	BAC constructor.
std::string	name () const
	Returns the name of the stage.
void	regProbePoints ()
	Registers probes and listeners.
void	setTimeBuffer (TimeBuffer< TimeStruct > *tb_ptr)
	Sets the main backwards communication time buffer pointer.
void	setActiveThreads (std::list< ThreadID > *at_ptr)
	Sets pointer to list of active threads.
void	setFetchTargetQueue (FTQ *_ptr)
	Connect the FTQ.
void	startupStage ()
	Initialize stage.
void	clearStates (ThreadID tid)
	Clear all thread-specific states.
void	drainResume ()
	Resume after a drain.
void	drainSanityCheck () const
	Perform sanity checks after a drain.
bool	isDrained () const
	Has the stage drained?
void	drainStall (ThreadID tid)
	Stall the fetch stage after reaching a safe drain point.
void	takeOverFrom ()
	Takes over from another CPU's thread.
void	deactivateThread (ThreadID tid)
void	tick ()
	Process all input signals and create the next fetch target.
bool	updatePC (const DynInstPtr &inst, PCStateBase &fetch_pc, FetchTargetPtr &ft)
	Calculate the next PC address depending on the instruction type and the branch prediction.

Protected Attributes
gem5::o3::BAC::BACStats	stats

Private Types
typedef branch_prediction::BranchType	BranchType

Private Member Functions
void	resetStage ()
	Reset this pipeline stage.
void	switchToActive ()
	Changes the status of this stage to active, and indicates this to the CPU.
void	switchToInactive ()
	Changes the status of this stage to inactive, and indicates this to the CPU.
bool	checkStall (ThreadID tid) const
	Checks if a thread is stalled.
void	updateBACStatus ()
	Updates overall BAC stage status; to be called at the end of each cycle.
bool	checkSignalsAndUpdate (ThreadID tid)
	Checks all input signals and updates the status as necessary.
bool	checkAndUpdateBPUSignals (ThreadID tid)
	Check the backward signals that update the BPU.
FetchTargetPtr	newFetchTarget (ThreadID tid, const PCStateBase &start_pc)
	Create a new fetch target.
bool	predict (ThreadID tid, const StaticInstPtr &inst, const FetchTargetPtr &ft, PCStateBase &pc)
	The prediction function for the BAC stage.
void	generateFetchTargets (ThreadID tid, bool &status_change)
	Main function that feeds the FTQ with new fetch targets.
bool	updatePreDecode (ThreadID tid, const InstSeqNum seqNum, const StaticInstPtr &inst, PCStateBase &pc, const FetchTargetPtr &ft)
	Pre-decode update --------------------------------------— After predecoding instruction in the fetch stage all instructions are known together and a sequence number is assigned to them.
void	squash (const PCStateBase &new_pc, ThreadID tid)
	Squashes BAC for a specific thread and resets the PC.
void	squashBpuHistories (ThreadID tid)
	Squashes the BPU histories in the FTQ.
Addr	alignToCacheBlock (Addr addr)
	Align a address to the start of a cache block.

Private Attributes
BACStatus	_status
	Decode status.
ThreadStatus	bacStatus [MaxThreads]
	Per-thread status.
CPU *	cpu
	Pointer to the main CPU.
branch_prediction::BPredUnit *	bpu
	BPredUnit.
FTQ *	ftq
	Fetch target Queue.
TimeBuffer< TimeStruct > *	timeBuffer
	Time buffer interface.
TimeBuffer< TimeStruct >::wire	fromFetch
	Wire to get fetches's information from backwards time buffer.
TimeBuffer< TimeStruct >::wire	fromDecode
	Wire to get decode's information from backwards time buffer.
TimeBuffer< TimeStruct >::wire	fromCommit
	Wire to get commit's information from backwards time buffer.
TimeBuffer< FetchStruct >::wire	toFetch
	Wire used to write any information heading to fetch.
std::unique_ptr< PCStateBase >	bacPC [MaxThreads]
	The decoupled PC which runs ahead of fetch.
bool	wroteToTimeBuffer
	Variable that tracks if BAC has written to the time buffer this cycle.
Stalls	stalls [MaxThreads]
	Tracks which stages are telling the ftq to stall.
const bool	decoupledFrontEnd
	Enables the decoupled front-end.
const Cycles	fetchToBacDelay
	Fetch to BAC delay.
const Cycles	decodeToFetchDelay
	Decode to fetch delay.
const Cycles	commitToFetchDelay
	Commit to fetch delay.
const Cycles	bacToFetchDelay
	BAC to fetch delay.
const unsigned int	cacheBlkSize
	Cache block size.
const unsigned	fetchTargetWidth
	The maximum width of a fetch target.
const unsigned	minInstSize
	The minimum size an instruction can have in the current architecture.
std::list< ThreadID > *	activeThreads
	List of Active FTQ Threads.
const ThreadID	numThreads
	Number of threads.
const unsigned	maxFTPerCycle
const unsigned	maxTakenPredPerCycle

Detailed Description

Definition at line 91 of file bac.hh.

Member Typedef Documentation

◆ BranchType

typedef branch_prediction::BranchType gem5::o3::BAC::BranchType

private

Definition at line 93 of file bac.hh.

Member Enumeration Documentation

◆ BACStatus

enum gem5::o3::BAC::BACStatus

Overall decoupled BPU stage status.

Used to determine if the CPU can deschedule itself due to a lack of activity.

Enumerator
Active
Inactive

Definition at line 99 of file bac.hh.

◆ ThreadStatus

enum gem5::o3::BAC::ThreadStatus

Individual thread status.

Enumerator
Idle
Running
Squashing
Blocked
FTQFull
FTQLocked
ThreadStatusMax

Definition at line 106 of file bac.hh.

Constructor & Destructor Documentation

◆ BAC()

gem5::o3::BAC::BAC	(	CPU *	_cpu,
		const BaseO3CPUParams &	params )

BAC constructor.

Definition at line 77 of file bac.cc.

References bacPC, bacToFetchDelay, bpu, cacheBlkSize, commitToFetchDelay, cpu, decodeToFetchDelay, decoupledFrontEnd, fatal_if, fetchTargetWidth, fetchToBacDelay, ftq, gem5::ArmISA::i, maxFTPerCycle, maxTakenPredPerCycle, gem5::o3::MaxThreads, minInstSize, numThreads, stalls, stats, and wroteToTimeBuffer.

Referenced by gem5::o3::BAC::BACStats::BACStats(), checkAndUpdateBPUSignals(), checkSignalsAndUpdate(), checkStall(), generateFetchTargets(), newFetchTarget(), squash(), squashBpuHistories(), updatePC(), and updatePreDecode().

Member Function Documentation

◆ alignToCacheBlock()

Addr gem5::o3::BAC::alignToCacheBlock ( Addr addr )

inlineprivate

Align a address to the start of a cache block.

Definition at line 421 of file bac.hh.

References gem5::X86ISA::addr, and cacheBlkSize.

◆ checkAndUpdateBPUSignals()

bool gem5::o3::BAC::checkAndUpdateBPUSignals ( ThreadID tid )

private

Check the backward signals that update the BPU.

Definition at line 290 of file bac.cc.

References BAC(), bacStatus, bpu, DPRINTF, fromCommit, fromDecode, fromFetch, squash(), squashBpuHistories(), Squashing, and stats.

Referenced by checkSignalsAndUpdate(), and tick().

◆ checkSignalsAndUpdate()

bool gem5::o3::BAC::checkSignalsAndUpdate ( ThreadID tid )

private

Checks all input signals and updates the status as necessary.

Returns: : Returns true if the status changed due to input signals.

Definition at line 375 of file bac.cc.

References BAC(), bacStatus, Blocked, checkAndUpdateBPUSignals(), checkStall(), cpu, DPRINTF, ftq, FTQFull, FTQLocked, Idle, Running, squashBpuHistories(), Squashing, and stalls.

Referenced by tick().

◆ checkStall()

bool gem5::o3::BAC::checkStall ( ThreadID tid ) const

private

Checks if a thread is stalled.

Definition at line 243 of file bac.cc.

References BAC(), bpu, DPRINTF, and stalls.

Referenced by checkSignalsAndUpdate().

◆ clearStates()

void gem5::o3::BAC::clearStates ( ThreadID tid )

Clear all thread-specific states.

Definition at line 148 of file bac.cc.

References bacPC, bacStatus, cpu, ftq, Running, gem5::ArmISA::set, and stalls.

Referenced by resetStage().

◆ deactivateThread()

void gem5::o3::BAC::deactivateThread ( ThreadID tid )

inline

Definition at line 182 of file bac.hh.

◆ drainResume()

void gem5::o3::BAC::drainResume ( )

Resume after a drain.

Definition at line 174 of file bac.cc.

References DPRINTF, gem5::ArmISA::i, numThreads, and stalls.

◆ drainSanityCheck()

void gem5::o3::BAC::drainSanityCheck ( ) const

Perform sanity checks after a drain.

Definition at line 183 of file bac.cc.

References bacStatus, bpu, ftq, gem5::ArmISA::i, Idle, isDrained(), numThreads, and stalls.

◆ drainStall()

void gem5::o3::BAC::drainStall ( ThreadID tid )

Stall the fetch stage after reaching a safe drain point.

The CPU uses this method to stop fetching instructions from a thread that has been drained. The drain stall is different from all other stalls in that it is signaled instantly from the commit stage (without the normal communication delay) when it has reached a safe point to drain from.

Definition at line 214 of file bac.cc.

References cpu, DPRINTF, and stalls.

◆ generateFetchTargets()

void gem5::o3::BAC::generateFetchTargets	(	ThreadID	tid,
		bool &	status_change )

private

Main function that feeds the FTQ with new fetch targets.

By leveraging the BTB up to N consecutive addresses are searched to detect a branch instruction. For every BTB hit the direction predictor is asked to make a prediction. In every cycle one fetch target is created. A fetch target ends once the first branch instruction is detected or the maximum search bandwidth for a cycle is reached.

This function implements the head of the decoupled frontend. Instead of waiting for the pre-decoding the current instruction, as done in the standared front-end, the BTB is leveraged for finding branches in the instruction stream.

Starting from the current address we search all consecutive addresses if a entry exits in the BTB. As soon as the BTB hits, we know we have reached a branch instruction and make a prediction for the branch. The start and end address of this so called fetch target is stored together with the prediction in the FTQ.

Depending on the prediction of the BPU the branch target or the fallthrough address determine the start address for the next fetch target and search cycle.

For simplicity each fetch target contains at max one branch. However, as a not-taken branch does not require redirecting the fetch unit CPU's may continue fetching past a not taken branch. Therefore, this implementationt may create multiple fetach targets per cycle. A cycle ends when (1) the fetch target size is reached, (2) an upper bound of fetch targets per cycle is reached, or (3) a branch is predicted as taken.

The same mechanism enables us to simulate making multiple taken predictions per cycles as it is the case in very recent commercial CPU's.

Definition at line 585 of file bac.cc.

References BAC(), bacPC, bacStatus, bpu, gem5::PCStateBase::clone(), DPRINTF, fetchTargetWidth, ftq, FTQFull, gem5::PCStateBase::instAddr(), gem5::StaticInst::isLastMicroop(), gem5::StaticInst::isMicroop(), maxFTPerCycle, maxTakenPredPerCycle, minInstSize, newFetchTarget(), predict(), gem5::ArmISA::set, gem5::PCStateBase::set(), gem5::StaticInst::size(), stats, and wroteToTimeBuffer.

Referenced by tick().

◆ isDrained()

bool gem5::o3::BAC::isDrained ( ) const

Has the stage drained?

Definition at line 196 of file bac.cc.

References bacStatus, ftq, gem5::ArmISA::i, Idle, and numThreads.

Referenced by drainSanityCheck().

◆ name()

std::string gem5::o3::BAC::name ( ) const

Returns the name of the stage.

Definition at line 109 of file bac.cc.

References cpu.

◆ newFetchTarget()

FetchTargetPtr gem5::o3::BAC::newFetchTarget	(	ThreadID	tid,
		const PCStateBase &	start_pc )

private

Create a new fetch target.

Parameters

start_pc The current PC. Will be the start address of the fetch target.

Definition at line 554 of file bac.cc.

References BAC(), cpu, DPRINTF, and stats.

Referenced by generateFetchTargets().

◆ predict()

bool gem5::o3::BAC::predict	(	ThreadID	tid,
		const StaticInstPtr &	inst,
		const FetchTargetPtr &	ft,
		PCStateBase &	pc )

private

The prediction function for the BAC stage.

In the decoupled scenario the branch history is not added to the BPUs very own predictor history because at the moment a prediction is made the sequence number in not known.

Parameters

inst	The branch instruction.
ft	The fetch target that is currently processed.
PC	The predicted PC is passed back through this parameter.

Returns: Returns if the branch is taken or not.

Perform the prediction. The prediction history object is pushed onto the fetch target. This allows tracking which object belongs to which branch. It also allows inserting dummy objects for branches that where not detected by the BAC state due to BTB misses. The postFetch() function will move the history from the FT to the main history of the BPU and insert these missing histories.

Definition at line 565 of file bac.cc.

References bpu, DPRINTF, and gem5::MipsISA::pc.

Referenced by generateFetchTargets().

◆ regProbePoints()

void gem5::o3::BAC::regProbePoints ( )

inline

Registers probes and listeners.

Definition at line 137 of file bac.hh.

◆ resetStage()

void gem5::o3::BAC::resetStage ( )

private

Reset this pipeline stage.

Definition at line 162 of file bac.cc.

References _status, clearStates(), Inactive, numThreads, and wroteToTimeBuffer.

Referenced by startupStage(), and takeOverFrom().

◆ setActiveThreads()

void gem5::o3::BAC::setActiveThreads ( std::list< ThreadID > * at_ptr )

Sets pointer to list of active threads.

Definition at line 126 of file bac.cc.

References activeThreads.

◆ setFetchTargetQueue()

void gem5::o3::BAC::setFetchTargetQueue ( FTQ * _ptr )

Connect the FTQ.

Definition at line 132 of file bac.cc.

References ftq.

◆ setTimeBuffer()

void gem5::o3::BAC::setTimeBuffer ( TimeBuffer< TimeStruct > * tb_ptr )

Sets the main backwards communication time buffer pointer.

Definition at line 115 of file bac.cc.

References commitToFetchDelay, decodeToFetchDelay, fetchToBacDelay, fromCommit, fromDecode, fromFetch, and timeBuffer.

◆ squash()

void gem5::o3::BAC::squash	(	const PCStateBase &	new_pc,
		ThreadID	tid )

private

Squashes BAC for a specific thread and resets the PC.

Definition at line 484 of file bac.cc.

References BAC(), bacPC, bacStatus, decoupledFrontEnd, DPRINTF, ftq, gem5::ArmISA::set, and Squashing.

Referenced by checkAndUpdateBPUSignals().

◆ squashBpuHistories()

void gem5::o3::BAC::squashBpuHistories ( ThreadID tid )

private

Squashes the BPU histories in the FTQ.

by iterating from tail to head and reverts the predictions made.

Definition at line 464 of file bac.cc.

References BAC(), bpu, decoupledFrontEnd, DPRINTF, and ftq.

Referenced by checkAndUpdateBPUSignals(), checkSignalsAndUpdate(), and updatePreDecode().

◆ startupStage()

void gem5::o3::BAC::startupStage ( )

Initialize stage.

Definition at line 139 of file bac.cc.

References resetStage(), and switchToActive().

◆ switchToActive()

void gem5::o3::BAC::switchToActive ( )

private

Changes the status of this stage to active, and indicates this to the CPU.

Definition at line 223 of file bac.cc.

References _status, Active, gem5::o3::CPU::BACIdx, cpu, DPRINTF, and Inactive.

Referenced by startupStage().

◆ switchToInactive()

void gem5::o3::BAC::switchToInactive ( )

private

Changes the status of this stage to inactive, and indicates this to the CPU.

Definition at line 233 of file bac.cc.

References _status, Active, gem5::o3::CPU::BACIdx, cpu, DPRINTF, and Inactive.

◆ takeOverFrom()

void gem5::o3::BAC::takeOverFrom ( )

inline

Takes over from another CPU's thread.

Definition at line 177 of file bac.hh.

References resetStage().

◆ tick()

void gem5::o3::BAC::tick ( )

Process all input signals and create the next fetch target.

Definition at line 503 of file bac.cc.

References activeThreads, bacStatus, checkAndUpdateBPUSignals(), checkSignalsAndUpdate(), cpu, decoupledFrontEnd, DPRINTF, generateFetchTargets(), Idle, Running, stats, and updateBACStatus().

◆ updateBACStatus()

void gem5::o3::BAC::updateBACStatus ( )

private

Updates overall BAC stage status; to be called at the end of each cycle.

Definition at line 261 of file bac.cc.

References _status, Active, activeThreads, gem5::o3::CPU::BACIdx, bacStatus, cpu, DPRINTF, Inactive, Running, and Squashing.

Referenced by tick().

◆ updatePC()

bool gem5::o3::BAC::updatePC	(	const DynInstPtr &	inst,
		PCStateBase &	fetch_pc,
		FetchTargetPtr &	ft )

Calculate the next PC address depending on the instruction type and the branch prediction.

Parameters

inst	The currently processed dynamic instruction.
fetch_pc	The current fetch PC passed in by reference. It will be updated with what the next PC will be.
ft	The currently processed fetch target. Can be nullptr for the non-decoupled scenario.

Returns: Whether or not a branch was predicted as taken.

Definition at line 904 of file bac.cc.

References BAC(), bpu, decoupledFrontEnd, DPRINTF, ftq, stats, and updatePreDecode().

◆ updatePreDecode()

bool gem5::o3::BAC::updatePreDecode	(	ThreadID	tid,
		const InstSeqNum	seqNum,
		const StaticInstPtr &	inst,
		PCStateBase &	pc,
		const FetchTargetPtr &	ft )

private

Pre-decode update --------------------------------------— After predecoding instruction in the fetch stage all instructions are known together and a sequence number is assigned to them.

Post fetch part ---------------------------------------—.

The fetch stage will call this function for every branch instruction to allow the BAC stage to update the branch predictor history.

There can be the following two cases:

The branch was detected by the BAC stage and a prediction was made. In that case the branch history is moved from the FTQ to the BPU.
The branch was not detected by the BAC stage. In that case a "dummy" branch history is created and inserted into the BPU. For this dummy prediction it is assumed that the branch is not taken. If it turns unconditional or is taken decode or commit will squash the branch.

This function performs the following steps:

For every branch where a prediction was made in the first place It moves the branch history from the FTQ to the BPU.

Together with inserting an instruction into the instruction queue instruction matches the predicted instruction type. If so update the information with the new. In case the types dont match something is wrong and we need to squash. (should not be the case.)

Parameters

seq_num	The branches sequence that we want to update.
inst	The new pre-decoded branch instruction.
tid	The thread id.

Returns: Returns if the update was successful.

Definition at line 764 of file bac.cc.

References gem5::StaticInst::advancePC(), BAC(), gem5::branch_prediction::BPredUnit::PredictorHistory::bpHistory, bpu, DPRINTF, ftq, gem5::branch_prediction::getBranchType(), gem5::StaticInst::isLastMicroop(), gem5::StaticInst::isMicroop(), gem5::StaticInst::isUncondCtrl(), gem5::branch_prediction::BPredUnit::PredictorHistory::pc, gem5::MipsISA::pc, gem5::branch_prediction::BPredUnit::PredictorHistory::predTaken, gem5::branch_prediction::BPredUnit::PredictorHistory::seqNum, gem5::ArmISA::set, squashBpuHistories(), stats, gem5::branch_prediction::BPredUnit::PredictorHistory::target, gem5::branch_prediction::toString(), and gem5::branch_prediction::BPredUnit::PredictorHistory::type.

Referenced by updatePC().

Member Data Documentation

◆ _status

BACStatus gem5::o3::BAC::_status

private

Decode status.

Definition at line 119 of file bac.hh.

Referenced by resetStage(), switchToActive(), switchToInactive(), and updateBACStatus().

◆ activeThreads

std::list<ThreadID>* gem5::o3::BAC::activeThreads

private

List of Active FTQ Threads.

Definition at line 408 of file bac.hh.

Referenced by setActiveThreads(), tick(), and updateBACStatus().

◆ bacPC

std::unique_ptr<PCStateBase> gem5::o3::BAC::bacPC[MaxThreads]

private

The decoupled PC which runs ahead of fetch.

Definition at line 361 of file bac.hh.

Referenced by BAC(), clearStates(), generateFetchTargets(), and squash().

◆ bacStatus

ThreadStatus gem5::o3::BAC::bacStatus[MaxThreads]

private

Per-thread status.

Definition at line 122 of file bac.hh.

Referenced by checkAndUpdateBPUSignals(), checkSignalsAndUpdate(), clearStates(), drainSanityCheck(), generateFetchTargets(), isDrained(), squash(), tick(), and updateBACStatus().

◆ bacToFetchDelay

const Cycles gem5::o3::BAC::bacToFetchDelay

private

BAC to fetch delay.

Definition at line 392 of file bac.hh.

Referenced by BAC().

◆ bpu

branch_prediction::BPredUnit* gem5::o3::BAC::bpu

private

BPredUnit.

Definition at line 340 of file bac.hh.

Referenced by BAC(), checkAndUpdateBPUSignals(), checkStall(), drainSanityCheck(), generateFetchTargets(), predict(), squashBpuHistories(), updatePC(), and updatePreDecode().

◆ cacheBlkSize

const unsigned int gem5::o3::BAC::cacheBlkSize

private

Cache block size.

Definition at line 395 of file bac.hh.

Referenced by alignToCacheBlock(), and BAC().

◆ commitToFetchDelay

const Cycles gem5::o3::BAC::commitToFetchDelay

private

Commit to fetch delay.

(Same delay for BAC as for fetch)

Definition at line 389 of file bac.hh.

Referenced by BAC(), and setTimeBuffer().

◆ cpu

CPU* gem5::o3::BAC::cpu

private

Pointer to the main CPU.

Definition at line 337 of file bac.hh.

Referenced by BAC(), gem5::o3::BAC::BACStats::BACStats(), checkSignalsAndUpdate(), clearStates(), drainStall(), name(), newFetchTarget(), switchToActive(), switchToInactive(), tick(), and updateBACStatus().

◆ decodeToFetchDelay

const Cycles gem5::o3::BAC::decodeToFetchDelay

private

Decode to fetch delay.

(Same delay for BAC as for fetch)

Definition at line 386 of file bac.hh.

Referenced by BAC(), and setTimeBuffer().

◆ decoupledFrontEnd

const bool gem5::o3::BAC::decoupledFrontEnd

private

Enables the decoupled front-end.

Definition at line 380 of file bac.hh.

Referenced by BAC(), squash(), squashBpuHistories(), tick(), and updatePC().

◆ fetchTargetWidth

const unsigned gem5::o3::BAC::fetchTargetWidth

private

The maximum width of a fetch target.

This also determines the maximum addresses searched in one cycle. (FT width / minInstSize)

Definition at line 399 of file bac.hh.

Referenced by BAC(), gem5::o3::BAC::BACStats::BACStats(), and generateFetchTargets().

◆ fetchToBacDelay

const Cycles gem5::o3::BAC::fetchToBacDelay

private

Fetch to BAC delay.

Definition at line 383 of file bac.hh.

Referenced by BAC(), and setTimeBuffer().

◆ fromCommit

TimeBuffer<TimeStruct>::wire gem5::o3::BAC::fromCommit

private

Wire to get commit's information from backwards time buffer.

Definition at line 355 of file bac.hh.

Referenced by checkAndUpdateBPUSignals(), and setTimeBuffer().

◆ fromDecode

TimeBuffer<TimeStruct>::wire gem5::o3::BAC::fromDecode

private

Wire to get decode's information from backwards time buffer.

Definition at line 352 of file bac.hh.

Referenced by checkAndUpdateBPUSignals(), and setTimeBuffer().

◆ fromFetch

TimeBuffer<TimeStruct>::wire gem5::o3::BAC::fromFetch

private

Wire to get fetches's information from backwards time buffer.

Definition at line 349 of file bac.hh.

Referenced by checkAndUpdateBPUSignals(), and setTimeBuffer().

◆ ftq

FTQ* gem5::o3::BAC::ftq

private

Fetch target Queue.

Definition at line 343 of file bac.hh.

Referenced by BAC(), checkSignalsAndUpdate(), clearStates(), drainSanityCheck(), generateFetchTargets(), isDrained(), setFetchTargetQueue(), squash(), squashBpuHistories(), updatePC(), and updatePreDecode().

◆ maxFTPerCycle

const unsigned gem5::o3::BAC::maxFTPerCycle

private

Definition at line 414 of file bac.hh.

Referenced by BAC(), gem5::o3::BAC::BACStats::BACStats(), and generateFetchTargets().

◆ maxTakenPredPerCycle

const unsigned gem5::o3::BAC::maxTakenPredPerCycle

private

Definition at line 417 of file bac.hh.

Referenced by BAC(), and generateFetchTargets().

◆ minInstSize

const unsigned gem5::o3::BAC::minInstSize

private

The minimum size an instruction can have in the current architecture.

It determines the search granularity of the decoupled front-end. I.e. for x86 this must be 1. For fixed size ISA's it should be equal to the instruction size to speedup simulation time.

Definition at line 405 of file bac.hh.

Referenced by BAC(), and generateFetchTargets().

◆ numThreads

const ThreadID gem5::o3::BAC::numThreads

private

Number of threads.

Definition at line 411 of file bac.hh.

Referenced by BAC(), drainResume(), drainSanityCheck(), isDrained(), and resetStage().

◆ stalls

Stalls gem5::o3::BAC::stalls[MaxThreads]

private

Tracks which stages are telling the ftq to stall.

Definition at line 377 of file bac.hh.

Referenced by BAC(), checkSignalsAndUpdate(), checkStall(), clearStates(), drainResume(), drainSanityCheck(), and drainStall().

◆ stats

gem5::o3::BAC::BACStats gem5::o3::BAC::stats

protected

Referenced by BAC(), checkAndUpdateBPUSignals(), generateFetchTargets(), newFetchTarget(), tick(), updatePC(), and updatePreDecode().

◆ timeBuffer

TimeBuffer<TimeStruct>* gem5::o3::BAC::timeBuffer

private

Time buffer interface.

Definition at line 346 of file bac.hh.

Referenced by setTimeBuffer().

◆ toFetch

TimeBuffer<FetchStruct>::wire gem5::o3::BAC::toFetch

private

Wire used to write any information heading to fetch.

Definition at line 358 of file bac.hh.

◆ wroteToTimeBuffer

bool gem5::o3::BAC::wroteToTimeBuffer

private

Variable that tracks if BAC has written to the time buffer this cycle.

Used to tell CPU if there is activity this cycle.

Definition at line 366 of file bac.hh.

Referenced by BAC(), generateFetchTargets(), and resetStage().

The documentation for this class was generated from the following files:

cpu/o3/bac.hh
cpu/o3/bac.cc

Classes

Public Types

Public Member Functions

Protected Attributes

Private Types

Private Member Functions

Private Attributes

Detailed Description

Member Typedef Documentation

◆ BranchType

Member Enumeration Documentation

◆ BACStatus

◆ ThreadStatus

Constructor & Destructor Documentation

◆ BAC()

Member Function Documentation

◆ alignToCacheBlock()

◆ checkAndUpdateBPUSignals()

◆ checkSignalsAndUpdate()

◆ checkStall()

◆ clearStates()

◆ deactivateThread()

◆ drainResume()

◆ drainSanityCheck()

◆ drainStall()

◆ generateFetchTargets()

◆ isDrained()

◆ name()

◆ newFetchTarget()

◆ predict()

◆ regProbePoints()

◆ resetStage()

◆ setActiveThreads()

◆ setFetchTargetQueue()

◆ setTimeBuffer()

◆ squash()

◆ squashBpuHistories()

◆ startupStage()

◆ switchToActive()

◆ switchToInactive()

◆ takeOverFrom()

◆ tick()

◆ updateBACStatus()

◆ updatePC()

◆ updatePreDecode()

Member Data Documentation

◆ _status

◆ activeThreads

◆ bacPC

◆ bacStatus

◆ bacToFetchDelay

◆ bpu

◆ cacheBlkSize

◆ commitToFetchDelay

◆ cpu

◆ decodeToFetchDelay

◆ decoupledFrontEnd

◆ fetchTargetWidth

◆ fetchToBacDelay

◆ fromCommit

◆ fromDecode

◆ fromFetch

◆ ftq

◆ maxFTPerCycle

◆ maxTakenPredPerCycle

◆ minInstSize

◆ numThreads

◆ stalls

◆ stats

◆ timeBuffer

◆ toFetch

◆ wroteToTimeBuffer