fetch.hh

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#ifndef __CPU_O3_FETCH_HH__
#define __CPU_O3_FETCH_HH__
 
#include "arch/generic/decoder.hh"
#include "arch/generic/mmu.hh"
#include "base/random.hh"
#include "base/statistics.hh"
#include "cpu/o3/bac.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/ftq.hh"
#include "cpu/o3/limits.hh"
#include "cpu/pc_event.hh"
#include "cpu/pred/bpred_unit.hh"
#include "cpu/timebuf.hh"
#include "cpu/translation.hh"
#include "enums/SMTFetchPolicy.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
struct BaseO3CPUParams;
 
namespace o3
{
 
class CPU;

class Fetch
{
  public:
    class IcachePort : public RequestPort
    {
      protected:
        Fetch *fetch;
 
      public:
        IcachePort(Fetch *_fetch, CPU *_cpu);
 
      protected:

        virtual bool recvTimingResp(PacketPtr pkt);

        virtual void recvReqRetry();
    };
 
    class FetchTranslation : public BaseMMU::Translation
    {
      protected:
        Fetch *fetch;
 
      public:
        FetchTranslation(Fetch *_fetch) : fetch(_fetch) {}
 
        void markDelayed() {}
 
        void
        finish(const Fault &fault, const RequestPtr &req,
            gem5::ThreadContext *tc, BaseMMU::Mode mode)
        {
            assert(mode == BaseMMU::Execute);
            fetch->finishTranslation(fault, req);
            delete this;
        }
    };
 
  private:
    /* Event to delay delivery of a fetch translation result in case of
     * a fault and the nop to carry the fault cannot be generated
     * immediately */
    class FinishTranslationEvent : public Event
    {
      private:
        Fetch *fetch;
        Fault fault;
        RequestPtr req;
 
      public:
        FinishTranslationEvent(Fetch *_fetch)
            : fetch(_fetch), req(nullptr)
        {}
 
        void setFault(Fault _fault) { fault = _fault; }
        void setReq(const RequestPtr &_req) { req = _req; }

        void
        process()
        {
            assert(fetch->numInst < fetch->fetchWidth);
            fetch->finishTranslation(fault, req);
        }
 
        const char *
        description() const
        {
            return "CPU FetchFinishTranslation";
        }
      };
 
  public:
    enum FetchStatus
    {
        Active,
        Inactive
    };

    enum ThreadStatus
    {
        Running,
        Idle,
        Squashing,
        Blocked,
        Fetching,
        TrapPending,
        QuiescePending,
        ItlbWait,
        IcacheWaitResponse,
        IcacheWaitRetry,
        IcacheAccessComplete,
        FTQEmpty,
        NoGoodAddr
    };
 
  private:
    FetchStatus _status;

    ThreadStatus fetchStatus[MaxThreads];

    SMTFetchPolicy fetchPolicy;

    std::list<ThreadID> priorityList;

    ProbePointArg<DynInstPtr> *ppFetch;
    ProbePointArg<RequestPtr> *ppFetchRequestSent;
 
    Random::RandomPtr rng = Random::genRandom();
 
  public:
    Fetch(CPU *_cpu, const BaseO3CPUParams &params);

    std::string name() const;
 

    void regProbePoints();

    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);

    void setActiveThreads(std::list<ThreadID> *at_ptr);

    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);

    void setBACandFTQPtr(BAC *bac_ptr, FTQ *ftq_ptr);

    void startupStage();

    void clearStates(ThreadID tid);

    void recvReqRetry();

    void processCacheCompletion(PacketPtr pkt);

    void drainResume();

    void drainSanityCheck() const;

    bool isDrained() const;

    void takeOverFrom();

    void drainStall(ThreadID tid);

    void wakeFromQuiesce();

    void deactivateThread(ThreadID tid);
  private:
    void resetStage();

    void switchToActive();

    void switchToInactive();

    bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
    void finishTranslation(const Fault &fault, const RequestPtr &mem_req);
 

    bool checkInterrupt(Addr pc) { return interruptPending; }

    void doSquash(const PCStateBase &new_pc, const DynInstPtr squashInst,
            ThreadID tid);

    void squashFromDecode(const PCStateBase &new_pc,
                          const DynInstPtr squashInst,
                          const InstSeqNum seq_num, ThreadID tid);

    void bacResteer(const PCStateBase &new_pc, ThreadID tid);

    bool checkStall(ThreadID tid) const;

    bool ftqReady(ThreadID tid, bool &status_change);

    FetchStatus updateFetchStatus();
 
  public:
    void squashFromCommit(const PCStateBase &new_pc, const InstSeqNum seq_num,
                          DynInstPtr squashInst, ThreadID tid);

    void tick();

    bool checkSignalsAndUpdate(ThreadID tid);

    void fetch(bool &status_change);

    Addr fetchBufferAlignPC(Addr addr)
    {
        return (addr & ~(fetchBufferMask));
    }

    InstDecoder *decoder[MaxThreads];
 
    RequestPort &getInstPort() { return icachePort; }
 
  private:
    DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
            StaticInstPtr curMacroop, const PCStateBase &this_pc,
            const PCStateBase &next_pc, bool trace);

    ThreadID getFetchingThread();

    ThreadID roundRobin();

    ThreadID iqCount();

    ThreadID lsqCount();

    ThreadID branchCount();

    void pipelineIcacheAccesses(ThreadID tid);

    void profileStall(ThreadID tid);
 
  private:
    CPU *cpu;

    TimeBuffer<TimeStruct> *timeBuffer;

    TimeBuffer<TimeStruct>::wire fromDecode;

    TimeBuffer<TimeStruct>::wire fromRename;

    TimeBuffer<TimeStruct>::wire fromIEW;

    TimeBuffer<TimeStruct>::wire fromCommit;

    TimeBuffer<TimeStruct>::wire toBAC;
 
    //Might be annoying how this name is different than the queue.
    TimeBuffer<FetchStruct>::wire toDecode;

    BAC *bac;

    FTQ *ftq;
 
    std::unique_ptr<PCStateBase> pc[MaxThreads];
 
    Addr fetchOffset[MaxThreads];
 
    StaticInstPtr macroop[MaxThreads];

    bool delayedCommit[MaxThreads];

    RequestPtr memReq[MaxThreads];

    bool wroteToTimeBuffer;

    int numInst;

    struct Stalls
    {
        bool decode;
        bool drain;
    };

    Stalls stalls[MaxThreads];

    const bool decoupledFrontEnd;

    const Cycles decodeToFetchDelay;

    const Cycles renameToFetchDelay;

    const Cycles iewToFetchDelay;

    const Cycles commitToFetchDelay;

    const unsigned fetchWidth;

    const unsigned decodeWidth;

    bool cacheBlocked;

    PacketPtr retryPkt;

    ThreadID retryTid;

    Addr cacheBlkSize;

    unsigned fetchBufferSize;

    Addr fetchBufferMask;

    uint8_t *fetchBuffer[MaxThreads];

    Addr fetchBufferPC[MaxThreads];

    unsigned fetchQueueSize;

    std::deque<DynInstPtr> fetchQueue[MaxThreads];

    bool fetchBufferValid[MaxThreads];

    int instSize;

    Counter lastIcacheStall[MaxThreads];

    std::list<ThreadID> *activeThreads;

    ThreadID numThreads;

    ThreadID numFetchingThreads;

    ThreadID threadFetched;

    bool interruptPending;

    IcachePort icachePort;

    bool issuePipelinedIfetch[MaxThreads];

    FinishTranslationEvent finishTranslationEvent;
 
    /*Max number of FT added to the FTQ per Cycle*/
    const unsigned maxFTPerCycle;
    const unsigned maxTakenPredPerCycle;
 
  protected:
    struct FetchStatGroup : public statistics::Group
    {
        FetchStatGroup(CPU *cpu, Fetch *fetch);
        // @todo: Consider making these
        // vectors and tracking on a per thread basis.
        statistics::Scalar predictedBranches;
        statistics::Scalar cycles;
        statistics::Scalar squashCycles;
        statistics::Scalar tlbCycles;
        statistics::Scalar ftqStallCycles;
        statistics::Scalar idleCycles;
        statistics::Scalar blockedCycles;
        statistics::Scalar miscStallCycles;
        statistics::Scalar pendingDrainCycles;
        statistics::Scalar noActiveThreadStallCycles;
        statistics::Scalar pendingTrapStallCycles;
        statistics::Scalar pendingQuiesceStallCycles;
        statistics::Scalar icacheWaitRetryStallCycles;
        statistics::Scalar cacheLines;
        statistics::Scalar icacheSquashes;
        statistics::Scalar tlbSquashes;
        statistics::Distribution nisnDist;
        statistics::Formula idleRate;
        /*Number of fetch target processed per cycle*/
        statistics::Distribution ftNumber;
    } fetchStats;
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_FETCH_HH__