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thread_context.hh
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41 
42 #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
43 #define __CPU_CHECKER_THREAD_CONTEXT_HH__
44 
45 #include "arch/generic/pcstate.hh"
46 #include "cpu/checker/cpu.hh"
47 #include "cpu/simple_thread.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/Checker.hh"
50 
51 namespace gem5
52 {
53 
62 template <class TC>
64 {
65  public:
66  CheckerThreadContext(TC *actual_tc,
67  CheckerCPU *checker_cpu)
68  : actualTC(actual_tc), checkerTC(checker_cpu->thread),
69  checkerCPU(checker_cpu)
70  { }
71 
72  private:
75  TC *actualTC;
82 
83  public:
84  bool
85  schedule(PCEvent *e) override
86  {
87  [[maybe_unused]] bool check_ret = checkerTC->schedule(e);
88  bool actual_ret = actualTC->schedule(e);
89  assert(actual_ret == check_ret);
90  return actual_ret;
91  }
92 
93  bool
94  remove(PCEvent *e) override
95  {
96  [[maybe_unused]] bool check_ret = checkerTC->remove(e);
97  bool actual_ret = actualTC->remove(e);
98  assert(actual_ret == check_ret);
99  return actual_ret;
100  }
101 
102  void
104  {
105  actualTC->scheduleInstCountEvent(event, count);
106  }
107  void
109  {
110  actualTC->descheduleInstCountEvent(event);
111  }
112  Tick
114  {
115  return actualTC->getCurrentInstCount();
116  }
117 
118  BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
119 
120  uint32_t socketId() const override { return actualTC->socketId(); }
121 
122  int cpuId() const override { return actualTC->cpuId(); }
123 
124  ContextID contextId() const override { return actualTC->contextId(); }
125 
126  void
127  setContextId(ContextID id) override
128  {
129  actualTC->setContextId(id);
130  checkerTC->setContextId(id);
131  }
132 
134  int threadId() const override { return actualTC->threadId(); }
135  void
136  setThreadId(int id) override
137  {
138  checkerTC->setThreadId(id);
139  actualTC->setThreadId(id);
140  }
141 
142  BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
143 
144  CheckerCPU *
145  getCheckerCpuPtr() override
146  {
147  return checkerCPU;
148  }
149 
150  BaseISA *getIsaPtr() const override { return actualTC->getIsaPtr(); }
151 
152  InstDecoder *
153  getDecoderPtr() override
154  {
155  return actualTC->getDecoderPtr();
156  }
157 
158  System *getSystemPtr() override { return actualTC->getSystemPtr(); }
159 
160  Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
161 
162  void setProcessPtr(Process *p) override { actualTC->setProcessPtr(p); }
163 
164  void
166  {
167  actualTC->connectMemPorts(tc);
168  }
169 
170  Status status() const override { return actualTC->status(); }
171 
172  void
173  setStatus(Status new_status) override
174  {
175  actualTC->setStatus(new_status);
176  checkerTC->setStatus(new_status);
177  }
178 
180  void activate() override { actualTC->activate(); }
181 
183  void suspend() override { actualTC->suspend(); }
184 
186  void halt() override { actualTC->halt(); }
187 
188  void
189  takeOverFrom(ThreadContext *oldContext) override
190  {
191  actualTC->takeOverFrom(oldContext);
192  checkerTC->copyState(oldContext);
193  }
194 
195  void
196  regStats(const std::string &name) override
197  {
198  actualTC->regStats(name);
200  }
201 
202  Tick readLastActivate() override { return actualTC->readLastActivate(); }
203  Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
204 
205  // @todo: Do I need this?
206  void
208  {
209  actualTC->copyArchRegs(tc);
210  checkerTC->copyArchRegs(tc);
211  }
212 
213  void
214  clearArchRegs() override
215  {
216  actualTC->clearArchRegs();
218  }
219 
220  //
221  // New accessors for new decoder.
222  //
223  RegVal
224  getReg(const RegId &reg) const override
225  {
226  return actualTC->getReg(reg);
227  }
228 
229  void
230  getReg(const RegId &reg, void *val) const override
231  {
232  actualTC->getReg(reg, val);
233  }
234 
235  void *
236  getWritableReg(const RegId &reg) override
237  {
238  return actualTC->getWritableReg(reg);
239  }
240 
241  void
242  setReg(const RegId &reg, RegVal val) override
243  {
244  actualTC->setReg(reg, val);
245  checkerTC->setReg(reg, val);
246  }
247 
248  void
249  setReg(const RegId &reg, const void *val) override
250  {
251  actualTC->setReg(reg, val);
252  checkerTC->setReg(reg, val);
253  }
254 
256  const PCStateBase &pcState() const override { return actualTC->pcState(); }
257 
259  void
260  pcState(const PCStateBase &val) override
261  {
262  DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
263  val, checkerTC->pcState());
266  return actualTC->pcState(val);
267  }
268 
269  void
270  pcStateNoRecord(const PCStateBase &val) override
271  {
272  return actualTC->pcState(val);
273  }
274 
275  RegVal
276  readMiscRegNoEffect(RegIndex misc_reg) const override
277  {
278  return actualTC->readMiscRegNoEffect(misc_reg);
279  }
280 
281  RegVal
282  readMiscReg(RegIndex misc_reg) override
283  {
284  return actualTC->readMiscReg(misc_reg);
285  }
286 
287  void
288  setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
289  {
290  DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
291  " and O3..\n", misc_reg);
292  checkerTC->setMiscRegNoEffect(misc_reg, val);
293  actualTC->setMiscRegNoEffect(misc_reg, val);
294  }
295 
296  void
297  setMiscReg(RegIndex misc_reg, RegVal val) override
298  {
299  DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
300  " and O3..\n", misc_reg);
301  checkerTC->setMiscReg(misc_reg, val);
302  actualTC->setMiscReg(misc_reg, val);
303  }
304 
305  unsigned
306  readStCondFailures() const override
307  {
308  return actualTC->readStCondFailures();
309  }
310 
311  void
312  setStCondFailures(unsigned sc_failures) override
313  {
314  actualTC->setStCondFailures(sc_failures);
315  }
316 
317  // hardware transactional memory
318  void
319  htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
320  {
321  panic("function not implemented");
322  }
323 
326  {
327  return actualTC->getHtmCheckpointPtr();
328  }
329 
330  void
332  {
333  panic("function not implemented");
334  }
335 
336 };
337 
338 } // namespace gem5
339 
340 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
gem5::CheckerThreadContext::cpuId
int cpuId() const override
Definition: thread_context.hh:122
gem5::CheckerThreadContext::CheckerThreadContext
CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu)
Definition: thread_context.hh:66
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::CheckerThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: thread_context.hh:297
gem5::CheckerThreadContext::setReg
void setReg(const RegId &reg, const void *val) override
Definition: thread_context.hh:249
gem5::CheckerThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.hh:113
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::CheckerThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.hh:186
gem5::CheckerThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.hh:108
gem5::CheckerThreadContext::pcState
const PCStateBase & pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:256
gem5::CheckerThreadContext::socketId
uint32_t socketId() const override
Definition: thread_context.hh:120
gem5::SimpleThread::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: simple_thread.cc:167
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::CheckerThreadContext::checkerTC
SimpleThread * checkerTC
The checker's own SimpleThread.
Definition: thread_context.hh:79
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:776
gem5::SimpleThread::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:287
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:99
gem5::CheckerThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: thread_context.hh:288
gem5::CheckerThreadContext::getReg
RegVal getReg(const RegId &reg) const override
Definition: thread_context.hh:224
gem5::SimpleThread::remove
bool remove(PCEvent *e) override
Definition: simple_thread.hh:178
gem5::SimpleThread::clearArchRegs
void clearArchRegs() override
Definition: simple_thread.hh:245
gem5::ThreadContext::regStats
virtual void regStats(const std::string &name)
Definition: thread_context.hh:172
gem5::SimpleThread::setContextId
void setContextId(ContextID id) override
Definition: simple_thread.hh:203
gem5::CheckerThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.hh:94
gem5::CheckerThreadContext::actualTC
TC * actualTC
The main CPU's ThreadContext, or class that implements the ThreadContext interface.
Definition: thread_context.hh:75
gem5::CheckerThreadContext
Derived ThreadContext class for use with the Checker.
Definition: thread_context.hh:63
gem5::CheckerThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.hh:103
gem5::SimpleThread::setReg
void setReg(const RegId &arch_reg, RegVal val) override
Definition: simple_thread.hh:355
gem5::CheckerThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: thread_context.hh:282
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:93
gem5::SimpleThread::setThreadId
void setThreadId(int id) override
Definition: simple_thread.hh:201
gem5::BaseMMU
Definition: mmu.hh:53
gem5::CheckerThreadContext::readLastActivate
Tick readLastActivate() override
Definition: thread_context.hh:202
gem5::CheckerThreadContext::getReg
void getReg(const RegId &reg, void *val) const override
Definition: thread_context.hh:230
gem5::CheckerThreadContext::getSystemPtr
System * getSystemPtr() override
Definition: thread_context.hh:158
gem5::CheckerThreadContext::getCpuPtr
BaseCPU * getCpuPtr() override
Definition: thread_context.hh:118
gem5::CheckerThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:183
gem5::CheckerThreadContext::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: thread_context.hh:145
gem5::CheckerThreadContext::readLastSuspend
Tick readLastSuspend() override
Definition: thread_context.hh:203
gem5::System
Definition: system.hh:74
gem5::CheckerThreadContext::takeOverFrom
void takeOverFrom(ThreadContext *oldContext) override
Definition: thread_context.hh:189
gem5::SimpleThread::copyState
void copyState(ThreadContext *oldContext)
Definition: simple_thread.cc:107
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::CheckerThreadContext::setReg
void setReg(const RegId &reg, RegVal val) override
Definition: thread_context.hh:242
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::CheckerThreadContext::clearArchRegs
void clearArchRegs() override
Definition: thread_context.hh:214
gem5::InstDecoder
Definition: decoder.hh:42
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:210
gem5::CheckerThreadContext::connectMemPorts
void connectMemPorts(ThreadContext *tc)
Definition: thread_context.hh:165
gem5::Event
Definition: eventq.hh:254
gem5::X86ISA::count
count
Definition: misc.hh:710
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::SimpleThread::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Definition: simple_thread.hh:281
cpu.hh
gem5::CheckerThreadContext::getWritableReg
void * getWritableReg(const RegId &reg) override
Definition: thread_context.hh:236
gem5::CheckerThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.hh:331
gem5::BaseCPU
Definition: base.hh:104
gem5::CheckerThreadContext::setProcessPtr
void setProcessPtr(Process *p) override
Definition: thread_context.hh:162
gem5::CheckerThreadContext::copyArchRegs
void copyArchRegs(ThreadContext *tc) override
Definition: thread_context.hh:207
gem5::SimpleThread::schedule
bool schedule(PCEvent *e) override
Definition: simple_thread.hh:177
gem5::CheckerThreadContext::contextId
ContextID contextId() const override
Definition: thread_context.hh:124
gem5::CheckerThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.hh:319
gem5::SimpleThread::pcState
const PCStateBase & pcState() const override
Definition: simple_thread.hh:256
gem5::CheckerCPU::recordPCChange
void recordPCChange(const PCStateBase &val)
Definition: cpu.hh:336
name
const std::string & name()
Definition: trace.cc:48
gem5::SimpleThread::setStatus
void setStatus(Status newStatus) override
Definition: simple_thread.hh:220
gem5::CheckerThreadContext::checkerCPU
CheckerCPU * checkerCPU
Pointer to the checker CPU.
Definition: thread_context.hh:81
gem5::CheckerThreadContext::pcStateNoRecord
void pcStateNoRecord(const PCStateBase &val) override
Definition: thread_context.hh:270
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:67
pcstate.hh
gem5::CheckerThreadContext::getIsaPtr
BaseISA * getIsaPtr() const override
Definition: thread_context.hh:150
simple_thread.hh
gem5::CheckerThreadContext::pcState
void pcState(const PCStateBase &val) override
Sets this thread's PC state.
Definition: thread_context.hh:260
gem5::CheckerThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.hh:85
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::CheckerThreadContext::status
Status status() const override
Definition: thread_context.hh:170
gem5::CheckerThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.hh:325
gem5::CheckerThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.hh:180
gem5::CheckerThreadContext::setContextId
void setContextId(ContextID id) override
Definition: thread_context.hh:127
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::BaseISA
Definition: isa.hh:58
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::CheckerThreadContext::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: thread_context.hh:312
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::CheckerThreadContext::regStats
void regStats(const std::string &name) override
Definition: thread_context.hh:196
gem5::CheckerThreadContext::setStatus
void setStatus(Status new_status) override
Definition: thread_context.hh:173
gem5::CheckerThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.hh:276
gem5::Checker
Templated Checker class.
Definition: cpu.hh:447
gem5::CheckerThreadContext::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: thread_context.hh:153
thread_context.hh
gem5::CheckerThreadContext::readStCondFailures
unsigned readStCondFailures() const override
Definition: thread_context.hh:306
gem5::CheckerThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:134
gem5::CheckerThreadContext::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: thread_context.hh:142
gem5::CheckerThreadContext::getProcessPtr
Process * getProcessPtr() override
Definition: thread_context.hh:160
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:92
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:188
gem5::CheckerThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:136

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