tlb.hh File Reference

#include <list>
#include <queue>
#include <string>
#include <vector>
#include "arch/amdgpu/vega/pagetable.hh"
#include "arch/generic/mmu.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "params/VegaGPUTLB.hh"
#include "sim/clocked_object.hh"

Go to the source code of this file.

Classes
class	gem5::VegaISA::GpuTLB
class	gem5::VegaISA::GpuTLB::Translation
struct	gem5::VegaISA::GpuTLB::VegaTLBStats
class	gem5::VegaISA::GpuTLB::CpuSidePort
class	gem5::VegaISA::GpuTLB::MemSidePort
	MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected. More...
class	gem5::VegaISA::GpuTLB::TLBEvent

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::VegaISA
	classes that represnt vector/scalar operands in VEGA ISA.