gem5 v24.1.0.1
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mmu.hh
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1/*
2 * Copyright (c) 2020-2021 Arm Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __ARCH_GENERIC_MMU_HH__
39#define __ARCH_GENERIC_MMU_HH__
40
41#include <set>
42
43#include "mem/request.hh"
45#include "params/BaseMMU.hh"
46#include "sim/sim_object.hh"
47
48namespace gem5
49{
50
51class BaseTLB;
52
53class BaseMMU : public SimObject
54{
55 public:
56 enum Mode { Read, Write, Execute };
57
59 {
60 public:
61 virtual ~Translation()
62 {}
63
68 virtual void markDelayed() = 0;
69
70 /*
71 * The memory for this object may be dynamically allocated, and it may
72 * be responsible for cleaning itself up which will happen in this
73 * function. Once it's called, the object is no longer valid.
74 */
75 virtual void finish(const Fault &fault, const RequestPtr &req,
77
84 virtual bool squashed() const { return false; }
85 };
86
87 protected:
88 typedef BaseMMUParams Params;
89
91 : SimObject(p), dtb(p.dtb), itb(p.itb)
92 {}
93
94 BaseTLB*
96 {
97 if (mode == Execute)
98 return itb;
99 else
100 return dtb;
101 }
102
103 public:
108 void init() override;
109
110 virtual void flushAll();
111
112 virtual void reset();
113
114 void demapPage(Addr vaddr, uint64_t asn);
115
116 virtual Fault
118 Mode mode);
119
120 virtual void
122 Translation *translation, Mode mode);
123
124 virtual Fault
126 Mode mode);
127
129
131 {
132 private:
139
140 void translate(Range &range) const override;
141
142 public:
143 MMUTranslationGen(Addr page_bytes, Addr new_start, Addr new_size,
144 ThreadContext *new_tc, BaseMMU *new_mmu,
145 BaseMMU::Mode new_mode, Request::Flags new_flags);
146 };
147
154
155 virtual Fault
157 Mode mode) const;
158
159 virtual void takeOverFrom(BaseMMU *old_mmu);
160
161 public:
164
165 protected:
185 std::set<BaseTLB*> instruction;
186 std::set<BaseTLB*> data;
187 std::set<BaseTLB*> unified;
188
189};
190
191} // namespace gem5
192
193#endif
void translate(Range &range) const override
Subclasses implement this function to complete TranslationGen.
Definition mmu.cc:153
virtual ~Translation()
Definition mmu.hh:61
virtual bool squashed() const
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition mmu.hh:84
virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
virtual void markDelayed()=0
Signal that the translation has been delayed due to a hw page table walk.
std::set< BaseTLB * > instruction
It is possible from the MMU to traverse the entire hierarchy of TLBs, starting from the DTB and ITB (...
Definition mmu.hh:185
virtual void reset()
Definition mmu.cc:97
BaseMMUParams Params
Definition mmu.hh:88
BaseTLB * getTlb(Mode mode) const
Definition mmu.hh:95
void init() override
Called at init time, this method is traversing the TLB hierarchy and pupulating the instruction/data/...
Definition mmu.cc:53
virtual Addr getValidAddr(Addr vaddr, ThreadContext *tc, Mode mode)
Definition mmu.cc:132
virtual void flushAll()
Definition mmu.cc:81
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition mmu.cc:125
virtual TranslationGenPtr translateFunctional(Addr start, Addr size, ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags)=0
Returns a translation generator for a region of virtual addresses, instead of directly translating a ...
BaseTLB * itb
Definition mmu.hh:163
virtual void takeOverFrom(BaseMMU *old_mmu)
Definition mmu.cc:172
void demapPage(Addr vaddr, uint64_t asn)
Definition mmu.cc:104
std::set< BaseTLB * > data
Definition mmu.hh:186
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)
Definition mmu.cc:118
std::set< BaseTLB * > unified
Definition mmu.hh:187
BaseMMU(const Params &p)
Definition mmu.hh:90
BaseTLB * dtb
Definition mmu.hh:162
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition mmu.cc:111
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const
Definition mmu.cc:138
Abstract superclass for simulation objects.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
TranslationGen is a base class for a generator object which returns information about address transla...
uint8_t flags
Definition helpers.cc:87
Bitfield< 4, 0 > mode
Definition misc_types.hh:74
Bitfield< 0 > p
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int ContextID
Globally unique thread context ID.
Definition types.hh:239
std::unique_ptr< TranslationGen > TranslationGenPtr
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
This structure represents a single, contiguous translation, or carries information about whatever fau...

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