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amdgpu
amdgpu_defines.hh
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/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_AMDGPU_AMDGPU_DEFINES_HH__
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#define __DEV_AMDGPU_AMDGPU_DEFINES_HH__
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#include "
base/types.hh
"
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namespace
gem5
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{
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/* Types of queues supported by device */
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enum
QueueType
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{
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Compute
,
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Gfx
,
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SDMAGfx
,
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SDMAPage
,
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ComputeAQL
,
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InterruptHandler
,
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RLC
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};
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/*
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* Hold information about doorbells including queue type and the IP
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* block ID if the IP can have multiple instances.
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*/
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typedef
struct
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{
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QueueType
qtype
;
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int
ip_id
;
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}
DoorbellInfo
;
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// AMD GPUs support 16 different virtual address spaces
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static
constexpr
int
AMDGPU_VM_COUNT
= 16;
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/* Names of BARs used by the device. */
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constexpr
int
FRAMEBUFFER_BAR
= 0;
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constexpr
int
DOORBELL_BAR
= 2;
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constexpr
int
MMIO_BAR
= 5;
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/* By default the X86 kernel expects the vga ROM at 0xc0000. */
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constexpr
uint32_t
VGA_ROM_DEFAULT
= 0xc0000;
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constexpr
uint32_t
ROM_SIZE
= 0x20000;
// 128kB
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/* Most MMIOs use DWORD addresses and thus need to be shifted. */
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static
constexpr
uint32_t
IH_OFFSET_SHIFT
= 2;
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static
constexpr
uint32_t
GRBM_OFFSET_SHIFT
= 2;
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static
constexpr
uint32_t
MMHUB_OFFSET_SHIFT
= 2;
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}
// namespace gem5
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#endif
// __DEV_AMDGPU_AMDGPU_DEFINES_HH__
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition
binary32.hh:36
gem5::MMIO_BAR
constexpr int MMIO_BAR
Definition
amdgpu_defines.hh:68
gem5::QueueType
QueueType
Definition
amdgpu_defines.hh:42
gem5::SDMAGfx
@ SDMAGfx
Definition
amdgpu_defines.hh:45
gem5::Compute
@ Compute
Definition
amdgpu_defines.hh:43
gem5::RLC
@ RLC
Definition
amdgpu_defines.hh:49
gem5::InterruptHandler
@ InterruptHandler
Definition
amdgpu_defines.hh:48
gem5::Gfx
@ Gfx
Definition
amdgpu_defines.hh:44
gem5::ComputeAQL
@ ComputeAQL
Definition
amdgpu_defines.hh:47
gem5::SDMAPage
@ SDMAPage
Definition
amdgpu_defines.hh:46
gem5::ROM_SIZE
constexpr uint32_t ROM_SIZE
Definition
amdgpu_defines.hh:72
gem5::IH_OFFSET_SHIFT
static constexpr uint32_t IH_OFFSET_SHIFT
Definition
amdgpu_defines.hh:75
gem5::MMHUB_OFFSET_SHIFT
static constexpr uint32_t MMHUB_OFFSET_SHIFT
Definition
amdgpu_defines.hh:77
gem5::AMDGPU_VM_COUNT
static constexpr int AMDGPU_VM_COUNT
Definition
amdgpu_defines.hh:63
gem5::FRAMEBUFFER_BAR
constexpr int FRAMEBUFFER_BAR
Definition
amdgpu_defines.hh:66
gem5::DOORBELL_BAR
constexpr int DOORBELL_BAR
Definition
amdgpu_defines.hh:67
gem5::VGA_ROM_DEFAULT
constexpr uint32_t VGA_ROM_DEFAULT
Definition
amdgpu_defines.hh:71
gem5::GRBM_OFFSET_SHIFT
static constexpr uint32_t GRBM_OFFSET_SHIFT
Definition
amdgpu_defines.hh:76
gem5::DoorbellInfo
Definition
amdgpu_defines.hh:57
gem5::DoorbellInfo::qtype
QueueType qtype
Definition
amdgpu_defines.hh:58
gem5::DoorbellInfo::ip_id
int ip_id
Definition
amdgpu_defines.hh:59
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