gem5  v21.2.1.1
htm.hh
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37 
38 #ifndef __ARCH_ARM_HTM_HH__
39 #define __ARCH_ARM_HTM_HH__
40 
47 #include "arch/arm/regs/int.hh"
48 #include "arch/arm/regs/vec.hh"
49 #include "arch/generic/htm.hh"
50 #include "base/types.hh"
51 
52 namespace gem5
53 {
54 
55 namespace ArmISA
56 {
57 
59 {
60  public:
63  {}
64 
65  const static int MAX_HTM_DEPTH = 255;
66 
67  void reset() override;
68  void save(ThreadContext *tc) override;
69  void restore(ThreadContext *tc, HtmFailureFaultCause cause) override;
70 
71  void destinationRegister(RegIndex dest) { rt = dest; }
72  void cancelReason(uint16_t reason) { tcreason = reason; }
73 
74  private:
75  uint8_t rt; // TSTART destination register
76  Addr nPc; // Fallback instruction address
77  std::array<RegVal, NUM_ARCH_INTREGS> x; // General purpose registers
78  std::array<VecRegContainer, NumVecRegs> z; // Vector registers
79  std::array<VecPredRegContainer, NumVecRegs> p; // Predicate registers
80  Addr sp; // Stack Pointer at current EL
81  uint16_t tcreason; // TCANCEL reason
82  uint32_t fpcr; // Floating-point Control Register
83  uint32_t fpsr; // Floating-point Status Register
84  uint32_t iccPmrEl1; // Interrupt Controller Interrupt Priority Mask
85  uint8_t nzcv; // Condition flags
86  uint8_t daif;
88 };
89 
90 } // namespace ArmISA
91 } // namespace gem5
92 
93 #endif
gem5::ArmISA::HTMCheckpoint::iccPmrEl1
uint32_t iccPmrEl1
Definition: htm.hh:84
htm.hh
gem5::BaseHTMCheckpoint
Transactional Memory checkpoint.
Definition: htm.hh:132
gem5::ArmISA::HTMCheckpoint::nPc
Addr nPc
Definition: htm.hh:76
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::ArmISA::HTMCheckpoint::sp
Addr sp
Definition: htm.hh:80
gem5::ArmISA::HTMCheckpoint::save
void save(ThreadContext *tc) override
Every ISA implementing HTM support should override the save method.
Definition: htm.cc:72
vec.hh
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::HTMCheckpoint::destinationRegister
void destinationRegister(RegIndex dest)
Definition: htm.hh:71
gem5::ArmISA::HTMCheckpoint::MAX_HTM_DEPTH
const static int MAX_HTM_DEPTH
Definition: htm.hh:65
gem5::ArmISA::HTMCheckpoint::tcreason
uint16_t tcreason
Definition: htm.hh:81
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ArmISA::HTMCheckpoint::HTMCheckpoint
HTMCheckpoint()
Definition: htm.hh:61
gem5::ArmISA::HTMCheckpoint::z
std::array< VecRegContainer, NumVecRegs > z
Definition: htm.hh:78
gem5::ArmISA::HTMCheckpoint::reset
void reset() override
Resets the checkpoint once a transaction has completed.
Definition: htm.cc:48
gem5::ArmISA::HTMCheckpoint::fpsr
uint32_t fpsr
Definition: htm.hh:83
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::HTMCheckpoint::nzcv
uint8_t nzcv
Definition: htm.hh:85
gem5::ArmISA::HTMCheckpoint
Definition: htm.hh:58
gem5::ArmISA::HTMCheckpoint::rt
uint8_t rt
Definition: htm.hh:75
types.hh
gem5::ArmISA::HTMCheckpoint::x
std::array< RegVal, NUM_ARCH_INTREGS > x
Definition: htm.hh:77
gem5::ArmISA::HTMCheckpoint::fpcr
uint32_t fpcr
Definition: htm.hh:82
gem5::ArmISA::HTMCheckpoint::p
std::array< VecPredRegContainer, NumVecRegs > p
Definition: htm.hh:79
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmISA::HTMCheckpoint::cancelReason
void cancelReason(uint16_t reason)
Definition: htm.hh:72
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::HTMCheckpoint::pcstateckpt
PCState pcstateckpt
Definition: htm.hh:87
gem5::ArmISA::HTMCheckpoint::daif
uint8_t daif
Definition: htm.hh:86
int.hh
gem5::ArmISA::HTMCheckpoint::restore
void restore(ThreadContext *tc, HtmFailureFaultCause cause) override
Every ISA implementing HTM support should override the restore method.
Definition: htm.cc:99

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