gem5  v21.1.0.2
htm.hh
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37 
38 /*
39  * Gem5 Hardware Transactional Memory (HTM)
40  *
41  * Here we provide a brief note describing HTM support in Gem5 at
42  * a high level.
43  *
44  * HTM is an architectural feature that enables speculative
45  * concurrency in a shared-memory system; groups of instructions known as
46  * transactions are executed as an atomic unit. The system allows that
47  * transactions be executed concurrently but intervenes if a transaction's
48  * atomicity/isolation is jeapordised and takes corrective action. In this
49  * implementation, corrective active explicitely means rolling back a thread's
50  * architectural state and reverting any memory updates to a point just
51  * before the transaction began.
52  *
53  * This HTM implementation relies on--
54  * (1) A checkpointing mechanism for architectural register state.
55  * (2) Buffering speculative memory updates.
56  *
57  * The checkpointing mechanism is architecture dependent. Each ISA leveraging
58  * HTM support must define a class HTMCheckpoint in src/arch/theISA/htm.hh.
59  * Instances of this class live in O3's ThreadState and Atomic's SimpleThread.
60  * It is up to the ISA to populate this instance when executing an instruction
61  * that begins a new transaction.
62  *
63  * The buffering of speculative memory updates is currently implemented in
64  * the MESI_Three_Level Ruby protocol. The core notifies the L0 cache
65  * controller that a new transaction has started and the controller in turn
66  * places itself in transactional state (htmTransactionalState := true).
67  * When operating in transactional state, the usual MESI protocol changes
68  * slightly. Lines loaded or stored are marked as part of a transaction's
69  * read and write set respectively. If there is an invalidation request to
70  * cache line in the read/write set, the transaction is marked as failed.
71  * Similarly, if there is a read request by another core to a speculatively
72  * written cache line, i.e. in the write set, the transaction is marked as
73  * failed. If failed, all subsequent loads and stores from the core are
74  * made benign, i.e. made into NOPS at the cache controller, and responses are
75  * marked to indicate that the transactional state has failed. When the core
76  * receives these marked responses, it generates a HtmFailureFault with the
77  * reason for the transaction failure. Servicing this fault does two things--
78  * (a) Restores the architectural checkpoint
79  * (b) Sends an HTM abort signal to the cache controller
80  *
81  * The restoration includes all registers in the checkpoint as well as the
82  * program counter of the instruction before the transaction started.
83  *
84  * The abort signal is sent to the L0 cache controller and resets the
85  * failed transactional state. It resets the transactional read and write sets
86  * and invalidates any speculatively written cache lines. It also exits
87  * the transactional state so that the MESI protocol operates as usual.
88  *
89  * Alternatively, if the instructions within a transaction complete without
90  * triggering a HtmFailureFault, the transaction can be committed. The core
91  * is responsible for notifying the cache controller that the transaction is
92  * complete and the cache controller makes all speculative writes visible
93  * to the rest of the system and exits the transactional state.
94  *
95  * Notifting the cache controller is done through HtmCmd Requests which are
96  * a subtype of Load Requests.
97  *
98  * Most HTMs allow for a limited number of nested transactions, e.g. a nesting
99  * depth of two would be inside a transaction started within another
100  * transaction. The ExecContext class is extended with
101  * getHtmTransactionalDepth() to return the current depth. For the
102  * TimingSimpleCPU it is straightforward to track this, whereas for
103  * O3DerivCPU it must be tracked in the frontend and commit stages as well as
104  * be corrected on branch mispredictions. This is done in iew_impl.hh.
105  */
106 
107  #ifndef __ARCH_GENERIC_HTM_HH__
108  #define __ARCH_GENERIC_HTM_HH__
109 
110 #include <cstdint>
111 #include <memory>
112 
113 #include "mem/htm.hh"
114 
115 namespace gem5
116 {
117 
124 class ThreadContext;
126 
127 typedef std::unique_ptr<BaseHTMCheckpoint> BaseHTMCheckpointPtr;
128 
133 {
134  private:
135  static uint64_t globalHtmUid;
136  uint64_t localHtmUid;
137 
138  public:
140  {
141  reset();
142  }
143  virtual ~BaseHTMCheckpoint() {}
144 
153  virtual void
155  {
156  _valid = true;
157  }
158 
168  virtual void
170  {
171  reset();
172  }
173 
174  bool valid() const { return _valid; }
175 
179  uint64_t
181  {
183  return localHtmUid;
184  }
185 
189  uint64_t
190  getHtmUid() const
191  {
192  return localHtmUid;
193  }
194 
198  void
199  setHtmUid(uint64_t new_htm_uid)
200  {
201  localHtmUid = new_htm_uid;
202  }
203 
204  protected:
213  virtual void reset() { _valid = false; }
214  bool _valid;
215 };
216 
217 } // namespace gem5
218 
219 #endif // __ARCH_GENERIC_HTM_HH__
gem5::BaseHTMCheckpoint::~BaseHTMCheckpoint
virtual ~BaseHTMCheckpoint()
Definition: htm.hh:143
gem5::BaseHTMCheckpoint
Transactional Memory checkpoint.
Definition: htm.hh:132
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::BaseHTMCheckpoint::setHtmUid
void setHtmUid(uint64_t new_htm_uid)
Sets the current HTM identifier.
Definition: htm.hh:199
htm.hh
gem5::BaseHTMCheckpoint::localHtmUid
uint64_t localHtmUid
Definition: htm.hh:136
gem5::BaseHTMCheckpoint::restore
virtual void restore(ThreadContext *tc, HtmFailureFaultCause cause)
Every ISA implementing HTM support should override the restore method.
Definition: htm.hh:169
gem5::BaseHTMCheckpoint::getHtmUid
uint64_t getHtmUid() const
Returns the current HTM identifier.
Definition: htm.hh:190
gem5::BaseHTMCheckpoint::valid
bool valid() const
Definition: htm.hh:174
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::BaseHTMCheckpoint::BaseHTMCheckpoint
BaseHTMCheckpoint()
Definition: htm.hh:139
gem5::BaseHTMCheckpoint::reset
virtual void reset()
Resets the checkpoint once a transaction has completed.
Definition: htm.hh:213
gem5::BaseHTMCheckpoint::globalHtmUid
static uint64_t globalHtmUid
Definition: htm.hh:135
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseHTMCheckpoint::save
virtual void save(ThreadContext *tc)
Every ISA implementing HTM support should override the save method.
Definition: htm.hh:154
gem5::BaseHTMCheckpoint::newHtmUid
uint64_t newHtmUid()
Generates a new HTM identifier (used when starting a new transaction)
Definition: htm.hh:180
gem5::BaseHTMCheckpoint::_valid
bool _valid
Definition: htm.hh:214

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