gem5  v21.1.0.2
htm.cc
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37 
38 #include "arch/arm/htm.hh"
39 
40 #include "arch/arm/regs/int.hh"
41 #include "arch/arm/regs/misc.hh"
42 #include "cpu/thread_context.hh"
43 
44 namespace gem5
45 {
46 
47 void
49 {
50  rt = 0;
51  nPc = 0;
52  sp = 0;
53  fpcr = 0;
54  fpsr = 0;
55  iccPmrEl1 = 0;
56  nzcv = 0;
57  daif = 0;
58  tcreason = 0;
59  x.fill(0);
60  for (auto i = 0; i < NumVecRegs; ++i) {
61  z[i].zero();
62  }
63  for (auto i = 0; i < NumVecPredRegs; ++i) {
64  p[i].reset();
65  }
66  pcstateckpt = PCState();
67 
69 }
70 
71 void
73 {
74  sp = tc->readIntReg(INTREG_SPX);
75  // below should be enabled on condition that GICV3 is enabled
76  //tme_checkpoint->iccPmrEl1 = tc->readMiscReg(MISCREG_ICC_PMR_EL1);
77  nzcv = tc->readMiscReg(MISCREG_NZCV);
79  for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
80  x[n] = tc->readIntReg(n);
81  }
82  // TODO first detect if FP is enabled at this EL
83  for (auto n = 0; n < NumVecRegs; n++) {
84  RegId idx = RegId(VecRegClass, n);
85  z[n] = tc->readVecReg(idx);
86  }
87  for (auto n = 0; n < NumVecPredRegs; n++) {
88  RegId idx = RegId(VecPredRegClass, n);
89  p[n] = tc->readVecPredReg(idx);
90  }
91  fpcr = tc->readMiscReg(MISCREG_FPCR);
92  fpsr = tc->readMiscReg(MISCREG_FPSR);
93  pcstateckpt = tc->pcState();
94 
96 }
97 
98 void
100 {
101  tc->setIntReg(INTREG_SPX, sp);
102  // below should be enabled on condition that GICV3 is enabled
103  //tc->setMiscReg(MISCREG_ICC_PMR_EL1, tme_checkpoint->iccPmrEl1);
104  tc->setMiscReg(MISCREG_NZCV, nzcv);
106  for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
107  tc->setIntReg(n, x[n]);
108  }
109  // TODO first detect if FP is enabled at this EL
110  for (auto n = 0; n < NumVecRegs; n++) {
111  RegId idx = RegId(VecRegClass, n);
112  tc->setVecReg(idx, z[n]);
113  }
114  for (auto n = 0; n < NumVecPredRegs; n++) {
115  RegId idx = RegId(VecPredRegClass, n);
116  tc->setVecPredReg(idx, p[n]);
117  }
118  tc->setMiscReg(MISCREG_FPCR, fpcr);
119  tc->setMiscReg(MISCREG_FPSR, fpsr);
120 
121  // this code takes the generic HTM failure reason
122  // and prepares an Arm/TME-specific error code
123  // which is written to a destination register
124 
125  bool interrupt = false; // TODO get this from threadcontext
126  bool retry = false;
127  uint64_t error_code = 0;
128  switch (cause) {
130  replaceBits(error_code, 14, 0, tcreason);
131  replaceBits(error_code, 16, 1);
132  retry = bits(tcreason, 15);
133  break;
135  replaceBits(error_code, 17, 1);
136  retry = true;
137  break;
139  replaceBits(error_code, 18, 1);
140  break;
142  replaceBits(error_code, 19, 1);
143  break;
145  replaceBits(error_code, 20, 1);
146  break;
148  replaceBits(error_code, 21, 1);
149  break;
150  // case HtmFailureFaultCause_DEBUG:
151  // replaceBits(error_code, 22, 1);
152  // break;
153  default:
154  panic("Unknown HTM failure reason\n");
155  }
156  assert(!retry || !interrupt);
157  if (retry)
158  replaceBits(error_code, 15, 1);
159  if (interrupt)
160  replaceBits(error_code, 23, 1);
161  tc->setIntReg(rt, error_code);
162 
163  // set next PC
164  pcstateckpt.uReset();
165  pcstateckpt.advance();
166  tc->pcState(pcstateckpt);
167 
168  BaseHTMCheckpoint::restore(tc, cause);
169 }
170 
171 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ArmISA::HTMCheckpoint::iccPmrEl1
uint32_t iccPmrEl1
Definition: htm.hh:84
gem5::HtmFailureFaultCause::NEST
@ NEST
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmISA::HTMCheckpoint::nPc
Addr nPc
Definition: htm.hh:76
gem5::ThreadContext::readVecPredReg
virtual const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const =0
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::HtmFailureFaultCause::MEMORY
@ MEMORY
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition: misc.hh:619
gem5::ArmISA::HTMCheckpoint::sp
Addr sp
Definition: htm.hh:80
gem5::ArmISA::HTMCheckpoint::save
void save(ThreadContext *tc) override
Every ISA implementing HTM support should override the save method.
Definition: htm.cc:72
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition: misc.hh:620
gem5::ArmISA::daif
Bitfield< 9, 6 > daif
Definition: misc_types.hh:69
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::HtmFailureFaultCause::EXPLICIT
@ EXPLICIT
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::BaseHTMCheckpoint::restore
virtual void restore(ThreadContext *tc, HtmFailureFaultCause cause)
Every ISA implementing HTM support should override the restore method.
Definition: htm.hh:169
gem5::HtmFailureFaultCause::OTHER
@ OTHER
gem5::ArmISA::HTMCheckpoint::tcreason
uint16_t tcreason
Definition: htm.hh:81
gem5::HtmFailureFaultCause::EXCEPTION
@ EXCEPTION
htm.hh
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:81
gem5::ArmISA::z
Bitfield< 11 > z
Definition: misc_types.hh:374
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::rt
Bitfield< 15, 12 > rt
Definition: types.hh:115
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmISA::HTMCheckpoint::z
std::array< VecRegContainer, NumVecRegs > z
Definition: htm.hh:78
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::HTMCheckpoint::reset
void reset() override
Resets the checkpoint once a transaction has completed.
Definition: htm.cc:48
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ArmISA::HTMCheckpoint::fpsr
uint32_t fpsr
Definition: htm.hh:83
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ThreadContext::setVecPredReg
virtual void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val)=0
gem5::ArmISA::HTMCheckpoint::nzcv
uint8_t nzcv
Definition: htm.hh:85
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
gem5::HtmFailureFaultCause::SIZE
@ SIZE
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::ArmISA::HTMCheckpoint::rt
uint8_t rt
Definition: htm.hh:75
gem5::BaseHTMCheckpoint::reset
virtual void reset()
Resets the checkpoint once a transaction has completed.
Definition: htm.hh:213
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:455
misc.hh
gem5::ArmISA::HTMCheckpoint::x
std::array< RegVal, NUM_ARCH_INTREGS > x
Definition: htm.hh:77
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ArmISA::HTMCheckpoint::fpcr
uint32_t fpcr
Definition: htm.hh:82
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition: misc.hh:622
gem5::ArmISA::HTMCheckpoint::p
std::array< VecPredRegContainer, NumVecRegs > p
Definition: htm.hh:79
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition: misc.hh:621
gem5::ArmISA::sp
Bitfield< 0 > sp
Definition: misc_types.hh:74
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseHTMCheckpoint::save
virtual void save(ThreadContext *tc)
Every ISA implementing HTM support should override the save method.
Definition: htm.hh:154
gem5::ArmISA::HTMCheckpoint::pcstateckpt
PCState pcstateckpt
Definition: htm.hh:87
gem5::ArmISA::HTMCheckpoint::daif
uint8_t daif
Definition: htm.hh:86
gem5::ThreadContext::setVecReg
virtual void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)=0
int.hh
gem5::ArmISA::HTMCheckpoint::restore
void restore(ThreadContext *tc, HtmFailureFaultCause cause) override
Every ISA implementing HTM support should override the restore method.
Definition: htm.cc:99
thread_context.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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