gem5  v21.2.0.0
Namespaces | Typedefs | Variables
vec.hh File Reference
#include "arch/arm/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"

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Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::ArmISA
 

Typedefs

using gem5::ArmISA::VecElem = uint32_t
 
using gem5::ArmISA::VecRegContainer = gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)>
 
using gem5::ArmISA::VecPredReg = gem5::VecPredRegT< VecElem, NumVecElemPerVecReg, false, false >
 
using gem5::ArmISA::ConstVecPredReg = gem5::VecPredRegT< VecElem, NumVecElemPerVecReg, false, true >
 
using gem5::ArmISA::VecPredRegContainer = VecPredReg::Container
 

Variables

constexpr unsigned gem5::ArmISA::NumVecElemPerNeonVecReg = 4
 
constexpr unsigned gem5::ArmISA::NumVecElemPerVecReg = MaxSveVecLenInWords
 
const int gem5::ArmISA::NumFloatV7ArchRegs = 64
 
const int gem5::ArmISA::NumVecV7ArchRegs = 16
 
const int gem5::ArmISA::NumVecV8ArchRegs = 32
 
const int gem5::ArmISA::NumVecSpecialRegs = 8
 
const int gem5::ArmISA::NumVecIntrlvRegs = 4
 
const int gem5::ArmISA::NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs
 
const int gem5::ArmISA::NumVecPredRegs = 18
 
const int gem5::ArmISA::VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg
 
const int gem5::ArmISA::INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs
 
const int gem5::ArmISA::INTRLVREG1 = INTRLVREG0 + 1
 
const int gem5::ArmISA::INTRLVREG2 = INTRLVREG0 + 2
 
const int gem5::ArmISA::INTRLVREG3 = INTRLVREG0 + 3
 
const int gem5::ArmISA::VECREG_UREG0 = 32
 
const int gem5::ArmISA::PREDREG_FFR = 16
 
const int gem5::ArmISA::PREDREG_UREG0 = 17
 

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