gem5 v24.0.0.0
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int.hh File Reference
#include <cassert>
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"
#include "sim/core.hh"

Go to the source code of this file.

Classes

class  gem5::ArmISA::IntRegClassOps
 

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::ArmISA
 
namespace  gem5::ArmISA::int_reg
 

Typedefs

typedef const RegId gem5::ArmISA::int_reg::RegMap[NumArchRegs]
 

Functions

 gem5::ArmISA::BitUnion32 (PackedIntReg) Bitfield< 31
 
 gem5::ArmISA::EndBitUnion (PackedIntReg) namespace int_reg
 
static RegId gem5::ArmISA::int_reg::x (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::usr (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::hyp (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::svc (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::mon (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::abt (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::und (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::irq (unsigned index)
 
static const RegId & gem5::ArmISA::int_reg::fiq (unsigned index)
 
static int gem5::ArmISA::int_reg::regInMode (OperatingMode mode, int reg)
 
static const RegId & gem5::ArmISA::flattenIntRegModeIndex (int reg)
 
static RegIndex gem5::ArmISA::makeSP (RegIndex reg)
 
static bool gem5::ArmISA::couldBeSP (RegIndex reg)
 
static bool gem5::ArmISA::isSP (RegIndex reg)
 
static bool gem5::ArmISA::couldBeZero (RegIndex reg)
 
static bool gem5::ArmISA::isZero (RegIndex reg)
 
static RegIndex gem5::ArmISA::makeZero (RegIndex reg)
 

Variables

 gem5::ArmISA::uh1
 
Bitfield< 15, 0 > gem5::ArmISA::uh0
 
SignedBitfield< 31, 16 > gem5::ArmISA::sh1
 
SignedBitfield< 15, 0 > gem5::ArmISA::sh0
 
Bitfield< 31, 0 > gem5::ArmISA::uw
 
SignedBitfield< 31, 0 > gem5::ArmISA::sw
 
constexpr IntRegClassOps gem5::ArmISA::intRegClassOps
 
constexpr RegClass gem5::ArmISA::intRegClass
 
constexpr RegClass gem5::ArmISA::flatIntRegClass
 
constexpr RegId gem5::ArmISA::int_reg::R0 = intRegClass[_R0Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R1 = intRegClass[_R1Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R2 = intRegClass[_R2Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R3 = intRegClass[_R3Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R4 = intRegClass[_R4Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R5 = intRegClass[_R5Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R6 = intRegClass[_R6Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R7 = intRegClass[_R7Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R8 = intRegClass[_R8Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R9 = intRegClass[_R9Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R10 = intRegClass[_R10Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R11 = intRegClass[_R11Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R12 = intRegClass[_R12Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R13 = intRegClass[_R13Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R14 = intRegClass[_R14Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R15 = intRegClass[_R15Idx]
 
constexpr RegId gem5::ArmISA::int_reg::R13Svc = intRegClass[_R13SvcIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R14Svc = intRegClass[_R14SvcIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R13Mon = intRegClass[_R13MonIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R14Mon = intRegClass[_R14MonIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R13Hyp = intRegClass[_R13HypIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R13Abt = intRegClass[_R13AbtIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R14Abt = intRegClass[_R14AbtIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R13Und = intRegClass[_R13UndIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R14Und = intRegClass[_R14UndIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R13Irq = intRegClass[_R13IrqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R14Irq = intRegClass[_R14IrqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R8Fiq = intRegClass[_R8FiqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R9Fiq = intRegClass[_R9FiqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R10Fiq = intRegClass[_R10FiqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R11Fiq = intRegClass[_R11FiqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R12Fiq = intRegClass[_R12FiqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R13Fiq = intRegClass[_R13FiqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::R14Fiq = intRegClass[_R14FiqIdx]
 
constexpr RegId gem5::ArmISA::int_reg::Zero = intRegClass[_ZeroIdx]
 
constexpr RegId gem5::ArmISA::int_reg::Ureg0 = intRegClass[_Ureg0Idx]
 
constexpr RegId gem5::ArmISA::int_reg::Ureg1 = intRegClass[_Ureg1Idx]
 
constexpr RegId gem5::ArmISA::int_reg::Ureg2 = intRegClass[_Ureg2Idx]
 
constexpr RegId gem5::ArmISA::int_reg::Sp0 = intRegClass[_Sp0Idx]
 
constexpr RegId gem5::ArmISA::int_reg::Sp1 = intRegClass[_Sp1Idx]
 
constexpr RegId gem5::ArmISA::int_reg::Sp2 = intRegClass[_Sp2Idx]
 
constexpr RegId gem5::ArmISA::int_reg::Sp3 = intRegClass[_Sp3Idx]
 
constexpr RegId gem5::ArmISA::int_reg::Spx = intRegClass[_SpxIdx]
 
constexpr RegId gem5::ArmISA::int_reg::X0 = intRegClass[_X0Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X1 = intRegClass[_X1Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X2 = intRegClass[_X2Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X3 = intRegClass[_X3Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X4 = intRegClass[_X4Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X5 = intRegClass[_X5Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X6 = intRegClass[_X6Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X7 = intRegClass[_X7Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X8 = intRegClass[_X8Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X9 = intRegClass[_X9Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X10 = intRegClass[_X10Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X11 = intRegClass[_X11Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X12 = intRegClass[_X12Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X13 = intRegClass[_X13Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X14 = intRegClass[_X14Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X15 = intRegClass[_X15Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X16 = intRegClass[_X16Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X17 = intRegClass[_X17Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X18 = intRegClass[_X18Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X19 = intRegClass[_X19Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X20 = intRegClass[_X20Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X21 = intRegClass[_X21Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X22 = intRegClass[_X22Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X23 = intRegClass[_X23Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X24 = intRegClass[_X24Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X25 = intRegClass[_X25Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X26 = intRegClass[_X26Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X27 = intRegClass[_X27Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X28 = intRegClass[_X28Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X29 = intRegClass[_X29Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X30 = intRegClass[_X30Idx]
 
constexpr RegId gem5::ArmISA::int_reg::X31 = intRegClass[_X31Idx]
 
constexpr auto & gem5::ArmISA::int_reg::Sp = R13
 
constexpr auto & gem5::ArmISA::int_reg::Lr = R14
 
constexpr auto & gem5::ArmISA::int_reg::Pc = R15
 
constexpr auto & gem5::ArmISA::int_reg::SpSvc = R13Svc
 
constexpr auto & gem5::ArmISA::int_reg::LRSvc = R14Svc
 
constexpr auto & gem5::ArmISA::int_reg::SPMon = R13Mon
 
constexpr auto & gem5::ArmISA::int_reg::LRMon = R14Mon
 
constexpr auto & gem5::ArmISA::int_reg::SPHyp = R13Hyp
 
constexpr auto & gem5::ArmISA::int_reg::SPAbt = R13Abt
 
constexpr auto & gem5::ArmISA::int_reg::LRAbt = R14Abt
 
constexpr auto & gem5::ArmISA::int_reg::SPUnd = R13Und
 
constexpr auto & gem5::ArmISA::int_reg::LRUnd = R14Und
 
constexpr auto & gem5::ArmISA::int_reg::SPIrq = R13Irq
 
constexpr auto & gem5::ArmISA::int_reg::LRIrq = R14Irq
 
constexpr auto & gem5::ArmISA::int_reg::SPFiq = R13Fiq
 
constexpr auto & gem5::ArmISA::int_reg::LRFiq = R14Fiq
 
constexpr auto & gem5::ArmISA::int_reg::R0Usr = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Usr = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Usr = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Usr = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Usr = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Usr = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Usr = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Usr = R7
 
constexpr auto & gem5::ArmISA::int_reg::R8Usr = R8
 
constexpr auto & gem5::ArmISA::int_reg::R9Usr = R9
 
constexpr auto & gem5::ArmISA::int_reg::R10Usr = R10
 
constexpr auto & gem5::ArmISA::int_reg::R11Usr = R11
 
constexpr auto & gem5::ArmISA::int_reg::R12Usr = R12
 
constexpr auto & gem5::ArmISA::int_reg::R13Usr = R13
 
constexpr auto & gem5::ArmISA::int_reg::SPUsr = Sp
 
constexpr auto & gem5::ArmISA::int_reg::R14Usr = R14
 
constexpr auto & gem5::ArmISA::int_reg::LRUsr = Lr
 
constexpr auto & gem5::ArmISA::int_reg::R15Usr = R15
 
constexpr auto & gem5::ArmISA::int_reg::PcUsr = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R0Svc = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Svc = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Svc = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Svc = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Svc = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Svc = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Svc = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Svc = R7
 
constexpr auto & gem5::ArmISA::int_reg::R8Svc = R8
 
constexpr auto & gem5::ArmISA::int_reg::R9Svc = R9
 
constexpr auto & gem5::ArmISA::int_reg::R10Svc = R10
 
constexpr auto & gem5::ArmISA::int_reg::R11Svc = R11
 
constexpr auto & gem5::ArmISA::int_reg::R12Svc = R12
 
constexpr auto & gem5::ArmISA::int_reg::PcSvc = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R15Svc = R15
 
constexpr auto & gem5::ArmISA::int_reg::R0Mon = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Mon = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Mon = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Mon = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Mon = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Mon = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Mon = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Mon = R7
 
constexpr auto & gem5::ArmISA::int_reg::R8Mon = R8
 
constexpr auto & gem5::ArmISA::int_reg::R9Mon = R9
 
constexpr auto & gem5::ArmISA::int_reg::R10Mon = R10
 
constexpr auto & gem5::ArmISA::int_reg::R11Mon = R11
 
constexpr auto & gem5::ArmISA::int_reg::R12Mon = R12
 
constexpr auto & gem5::ArmISA::int_reg::PcMon = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R15Mon = R15
 
constexpr auto & gem5::ArmISA::int_reg::R0Abt = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Abt = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Abt = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Abt = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Abt = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Abt = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Abt = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Abt = R7
 
constexpr auto & gem5::ArmISA::int_reg::R8Abt = R8
 
constexpr auto & gem5::ArmISA::int_reg::R9Abt = R9
 
constexpr auto & gem5::ArmISA::int_reg::R10Abt = R10
 
constexpr auto & gem5::ArmISA::int_reg::R11Abt = R11
 
constexpr auto & gem5::ArmISA::int_reg::R12Abt = R12
 
constexpr auto & gem5::ArmISA::int_reg::PcAbt = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R15Abt = R15
 
constexpr auto & gem5::ArmISA::int_reg::R0Hyp = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Hyp = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Hyp = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Hyp = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Hyp = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Hyp = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Hyp = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Hyp = R7
 
constexpr auto & gem5::ArmISA::int_reg::R8Hyp = R8
 
constexpr auto & gem5::ArmISA::int_reg::R9Hyp = R9
 
constexpr auto & gem5::ArmISA::int_reg::R10Hyp = R10
 
constexpr auto & gem5::ArmISA::int_reg::R11Hyp = R11
 
constexpr auto & gem5::ArmISA::int_reg::R12Hyp = R12
 
constexpr auto & gem5::ArmISA::int_reg::LRHyp = Lr
 
constexpr auto & gem5::ArmISA::int_reg::R14Hyp = R14
 
constexpr auto & gem5::ArmISA::int_reg::PcHyp = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R15Hyp = R15
 
constexpr auto & gem5::ArmISA::int_reg::R0Und = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Und = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Und = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Und = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Und = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Und = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Und = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Und = R7
 
constexpr auto & gem5::ArmISA::int_reg::R8Und = R8
 
constexpr auto & gem5::ArmISA::int_reg::R9Und = R9
 
constexpr auto & gem5::ArmISA::int_reg::R10Und = R10
 
constexpr auto & gem5::ArmISA::int_reg::R11Und = R11
 
constexpr auto & gem5::ArmISA::int_reg::R12Und = R12
 
constexpr auto & gem5::ArmISA::int_reg::PcUnd = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R15Und = R15
 
constexpr auto & gem5::ArmISA::int_reg::R0Irq = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Irq = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Irq = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Irq = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Irq = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Irq = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Irq = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Irq = R7
 
constexpr auto & gem5::ArmISA::int_reg::R8Irq = R8
 
constexpr auto & gem5::ArmISA::int_reg::R9Irq = R9
 
constexpr auto & gem5::ArmISA::int_reg::R10Irq = R10
 
constexpr auto & gem5::ArmISA::int_reg::R11Irq = R11
 
constexpr auto & gem5::ArmISA::int_reg::R12Irq = R12
 
constexpr auto & gem5::ArmISA::int_reg::PcIrq = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R15Irq = R15
 
constexpr auto & gem5::ArmISA::int_reg::R0Fiq = R0
 
constexpr auto & gem5::ArmISA::int_reg::R1Fiq = R1
 
constexpr auto & gem5::ArmISA::int_reg::R2Fiq = R2
 
constexpr auto & gem5::ArmISA::int_reg::R3Fiq = R3
 
constexpr auto & gem5::ArmISA::int_reg::R4Fiq = R4
 
constexpr auto & gem5::ArmISA::int_reg::R5Fiq = R5
 
constexpr auto & gem5::ArmISA::int_reg::R6Fiq = R6
 
constexpr auto & gem5::ArmISA::int_reg::R7Fiq = R7
 
constexpr auto & gem5::ArmISA::int_reg::PcFiq = Pc
 
constexpr auto & gem5::ArmISA::int_reg::R15Fiq = R15
 
const RegMap gem5::ArmISA::int_reg::Reg64Map
 
const RegMap gem5::ArmISA::int_reg::RegUsrMap
 
const RegMap gem5::ArmISA::int_reg::RegHypMap
 
const RegMap gem5::ArmISA::int_reg::RegSvcMap
 
const RegMap gem5::ArmISA::int_reg::RegMonMap
 
const RegMap gem5::ArmISA::int_reg::RegAbtMap
 
const RegMap gem5::ArmISA::int_reg::RegUndMap
 
const RegMap gem5::ArmISA::int_reg::RegIrqMap
 
const RegMap gem5::ArmISA::int_reg::RegFiqMap
 
static const unsigned gem5::ArmISA::int_reg::regsPerMode = NumRegs
 
constexpr size_t gem5::ArmISA::NumArgumentRegs = 4
 
constexpr size_t gem5::ArmISA::NumArgumentRegs64 = 8
 
constexpr auto & gem5::ArmISA::ReturnValueReg = int_reg::X0
 
constexpr auto & gem5::ArmISA::ReturnValueReg1 = int_reg::X1
 
constexpr auto & gem5::ArmISA::ArgumentReg0 = int_reg::X0
 
constexpr auto & gem5::ArmISA::ArgumentReg1 = int_reg::X1
 
constexpr auto & gem5::ArmISA::ArgumentReg2 = int_reg::X2
 
constexpr auto & gem5::ArmISA::FramePointerReg = int_reg::X11
 
constexpr auto & gem5::ArmISA::StackPointerReg = int_reg::Sp
 
constexpr auto & gem5::ArmISA::ReturnAddressReg = int_reg::Lr
 
constexpr auto & gem5::ArmISA::SyscallNumReg = ReturnValueReg
 
constexpr auto & gem5::ArmISA::SyscallPseudoReturnReg = ReturnValueReg
 
constexpr auto & gem5::ArmISA::SyscallSuccessReg = ReturnValueReg
 
Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0