gem5  v21.2.0.0
Classes | Namespaces | Typedefs | Enumerations
faults.hh File Reference
#include "arch/mips/pra_constants.hh"
#include "arch/mips/regs/misc.hh"
#include "cpu/null_static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"

Go to the source code of this file.

Classes

class  gem5::MipsISA::MipsFaultBase
 
struct  gem5::MipsISA::MipsFaultBase::FaultVals
 
class  gem5::MipsISA::MipsFault< T >
 
class  gem5::MipsISA::SystemCallFault
 
class  gem5::MipsISA::ReservedInstructionFault
 
class  gem5::MipsISA::ThreadFault
 
class  gem5::MipsISA::IntegerOverflowFault
 
class  gem5::MipsISA::TrapFault
 
class  gem5::MipsISA::BreakpointFault
 
class  gem5::MipsISA::DspStateDisabledFault
 
class  gem5::MipsISA::MachineCheckFault
 
class  gem5::MipsISA::ResetFault
 
class  gem5::MipsISA::SoftResetFault
 
class  gem5::MipsISA::NonMaskableInterrupt
 
class  gem5::MipsISA::CoprocessorUnusableFault
 
class  gem5::MipsISA::InterruptFault
 
class  gem5::MipsISA::AddressFault< T >
 
class  gem5::MipsISA::AddressErrorFault
 
class  gem5::MipsISA::TlbFault< T >
 
class  gem5::MipsISA::TlbRefillFault
 
class  gem5::MipsISA::TlbInvalidFault
 
class  gem5::MipsISA::TlbModifiedFault
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::MipsISA
 

Typedefs

typedef Addr gem5::MipsISA::FaultVect
 

Enumerations

enum  gem5::MipsISA::ExcCode {
  gem5::MipsISA::ExcCodeDummy = 0, gem5::MipsISA::ExcCodeInt = 0, gem5::MipsISA::ExcCodeMod = 1, gem5::MipsISA::ExcCodeTlbL = 2,
  gem5::MipsISA::ExcCodeTlbS = 3, gem5::MipsISA::ExcCodeAdEL = 4, gem5::MipsISA::ExcCodeAdES = 5, gem5::MipsISA::ExcCodeIBE = 6,
  gem5::MipsISA::ExcCodeDBE = 7, gem5::MipsISA::ExcCodeSys = 8, gem5::MipsISA::ExcCodeBp = 9, gem5::MipsISA::ExcCodeRI = 10,
  gem5::MipsISA::ExcCodeCpU = 11, gem5::MipsISA::ExcCodeOv = 12, gem5::MipsISA::ExcCodeTr = 13, gem5::MipsISA::ExcCodeC2E = 18,
  gem5::MipsISA::ExcCodeMDMX = 22, gem5::MipsISA::ExcCodeWatch = 23, gem5::MipsISA::ExcCodeMCheck = 24, gem5::MipsISA::ExcCodeThread = 25,
  gem5::MipsISA::ExcCodeCacheErr = 30
}
 

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