gem5  v21.1.0.2
misc.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __ARCH_MIPS_REGS_MISC_HH__
31 #define __ARCH_MIPS_REGS_MISC_HH__
32 
33 namespace gem5
34 {
35 
36 namespace MipsISA
37 {
38 
39 // Enumerate names for 'Control' Registers in the CPU
40 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
41 // (Register Number-Register Select) Summary of Register
42 //------------------------------------------------------
43 // The first set of names classify the CP0 names as Register Banks
44 // for easy indexing when using the 'RD + SEL' index combination
45 // in CP0 instructions.
47 {
48  MISCREG_INDEX = 0, //Bank 0: 0 - 3
52 
53  MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
61 
62  MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
70 
71  MISCREG_ENTRYLO1 = 24, // Bank 3: 24
72 
73  MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
75 
76  MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
78 
79  MISCREG_WIRED = 48, //Bank 6:48-55
85 
86  MISCREG_HWRENA = 56, //Bank 7: 56-63
87 
88  MISCREG_BADVADDR = 64, //Bank 8: 64-71
89 
90  MISCREG_COUNT = 72, //Bank 9: 72-79
91 
92  MISCREG_ENTRYHI = 80, //Bank 10: 80-87
93 
94  MISCREG_COMPARE = 88, //Bank 11: 88-95
95 
96  MISCREG_STATUS = 96, //Bank 12: 96-103
100 
101  MISCREG_CAUSE = 104, //Bank 13: 104-111
102 
103  MISCREG_EPC = 112, //Bank 14: 112-119
104 
105  MISCREG_PRID = 120, //Bank 15: 120-127,
107 
108  MISCREG_CONFIG = 128, //Bank 16: 128-135
116 
117 
118  MISCREG_LLADDR = 136, //Bank 17: 136-143
119 
120  MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
128 
129  MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
137 
138  MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
139 
140  //Bank 21: 168-175
141 
142  //Bank 22: 176-183
143 
144  MISCREG_DEBUG = 184, //Bank 23: 184-191
149 
150  MISCREG_DEPC = 192, //Bank 24: 192-199
151 
152  MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
160 
161  MISCREG_ERRCTL = 208, //Bank 26: 208-215
162 
163  MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
167 
168  MISCREG_TAGLO0 = 224, //Bank 28: 224-231
176 
177  MISCREG_TAGHI0 = 232, //Bank 29: 232-239
185 
186 
187  MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
188 
189  MISCREG_DESAVE = 248, //Bank 31: 248-256
190 
193 
195 };
196 
197 } // namespace MipsISA
198 } // namespace gem5
199 
200 #endif
gem5::MipsISA::MISCREG_DATALO7
@ MISCREG_DATALO7
Definition: misc.hh:175
gem5::MipsISA::MISCREG_ENTRYLO0
@ MISCREG_ENTRYLO0
Definition: misc.hh:62
gem5::MipsISA::MISCREG_COUNT
@ MISCREG_COUNT
Definition: misc.hh:90
gem5::MipsISA::MISCREG_TAGLO6
@ MISCREG_TAGLO6
Definition: misc.hh:174
gem5::MipsISA::MISCREG_CONFIG5
@ MISCREG_CONFIG5
Definition: misc.hh:113
gem5::MipsISA::MISCREG_DATALO5
@ MISCREG_DATALO5
Definition: misc.hh:173
gem5::MipsISA::MISCREG_TP_VALUE
@ MISCREG_TP_VALUE
Definition: misc.hh:192
gem5::MipsISA::MISCREG_DATAHI3
@ MISCREG_DATAHI3
Definition: misc.hh:180
gem5::MipsISA::MISCREG_CONFIG3
@ MISCREG_CONFIG3
Definition: misc.hh:111
gem5::MipsISA::MISCREG_MVP_CONTROL
@ MISCREG_MVP_CONTROL
Definition: misc.hh:49
gem5::MipsISA::MISCREG_WATCHHI2
@ MISCREG_WATCHHI2
Definition: misc.hh:131
gem5::MipsISA::MISCREG_WIRED
@ MISCREG_WIRED
Definition: misc.hh:79
gem5::MipsISA::MISCREG_PRID
@ MISCREG_PRID
Definition: misc.hh:105
gem5::MipsISA::MISCREG_TAGLO0
@ MISCREG_TAGLO0
Definition: misc.hh:168
gem5::MipsISA::MISCREG_CACHEERR1
@ MISCREG_CACHEERR1
Definition: misc.hh:164
gem5::MipsISA::MISCREG_WATCHHI6
@ MISCREG_WATCHHI6
Definition: misc.hh:135
gem5::MipsISA::MISCREG_SRS_CONF1
@ MISCREG_SRS_CONF1
Definition: misc.hh:81
gem5::MipsISA::MISCREG_PERFCNT5
@ MISCREG_PERFCNT5
Definition: misc.hh:157
gem5::MipsISA::MISCREG_ERROR_EPC
@ MISCREG_ERROR_EPC
Definition: misc.hh:187
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::MISCREG_WATCHLO3
@ MISCREG_WATCHLO3
Definition: misc.hh:123
gem5::MipsISA::MISCREG_WATCHHI3
@ MISCREG_WATCHHI3
Definition: misc.hh:132
gem5::MipsISA::MISCREG_TAGHI0
@ MISCREG_TAGHI0
Definition: misc.hh:177
gem5::MipsISA::MISCREG_ENTRYHI
@ MISCREG_ENTRYHI
Definition: misc.hh:92
gem5::MipsISA::MISCREG_WATCHHI1
@ MISCREG_WATCHHI1
Definition: misc.hh:130
gem5::MipsISA::MISCREG_EBASE
@ MISCREG_EBASE
Definition: misc.hh:106
gem5::MipsISA::MISCREG_CONTEXT_CONFIG
@ MISCREG_CONTEXT_CONFIG
Definition: misc.hh:74
gem5::MipsISA::MISCREG_SRSMAP
@ MISCREG_SRSMAP
Definition: misc.hh:99
gem5::MipsISA::MISCREG_PERFCNT3
@ MISCREG_PERFCNT3
Definition: misc.hh:155
gem5::MipsISA::MISCREG_YQMASK
@ MISCREG_YQMASK
Definition: misc.hh:57
gem5::MipsISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:46
gem5::MipsISA::MISCREG_TC_BIND
@ MISCREG_TC_BIND
Definition: misc.hh:64
gem5::MipsISA::MISCREG_CONFIG2
@ MISCREG_CONFIG2
Definition: misc.hh:110
gem5::MipsISA::MISCREG_VPE_CONF1
@ MISCREG_VPE_CONF1
Definition: misc.hh:56
gem5::MipsISA::MISCREG_PERFCNT7
@ MISCREG_PERFCNT7
Definition: misc.hh:159
gem5::MipsISA::MISCREG_WATCHHI0
@ MISCREG_WATCHHI0
Definition: misc.hh:129
gem5::MipsISA::MISCREG_CONFIG7
@ MISCREG_CONFIG7
Definition: misc.hh:115
gem5::MipsISA::MISCREG_PERFCNT6
@ MISCREG_PERFCNT6
Definition: misc.hh:158
gem5::MipsISA::MISCREG_SRSCTL
@ MISCREG_SRSCTL
Definition: misc.hh:98
gem5::MipsISA::MISCREG_DESAVE
@ MISCREG_DESAVE
Definition: misc.hh:189
gem5::MipsISA::MISCREG_NUMREGS
@ MISCREG_NUMREGS
Definition: misc.hh:194
gem5::MipsISA::MISCREG_PERFCNT4
@ MISCREG_PERFCNT4
Definition: misc.hh:156
gem5::MipsISA::MISCREG_WATCHLO2
@ MISCREG_WATCHLO2
Definition: misc.hh:122
gem5::MipsISA::MISCREG_WATCHLO0
@ MISCREG_WATCHLO0
Definition: misc.hh:120
gem5::MipsISA::MISCREG_SRS_CONF2
@ MISCREG_SRS_CONF2
Definition: misc.hh:82
gem5::MipsISA::MISCREG_CP0_RANDOM
@ MISCREG_CP0_RANDOM
Definition: misc.hh:53
gem5::MipsISA::MISCREG_INTCTL
@ MISCREG_INTCTL
Definition: misc.hh:97
gem5::MipsISA::MISCREG_DEPC
@ MISCREG_DEPC
Definition: misc.hh:150
gem5::MipsISA::MISCREG_WATCHLO1
@ MISCREG_WATCHLO1
Definition: misc.hh:121
gem5::MipsISA::MISCREG_INDEX
@ MISCREG_INDEX
Definition: misc.hh:48
gem5::MipsISA::MISCREG_PERFCNT2
@ MISCREG_PERFCNT2
Definition: misc.hh:154
gem5::MipsISA::MISCREG_CONFIG4
@ MISCREG_CONFIG4
Definition: misc.hh:112
gem5::MipsISA::MISCREG_TC_CONTEXT
@ MISCREG_TC_CONTEXT
Definition: misc.hh:67
gem5::MipsISA::MISCREG_TAGLO2
@ MISCREG_TAGLO2
Definition: misc.hh:170
gem5::MipsISA::MISCREG_SRS_CONF4
@ MISCREG_SRS_CONF4
Definition: misc.hh:84
gem5::MipsISA::MISCREG_WATCHLO5
@ MISCREG_WATCHLO5
Definition: misc.hh:125
gem5::MipsISA::MISCREG_DATAHI7
@ MISCREG_DATAHI7
Definition: misc.hh:184
gem5::MipsISA::MISCREG_TAGLO4
@ MISCREG_TAGLO4
Definition: misc.hh:172
gem5::MipsISA::MISCREG_VPE_SCHEFBACK
@ MISCREG_VPE_SCHEFBACK
Definition: misc.hh:59
gem5::MipsISA::MISCREG_TC_STATUS
@ MISCREG_TC_STATUS
Definition: misc.hh:63
gem5::MipsISA::MISCREG_TAGHI4
@ MISCREG_TAGHI4
Definition: misc.hh:181
gem5::MipsISA::MISCREG_WATCHLO6
@ MISCREG_WATCHLO6
Definition: misc.hh:126
gem5::MipsISA::MISCREG_TC_HALT
@ MISCREG_TC_HALT
Definition: misc.hh:66
gem5::MipsISA::MISCREG_BADVADDR
@ MISCREG_BADVADDR
Definition: misc.hh:88
gem5::MipsISA::MISCREG_CONFIG
@ MISCREG_CONFIG
Definition: misc.hh:108
gem5::MipsISA::MISCREG_CONFIG1
@ MISCREG_CONFIG1
Definition: misc.hh:109
gem5::MipsISA::MISCREG_LLFLAG
@ MISCREG_LLFLAG
Definition: misc.hh:191
gem5::MipsISA::MISCREG_ERRCTL
@ MISCREG_ERRCTL
Definition: misc.hh:161
gem5::MipsISA::MISCREG_TC_SCHEDULE
@ MISCREG_TC_SCHEDULE
Definition: misc.hh:68
gem5::MipsISA::MISCREG_PERFCNT1
@ MISCREG_PERFCNT1
Definition: misc.hh:153
gem5::MipsISA::MISCREG_WATCHHI5
@ MISCREG_WATCHHI5
Definition: misc.hh:134
gem5::MipsISA::MISCREG_CACHEERR2
@ MISCREG_CACHEERR2
Definition: misc.hh:165
gem5::MipsISA::MISCREG_WATCHHI4
@ MISCREG_WATCHHI4
Definition: misc.hh:133
gem5::MipsISA::MISCREG_PAGEMASK
@ MISCREG_PAGEMASK
Definition: misc.hh:76
gem5::MipsISA::MISCREG_VPE_CONTROL
@ MISCREG_VPE_CONTROL
Definition: misc.hh:54
gem5::MipsISA::MISCREG_TAGHI2
@ MISCREG_TAGHI2
Definition: misc.hh:179
gem5::MipsISA::MISCREG_MVP_CONF1
@ MISCREG_MVP_CONF1
Definition: misc.hh:51
gem5::MipsISA::MISCREG_DATAHI5
@ MISCREG_DATAHI5
Definition: misc.hh:182
gem5::MipsISA::MISCREG_EPC
@ MISCREG_EPC
Definition: misc.hh:103
gem5::MipsISA::MISCREG_XCCONTEXT64
@ MISCREG_XCCONTEXT64
Definition: misc.hh:138
gem5::MipsISA::MISCREG_VPE_SCHEDULE
@ MISCREG_VPE_SCHEDULE
Definition: misc.hh:58
gem5::MipsISA::MISCREG_DATALO1
@ MISCREG_DATALO1
Definition: misc.hh:169
gem5::MipsISA::MISCREG_WATCHHI7
@ MISCREG_WATCHHI7
Definition: misc.hh:136
gem5::MipsISA::MISCREG_HWRENA
@ MISCREG_HWRENA
Definition: misc.hh:86
gem5::MipsISA::MISCREG_TAGHI6
@ MISCREG_TAGHI6
Definition: misc.hh:183
gem5::MipsISA::MISCREG_DATALO3
@ MISCREG_DATALO3
Definition: misc.hh:171
gem5::MipsISA::MISCREG_MVP_CONF0
@ MISCREG_MVP_CONF0
Definition: misc.hh:50
gem5::MipsISA::MISCREG_USER_TRACE_DATA
@ MISCREG_USER_TRACE_DATA
Definition: misc.hh:147
gem5::MipsISA::MISCREG_VPE_CONF0
@ MISCREG_VPE_CONF0
Definition: misc.hh:55
gem5::MipsISA::MISCREG_TRACE_CONTROL2
@ MISCREG_TRACE_CONTROL2
Definition: misc.hh:146
gem5::MipsISA::MISCREG_TC_SCHEFBACK
@ MISCREG_TC_SCHEFBACK
Definition: misc.hh:69
gem5::MipsISA::MISCREG_WATCHLO7
@ MISCREG_WATCHLO7
Definition: misc.hh:127
gem5::MipsISA::MISCREG_TC_RESTART
@ MISCREG_TC_RESTART
Definition: misc.hh:65
gem5::MipsISA::MISCREG_DEBUG
@ MISCREG_DEBUG
Definition: misc.hh:144
gem5::MipsISA::MISCREG_LLADDR
@ MISCREG_LLADDR
Definition: misc.hh:118
gem5::MipsISA::MISCREG_COMPARE
@ MISCREG_COMPARE
Definition: misc.hh:94
gem5::MipsISA::MISCREG_ENTRYLO1
@ MISCREG_ENTRYLO1
Definition: misc.hh:71
gem5::MipsISA::MISCREG_TRACE_CONTROL1
@ MISCREG_TRACE_CONTROL1
Definition: misc.hh:145
gem5::MipsISA::MISCREG_SRS_CONF3
@ MISCREG_SRS_CONF3
Definition: misc.hh:83
gem5::MipsISA::MISCREG_CAUSE
@ MISCREG_CAUSE
Definition: misc.hh:101
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MipsISA::MISCREG_PAGEGRAIN
@ MISCREG_PAGEGRAIN
Definition: misc.hh:77
gem5::MipsISA::MISCREG_DATAHI1
@ MISCREG_DATAHI1
Definition: misc.hh:178
gem5::MipsISA::MISCREG_WATCHLO4
@ MISCREG_WATCHLO4
Definition: misc.hh:124
gem5::MipsISA::MISCREG_CONTEXT
@ MISCREG_CONTEXT
Definition: misc.hh:73
gem5::MipsISA::MISCREG_CACHEERR3
@ MISCREG_CACHEERR3
Definition: misc.hh:166
gem5::MipsISA::MISCREG_TRACE_BPC
@ MISCREG_TRACE_BPC
Definition: misc.hh:148
gem5::MipsISA::MISCREG_CACHEERR0
@ MISCREG_CACHEERR0
Definition: misc.hh:163
gem5::MipsISA::MISCREG_VPE_OPT
@ MISCREG_VPE_OPT
Definition: misc.hh:60
gem5::MipsISA::MISCREG_CONFIG6
@ MISCREG_CONFIG6
Definition: misc.hh:114
gem5::MipsISA::MISCREG_SRS_CONF0
@ MISCREG_SRS_CONF0
Definition: misc.hh:80
gem5::MipsISA::MISCREG_PERFCNT0
@ MISCREG_PERFCNT0
Definition: misc.hh:152

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