gem5  v22.0.0.1
faults.hh
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1 /*
2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __MIPS_FAULTS_HH__
31 #define __MIPS_FAULTS_HH__
32 
34 #include "arch/mips/regs/misc.hh"
35 #include "cpu/null_static_inst.hh"
36 #include "cpu/thread_context.hh"
37 #include "debug/MipsPRA.hh"
38 #include "sim/faults.hh"
39 #include "sim/full_system.hh"
40 
41 namespace gem5
42 {
43 
44 namespace MipsISA
45 {
46 
47 typedef Addr FaultVect;
48 
49 enum ExcCode
50 {
51  // A dummy value to use when the code isn't defined or doesn't matter.
53 
63  ExcCodeBp = 9,
64  ExcCodeRI = 10,
65  ExcCodeCpU = 11,
66  ExcCodeOv = 12,
67  ExcCodeTr = 13,
68  ExcCodeC2E = 18,
74 };
75 
76 class MipsFaultBase : public FaultBase
77 {
78  public:
79  struct FaultVals
80  {
81  const FaultName name;
83  const ExcCode code;
84  };
85 
86  void setExceptionState(ThreadContext *, uint8_t);
87 
88  virtual FaultVect offset(ThreadContext *tc) const = 0;
89  virtual ExcCode code() const = 0;
90  virtual FaultVect base(ThreadContext *tc) const
91  {
92  StatusReg status = tc->readMiscReg(MISCREG_STATUS);
93  if (!status.bev)
94  return tc->readMiscReg(MISCREG_EBASE);
95  else
96  return 0xbfc00200;
97  }
98 
99  FaultVect
100  vect(ThreadContext *tc) const
101  {
102  return base(tc) + offset(tc);
103  }
104 
105  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
107 };
108 
109 template <typename T>
110 class MipsFault : public MipsFaultBase
111 {
112  protected:
113  static FaultVals vals;
114  public:
115  FaultName name() const { return vals.name; }
116  FaultVect offset(ThreadContext *tc) const { return vals.offset; }
117  ExcCode code() const { return vals.code; }
118 };
119 
120 class SystemCallFault : public MipsFault<SystemCallFault> {};
121 class ReservedInstructionFault : public MipsFault<ReservedInstructionFault> {};
122 class ThreadFault : public MipsFault<ThreadFault> {};
123 class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {};
124 class TrapFault : public MipsFault<TrapFault> {};
125 class BreakpointFault : public MipsFault<BreakpointFault> {};
126 class DspStateDisabledFault : public MipsFault<DspStateDisabledFault> {};
127 
128 class MachineCheckFault : public MipsFault<MachineCheckFault>
129 {
130  public:
131  bool isMachineCheckFault() { return true; }
132 };
133 
134 class ResetFault : public MipsFault<ResetFault>
135 {
136  public:
137  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
139 
140 };
141 
142 class SoftResetFault : public MipsFault<SoftResetFault>
143 {
144  public:
145  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
147 };
148 
149 class NonMaskableInterrupt : public MipsFault<NonMaskableInterrupt>
150 {
151  public:
152  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
154 };
155 
156 class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
157 {
158  protected:
159  int coProcID;
160  public:
161  CoprocessorUnusableFault(int _procid) : coProcID(_procid)
162  {}
163 
164  void
165  invoke(ThreadContext * tc, const StaticInstPtr &inst =
167  {
169  if (FullSystem) {
170  CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
171  cause.ce = coProcID;
172  tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
173  }
174  }
175 };
176 
177 class InterruptFault : public MipsFault<InterruptFault>
178 {
179  public:
180  FaultVect
182  {
183  CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
184  // offset 0x200 for release 2, 0x180 for release 1.
185  return cause.iv ? 0x200 : 0x180;
186  }
187 };
188 
189 template <typename T>
190 class AddressFault : public MipsFault<T>
191 {
192  protected:
194  bool store;
195 
196  AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
197  {}
198 
199  void
200  invoke(ThreadContext * tc, const StaticInstPtr &inst =
202  {
203  MipsFault<T>::invoke(tc, inst);
204  if (FullSystem)
206  }
207 };
208 
209 class AddressErrorFault : public AddressFault<AddressErrorFault>
210 {
211  public:
212  AddressErrorFault(Addr _vaddr, bool _store) :
213  AddressFault<AddressErrorFault>(_vaddr, _store)
214  {}
215 
216  ExcCode
217  code() const
218  {
219  return store ? ExcCodeAdES : ExcCodeAdEL;
220  }
221 
222 };
223 
224 template <typename T>
225 class TlbFault : public AddressFault<T>
226 {
227  protected:
230 
231  TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store) :
232  AddressFault<T>(_vaddr, _store), asid(_asid), vpn(_vpn)
233  {}
234 
235  void
237  {
238  this->setExceptionState(tc, excCode);
239 
241  EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
242  entryHi.asid = this->asid;
243  entryHi.vpn2 = this->vpn >> 2;
244  entryHi.vpn2x = this->vpn & 0x3;
245  tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
246 
247  ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
248  context.badVPN2 = this->vpn >> 2;
249  tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
250  }
251 
252  void
253  invoke(ThreadContext * tc, const StaticInstPtr &inst =
255  {
256  if (FullSystem) {
257  DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
258  Addr vect = this->vect(tc);
259  setTlbExceptionState(tc, this->code());
260  tc->pcState(vect);
261  } else {
262  AddressFault<T>::invoke(tc, inst);
263  }
264  }
265 
266  ExcCode
267  code() const
268  {
269  return this->store ? ExcCodeTlbS : ExcCodeTlbL;
270  }
271 };
272 
273 class TlbRefillFault : public TlbFault<TlbRefillFault>
274 {
275  public:
278  {}
279 
280  FaultVect
282  {
283  StatusReg status = tc->readMiscReg(MISCREG_STATUS);
284  return status.exl ? 0x180 : 0x000;
285  }
286 };
287 
288 class TlbInvalidFault : public TlbFault<TlbInvalidFault>
289 {
290  public:
293  {}
294 };
295 
296 class TlbModifiedFault : public TlbFault<TlbModifiedFault>
297 {
298  public:
301  {}
302 
304 };
305 
306 /*
307  * Explicitly declare template static member variables to avoid warnings
308  * in some clang versions
309  */
327 
328 
329 
330 } // namespace MipsISA
331 } // namespace gem5
332 
333 #endif // __MIPS_FAULTS_HH__
gem5::MipsISA::BreakpointFault
Definition: faults.hh:125
gem5::MipsISA::AddressFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.hh:200
gem5::MipsISA::ExcCodeCacheErr
@ ExcCodeCacheErr
Definition: faults.hh:73
misc.hh
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::MipsISA::AddressErrorFault
Definition: faults.hh:209
gem5::MipsISA::CoprocessorUnusableFault
Definition: faults.hh:156
gem5::MipsISA::ResetFault
Definition: faults.hh:134
gem5::MipsISA::MipsFault::code
ExcCode code() const
Definition: faults.hh:117
gem5::MipsISA::TlbFault::asid
Addr asid
Definition: faults.hh:228
gem5::MipsISA::ExcCodeThread
@ ExcCodeThread
Definition: faults.hh:72
gem5::MipsISA::TlbFault::vpn
Addr vpn
Definition: faults.hh:229
gem5::MipsISA::ExcCodeMod
@ ExcCodeMod
Definition: faults.hh:55
gem5::MipsISA::TlbModifiedFault
Definition: faults.hh:296
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::MipsFaultBase::vect
FaultVect vect(ThreadContext *tc) const
Definition: faults.hh:100
gem5::MipsISA::MISCREG_ENTRYHI
@ MISCREG_ENTRYHI
Definition: misc.hh:92
gem5::MipsISA::excCode
Bitfield< 6, 2 > excCode
Definition: pra_constants.hh:199
gem5::MipsISA::MISCREG_EBASE
@ MISCREG_EBASE
Definition: misc.hh:106
gem5::MipsISA::IntegerOverflowFault
Definition: faults.hh:123
gem5::MipsISA::MipsFaultBase::FaultVals::code
const ExcCode code
Definition: faults.hh:83
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
pra_constants.hh
gem5::MipsISA::ExcCodeDummy
@ ExcCodeDummy
Definition: faults.hh:52
gem5::MipsISA::TlbFault::code
ExcCode code() const
Definition: faults.hh:267
gem5::MipsISA::TlbInvalidFault::TlbInvalidFault
TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store)
Definition: faults.hh:291
gem5::MipsISA::MipsFaultBase
Definition: faults.hh:76
gem5::MipsISA::MachineCheckFault::isMachineCheckFault
bool isMachineCheckFault()
Definition: faults.hh:131
gem5::MipsISA::ExcCodeTr
@ ExcCodeTr
Definition: faults.hh:67
gem5::MipsISA::ExcCode
ExcCode
Definition: faults.hh:49
gem5::MipsISA::MipsFaultBase::FaultVals::name
const FaultName name
Definition: faults.hh:81
gem5::MipsISA::ReservedInstructionFault
Definition: faults.hh:121
faults.hh
gem5::MipsISA::AddressErrorFault::AddressErrorFault
AddressErrorFault(Addr _vaddr, bool _store)
Definition: faults.hh:212
gem5::MipsISA::ExcCodeTlbL
@ ExcCodeTlbL
Definition: faults.hh:56
gem5::MipsISA::TlbRefillFault::offset
FaultVect offset(ThreadContext *tc) const
Definition: faults.hh:281
gem5::MipsISA::AddressFault::store
bool store
Definition: faults.hh:194
gem5::MipsISA::MipsFault
Definition: faults.hh:110
gem5::RefCountingPtr< StaticInst >
gem5::MipsISA::ExcCodeOv
@ ExcCodeOv
Definition: faults.hh:66
gem5::MipsISA::ExcCodeBp
@ ExcCodeBp
Definition: faults.hh:63
gem5::MipsISA::MipsFaultBase::code
virtual ExcCode code() const =0
gem5::MipsISA::MachineCheckFault
Definition: faults.hh:128
gem5::MipsISA::ExcCodeCpU
@ ExcCodeCpU
Definition: faults.hh:65
gem5::MipsISA::ExcCodeRI
@ ExcCodeRI
Definition: faults.hh:64
gem5::MipsISA::InterruptFault::offset
FaultVect offset(ThreadContext *tc) const
Definition: faults.hh:181
gem5::MipsISA::CoprocessorUnusableFault::CoprocessorUnusableFault
CoprocessorUnusableFault(int _procid)
Definition: faults.hh:161
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::MipsISA::MipsFaultBase::FaultVals
Definition: faults.hh:79
gem5::MipsISA::MipsFaultBase::offset
virtual FaultVect offset(ThreadContext *tc) const =0
gem5::MipsISA::MipsFaultBase::setExceptionState
void setExceptionState(ThreadContext *, uint8_t)
Definition: faults.cc:100
gem5::MipsISA::TlbRefillFault::TlbRefillFault
TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store)
Definition: faults.hh:276
gem5::MipsISA::TlbFault::TlbFault
TlbFault(Addr _asid, Addr _vaddr, Addr _vpn, bool _store)
Definition: faults.hh:231
gem5::MipsISA::AddressFault
Definition: faults.hh:190
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::MipsISA::ExcCodeAdES
@ ExcCodeAdES
Definition: faults.hh:59
gem5::MipsISA::SystemCallFault
Definition: faults.hh:120
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::MipsISA::AddressErrorFault::code
ExcCode code() const
Definition: faults.hh:217
gem5::MipsISA::ThreadFault
Definition: faults.hh:122
gem5::MipsISA::MipsFault::vals
static FaultVals vals
Definition: faults.hh:113
gem5::MipsISA::DspStateDisabledFault
Definition: faults.hh:126
gem5::MipsISA::MISCREG_BADVADDR
@ MISCREG_BADVADDR
Definition: misc.hh:88
gem5::MipsISA::TrapFault
Definition: faults.hh:124
gem5::MipsISA::ExcCodeWatch
@ ExcCodeWatch
Definition: faults.hh:70
gem5::MipsISA::SoftResetFault
Definition: faults.hh:142
gem5::MipsISA::CoprocessorUnusableFault::coProcID
int coProcID
Definition: faults.hh:159
gem5::MipsISA::AddressFault::vaddr
Addr vaddr
Definition: faults.hh:193
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::MipsISA::CoprocessorUnusableFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.hh:165
gem5::MipsISA::AddressFault::AddressFault
AddressFault(Addr _vaddr, bool _store)
Definition: faults.hh:196
null_static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::MipsISA::ExcCodeIBE
@ ExcCodeIBE
Definition: faults.hh:60
gem5::MipsISA::MipsFaultBase::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:132
full_system.hh
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::MipsISA::TlbFault
Definition: faults.hh:225
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::MipsISA::ExcCodeInt
@ ExcCodeInt
Definition: faults.hh:54
gem5::MipsISA::ExcCodeDBE
@ ExcCodeDBE
Definition: faults.hh:61
gem5::MipsISA::ExcCodeMCheck
@ ExcCodeMCheck
Definition: faults.hh:71
gem5::MipsISA::TlbModifiedFault::TlbModifiedFault
TlbModifiedFault(Addr asid, Addr vaddr, Addr vpn)
Definition: faults.hh:299
gem5::MipsISA::TlbRefillFault
Definition: faults.hh:273
gem5::MipsISA::ExcCodeAdEL
@ ExcCodeAdEL
Definition: faults.hh:58
gem5::FaultBase
Definition: translation_gen.test.cc:49
gem5::MipsISA::MipsFault::offset
FaultVect offset(ThreadContext *tc) const
Definition: faults.hh:116
gem5::MipsISA::ExcCodeSys
@ ExcCodeSys
Definition: faults.hh:62
gem5::MipsISA::MipsFaultBase::base
virtual FaultVect base(ThreadContext *tc) const
Definition: faults.hh:90
gem5::MipsISA::TlbFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.hh:253
gem5::MipsISA::NonMaskableInterrupt
Definition: faults.hh:149
gem5::MipsISA::TlbFault::setTlbExceptionState
void setTlbExceptionState(ThreadContext *tc, uint8_t excCode)
Definition: faults.hh:236
gem5::MipsISA::TlbModifiedFault::code
ExcCode code() const
Definition: faults.hh:303
gem5::MipsISA::ExcCodeC2E
@ ExcCodeC2E
Definition: faults.hh:68
gem5::MipsISA::ResetFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:144
gem5::MipsISA::MISCREG_CAUSE
@ MISCREG_CAUSE
Definition: misc.hh:101
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::InterruptFault
Definition: faults.hh:177
gem5::MipsISA::FaultVect
Addr FaultVect
Definition: faults.hh:47
gem5::MipsISA::ExcCodeMDMX
@ ExcCodeMDMX
Definition: faults.hh:69
gem5::MipsISA::MipsFault::name
FaultName name() const
Definition: faults.hh:115
gem5::MipsISA::MISCREG_CONTEXT
@ MISCREG_CONTEXT
Definition: misc.hh:73
thread_context.hh
gem5::MipsISA::ExcCodeTlbS
@ ExcCodeTlbS
Definition: faults.hh:57
gem5::MipsISA::MipsFaultBase::FaultVals::offset
const FaultVect offset
Definition: faults.hh:82
gem5::MipsISA::TlbInvalidFault
Definition: faults.hh:288
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::MipsISA::NonMaskableInterrupt::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:167
gem5::MipsISA::SoftResetFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr)
Definition: faults.cc:161
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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