gem5  v22.1.0.0
misc.hh
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40 
41 #ifndef __ARCH_ARM_REGS_MISC_HH__
42 #define __ARCH_ARM_REGS_MISC_HH__
43 
44 #include <bitset>
45 #include <tuple>
46 
48 #include "arch/arm/types.hh"
49 #include "base/compiler.hh"
50 #include "cpu/reg_class.hh"
51 #include "debug/MiscRegs.hh"
53 
54 namespace gem5
55 {
56 
57 class ArmSystem;
58 class ThreadContext;
59 class MiscRegOp64;
60 
61 namespace ArmISA
62 {
64  {
80 
81  // Helper registers
98 
99  // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
203  MISCREG_TEECR, // not in ARM DDI 0487A.b+
205  MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
208 
209  // AArch32 CP15 registers (system control)
417  // BEGIN Generic Timer (AArch32)
439  // END Generic Timer (AArch32)
456 
457  // AArch64 registers (Op0=2)
540  MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
541  MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
542 
543  // AArch64 registers (Op0=1,3)
757  // BEGIN Generic Timer (AArch64)
785  // IF Armv8.1-VHE
792  // ENDIF Armv8.1-VHE
794  // END Generic Timer (AArch64)
823 
824  // Introduced in ARMv8.1
826 
828 
829  //PAuth Key Regsiters
840 
841  // GICv3, CPU interface
888 
889  // GICv3, CPU interface, virtualization
920 
963 
1010 
1057 
1058  // SVE
1064 
1065  // NUM_PHYS_MISCREGS specifies the number of actual physical
1066  // registers, not considering the following pseudo-registers
1067  // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
1068  // Checkpointing should use this physical index when
1069  // saving/restoring register values.
1071 
1072  // Dummy registers
1076 
1077  // Implementation defined register: this represent
1078  // a pool of unimplemented registers whose access can throw
1079  // either UNDEFINED or hypervisor trap exception.
1081 
1082  // RAS extension (unimplemented)
1094 
1095  // PSTATE
1098 
1099  // Total number of Misc Registers: Physical + Dummy
1100  NUM_MISCREGS
1101  };
1102 
1104  {
1106  MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
1107  // arch generic counter)
1108  MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
1109  // tells whether the instruction should raise a
1110  // warning or fail
1111  MISCREG_MUTEX, // True if the register corresponds to a pair of
1112  // mutually exclusive registers
1113  MISCREG_BANKED, // True if the register is banked between the two
1114  // security states, and this is the parent node of the
1115  // two banked registers
1116  MISCREG_BANKED64, // True if the register is banked between the two
1117  // security states, and this is the parent node of
1118  // the two banked registers. Used in AA64 only.
1119  MISCREG_BANKED_CHILD, // The entry is one of the child registers that
1120  // forms a banked set of regs (along with the
1121  // other child regs)
1122 
1123  // Access permissions
1124  // User mode
1129  // Privileged modes other than hypervisor or monitor
1134  // Hypervisor mode
1139  // Monitor mode, SCR.NS == 0
1142  // Monitor mode, SCR.NS == 1
1145 
1147  };
1148 
1151  {
1152  uint32_t lower; // Lower half mapped to this register
1153  uint32_t upper; // Upper half mapped to this register
1154  uint64_t _reset; // value taken on reset (i.e. initialization)
1155  uint64_t _res0; // reserved
1156  uint64_t _res1; // reserved
1157  uint64_t _raz; // read as zero (fixed at 0)
1158  uint64_t _rao; // read as one (fixed at 1)
1159  std::bitset<NUM_MISCREG_INFOS> info;
1160 
1161  using FaultCB = std::function<
1162  Fault(const MiscRegLUTEntry &entry, ThreadContext *tc,
1163  const MiscRegOp64 &inst)
1164  >;
1165 
1166  std::array<FaultCB, EL3 + 1> faultRead;
1167  std::array<FaultCB, EL3 + 1> faultWrite;
1168 
1169  Fault checkFault(ThreadContext *tc, const MiscRegOp64 &inst,
1170  ExceptionLevel el);
1171 
1172  protected:
1173  template <MiscRegInfo Sec, MiscRegInfo NonSec>
1174  static Fault defaultFault(const MiscRegLUTEntry &entry,
1175  ThreadContext *tc, const MiscRegOp64 &inst);
1176 
1177  public:
1179  lower(0), upper(0),
1180  _reset(0), _res0(0), _res1(0), _raz(0), _rao(0), info(0),
1181  faultRead({defaultFault<MISCREG_USR_S_RD, MISCREG_USR_NS_RD>,
1182  defaultFault<MISCREG_PRI_S_RD, MISCREG_PRI_NS_RD>,
1183  defaultFault<MISCREG_HYP_S_RD, MISCREG_HYP_NS_RD>,
1184  defaultFault<MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD>}),
1185  faultWrite({defaultFault<MISCREG_USR_S_WR, MISCREG_USR_NS_WR>,
1186  defaultFault<MISCREG_PRI_S_WR, MISCREG_PRI_NS_WR>,
1187  defaultFault<MISCREG_HYP_S_WR, MISCREG_HYP_NS_WR>,
1188  defaultFault<MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR>})
1189  {}
1190  uint64_t reset() const { return _reset; }
1191  uint64_t res0() const { return _res0; }
1192  uint64_t res1() const { return _res1; }
1193  uint64_t raz() const { return _raz; }
1194  uint64_t rao() const { return _rao; }
1195  // raz/rao implies writes ignored
1196  uint64_t wi() const { return _raz | _rao; }
1197  };
1198 
1201  {
1204  public:
1205  chain
1206  mapsTo(uint32_t l, uint32_t u = 0) const
1207  {
1208  entry.lower = l;
1209  entry.upper = u;
1210  return *this;
1211  }
1212  chain
1213  res0(uint64_t mask) const
1214  {
1215  entry._res0 = mask;
1216  return *this;
1217  }
1218  chain
1219  res1(uint64_t mask) const
1220  {
1221  entry._res1 = mask;
1222  return *this;
1223  }
1224  chain
1225  raz(uint64_t mask) const
1226  {
1227  entry._raz = mask;
1228  return *this;
1229  }
1230  chain
1231  rao(uint64_t mask) const
1232  {
1233  entry._rao = mask;
1234  return *this;
1235  }
1236  chain
1237  implemented(bool v = true) const
1238  {
1240  return *this;
1241  }
1242  chain
1244  {
1245  return implemented(false);
1246  }
1247  chain
1248  unverifiable(bool v = true) const
1249  {
1251  return *this;
1252  }
1253  chain
1254  warnNotFail(bool v = true) const
1255  {
1257  return *this;
1258  }
1259  chain
1260  mutex(bool v = true) const
1261  {
1263  return *this;
1264  }
1265  chain
1266  banked(bool v = true) const
1267  {
1269  return *this;
1270  }
1271  chain
1272  banked64(bool v = true) const
1273  {
1275  return *this;
1276  }
1277  chain
1278  bankedChild(bool v = true) const
1279  {
1281  return *this;
1282  }
1283  chain
1284  userNonSecureRead(bool v = true) const
1285  {
1287  return *this;
1288  }
1289  chain
1290  userNonSecureWrite(bool v = true) const
1291  {
1293  return *this;
1294  }
1295  chain
1296  userSecureRead(bool v = true) const
1297  {
1299  return *this;
1300  }
1301  chain
1302  userSecureWrite(bool v = true) const
1303  {
1305  return *this;
1306  }
1307  chain
1308  user(bool v = true) const
1309  {
1312  userSecureRead(v);
1313  userSecureWrite(v);
1314  return *this;
1315  }
1316  chain
1317  privNonSecureRead(bool v = true) const
1318  {
1320  return *this;
1321  }
1322  chain
1323  privNonSecureWrite(bool v = true) const
1324  {
1326  return *this;
1327  }
1328  chain
1329  privNonSecure(bool v = true) const
1330  {
1333  return *this;
1334  }
1335  chain
1336  privSecureRead(bool v = true) const
1337  {
1339  return *this;
1340  }
1341  chain
1342  privSecureWrite(bool v = true) const
1343  {
1345  return *this;
1346  }
1347  chain
1348  privSecure(bool v = true) const
1349  {
1350  privSecureRead(v);
1351  privSecureWrite(v);
1352  return *this;
1353  }
1354  chain
1355  priv(bool v = true) const
1356  {
1357  privSecure(v);
1358  privNonSecure(v);
1359  return *this;
1360  }
1361  chain
1362  privRead(bool v = true) const
1363  {
1364  privSecureRead(v);
1366  return *this;
1367  }
1368  chain
1369  hypSecureRead(bool v = true) const
1370  {
1372  return *this;
1373  }
1374  chain
1375  hypNonSecureRead(bool v = true) const
1376  {
1378  return *this;
1379  }
1380  chain
1381  hypRead(bool v = true) const
1382  {
1383  hypSecureRead(v);
1385  return *this;
1386  }
1387  chain
1388  hypSecureWrite(bool v = true) const
1389  {
1391  return *this;
1392  }
1393  chain
1394  hypNonSecureWrite(bool v = true) const
1395  {
1397  return *this;
1398  }
1399  chain
1400  hypWrite(bool v = true) const
1401  {
1402  hypSecureWrite(v);
1404  return *this;
1405  }
1406  chain
1407  hypSecure(bool v = true) const
1408  {
1409  hypSecureRead(v);
1410  hypSecureWrite(v);
1411  return *this;
1412  }
1413  chain
1414  hyp(bool v = true) const
1415  {
1416  hypRead(v);
1417  hypWrite(v);
1418  return *this;
1419  }
1420  chain
1421  monSecureRead(bool v = true) const
1422  {
1424  return *this;
1425  }
1426  chain
1427  monSecureWrite(bool v = true) const
1428  {
1430  return *this;
1431  }
1432  chain
1433  monNonSecureRead(bool v = true) const
1434  {
1436  return *this;
1437  }
1438  chain
1439  monNonSecureWrite(bool v = true) const
1440  {
1442  return *this;
1443  }
1444  chain
1445  mon(bool v = true) const
1446  {
1447  monSecureRead(v);
1448  monSecureWrite(v);
1451  return *this;
1452  }
1453  chain
1454  monSecure(bool v = true) const
1455  {
1456  monSecureRead(v);
1457  monSecureWrite(v);
1458  return *this;
1459  }
1460  chain
1461  monNonSecure(bool v = true) const
1462  {
1465  return *this;
1466  }
1467  chain
1468  allPrivileges(bool v = true) const
1469  {
1472  userSecureRead(v);
1473  userSecureWrite(v);
1476  privSecureRead(v);
1477  privSecureWrite(v);
1478  hypRead(v);
1479  hypWrite(v);
1480  monSecureRead(v);
1481  monSecureWrite(v);
1484  return *this;
1485  }
1486  chain
1487  nonSecure(bool v = true) const
1488  {
1493  hypRead(v);
1494  hypWrite(v);
1497  return *this;
1498  }
1499  chain
1500  secure(bool v = true) const
1501  {
1502  userSecureRead(v);
1503  userSecureWrite(v);
1504  privSecureRead(v);
1505  privSecureWrite(v);
1506  monSecureRead(v);
1507  monSecureWrite(v);
1508  return *this;
1509  }
1510  chain
1511  reads(bool v) const
1512  {
1514  userSecureRead(v);
1516  privSecureRead(v);
1517  hypRead(v);
1518  monSecureRead(v);
1520  return *this;
1521  }
1522  chain
1523  writes(bool v) const
1524  {
1526  userSecureWrite(v);
1528  privSecureWrite(v);
1529  hypWrite(v);
1530  monSecureWrite(v);
1532  return *this;
1533  }
1534  chain
1536  {
1537  user(0);
1538  return *this;
1539  }
1540  chain highest(ArmSystem *const sys) const;
1541 
1542  chain
1544  {
1545  entry.faultRead[el] = cb;
1546  return *this;
1547  }
1548 
1549  chain
1551  {
1552  entry.faultWrite[el] = cb;
1553  return *this;
1554  }
1555 
1556  chain
1558  {
1559  return faultRead(el, cb).faultWrite(el, cb);
1560  }
1561 
1562  chain
1564  {
1565  return fault(EL0, cb).fault(EL1, cb).fault(EL2, cb).fault(EL3, cb);
1566  }
1567 
1569  : entry(e)
1570  {
1571  // force unimplemented registers to be thusly declared
1572  implemented(1);
1573  }
1574  };
1575 
1577 
1579  {
1580  MiscRegNum32(unsigned _coproc, unsigned _opc1,
1581  unsigned _crn, unsigned _crm,
1582  unsigned _opc2)
1583  : reg64(0), coproc(_coproc), opc1(_opc1), crn(_crn),
1584  crm(_crm), opc2(_opc2)
1585  {
1586  // MCR/MRC CP14 or CP15 register
1587  assert(coproc == 0b1110 || coproc == 0b1111);
1588  assert(opc1 < 8 && crn < 16 && crm < 16 && opc2 < 8);
1589  }
1590 
1591  MiscRegNum32(unsigned _coproc, unsigned _opc1,
1592  unsigned _crm)
1593  : reg64(1), coproc(_coproc), opc1(_opc1), crn(0),
1594  crm(_crm), opc2(0)
1595  {
1596  // MCRR/MRRC CP14 or CP15 register
1597  assert(coproc == 0b1110 || coproc == 0b1111);
1598  assert(opc1 < 16 && crm < 16);
1599  }
1600 
1601  MiscRegNum32(const MiscRegNum32& rhs) = default;
1602 
1603  bool
1604  operator==(const MiscRegNum32 &other) const
1605  {
1606  return reg64 == other.reg64 &&
1607  coproc == other.coproc &&
1608  opc1 == other.opc1 &&
1609  crn == other.crn &&
1610  crm == other.crm &&
1611  opc2 == other.opc2;
1612  }
1613 
1614  uint32_t
1615  packed() const
1616  {
1617  return reg64 << 19 |
1618  coproc << 15 |
1619  opc1 << 11 |
1620  crn << 7 |
1621  crm << 3 |
1622  opc2;
1623  }
1624 
1625  // 1 if the register is 64bit wide (accessed through MCRR/MRCC)
1626  // 0 otherwise. We need this when generating the hash as there
1627  // might be collisions between 32 and 64 bit registers
1628  const unsigned reg64;
1629 
1630  unsigned coproc;
1631  unsigned opc1;
1632  unsigned crn;
1633  unsigned crm;
1634  unsigned opc2;
1635  };
1636 
1638  {
1639  MiscRegNum64(unsigned _op0, unsigned _op1,
1640  unsigned _crn, unsigned _crm,
1641  unsigned _op2)
1642  : op0(_op0), op1(_op1), crn(_crn),
1643  crm(_crm), op2(_op2)
1644  {
1645  assert(op0 < 4 && op1 < 8 && crn < 16 && crm < 16 && op2 < 8);
1646  }
1647 
1648  MiscRegNum64(const MiscRegNum64& rhs) = default;
1649 
1650  bool
1651  operator==(const MiscRegNum64 &other) const
1652  {
1653  return op0 == other.op0 &&
1654  op1 == other.op1 &&
1655  crn == other.crn &&
1656  crm == other.crm &&
1657  op2 == other.op2;
1658  }
1659 
1660  uint32_t
1661  packed() const
1662  {
1663  return op0 << 14 |
1664  op1 << 11 |
1665  crn << 7 |
1666  crm << 3 |
1667  op2;
1668  }
1669 
1670  unsigned op0;
1671  unsigned op1;
1672  unsigned crn;
1673  unsigned crm;
1674  unsigned op2;
1675  };
1676 
1677  // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
1678  MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
1679  unsigned crm, unsigned opc2);
1680  MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
1681  unsigned crn, unsigned crm,
1682  unsigned op2);
1685 
1686  // Whether a particular AArch64 system register is -always- read only.
1688 
1689  // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
1690  MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
1691  unsigned crm, unsigned opc2);
1692 
1693  // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
1694  MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
1695 
1696 
1697  const char * const miscRegName[] = {
1698  "cpsr",
1699  "spsr",
1700  "spsr_fiq",
1701  "spsr_irq",
1702  "spsr_svc",
1703  "spsr_mon",
1704  "spsr_abt",
1705  "spsr_hyp",
1706  "spsr_und",
1707  "elr_hyp",
1708  "fpsid",
1709  "fpscr",
1710  "mvfr1",
1711  "mvfr0",
1712  "fpexc",
1713 
1714  // Helper registers
1715  "cpsr_mode",
1716  "cpsr_q",
1717  "fpscr_exc",
1718  "fpscr_qc",
1719  "lockaddr",
1720  "lockflag",
1721  "prrr_mair0",
1722  "prrr_mair0_ns",
1723  "prrr_mair0_s",
1724  "nmrr_mair1",
1725  "nmrr_mair1_ns",
1726  "nmrr_mair1_s",
1727  "pmxevtyper_pmccfiltr",
1728  "sctlr_rst",
1729  "sev_mailbox",
1730  "tlbi_needsync",
1731 
1732  // AArch32 CP14 registers
1733  "dbgdidr",
1734  "dbgdscrint",
1735  "dbgdccint",
1736  "dbgdtrtxint",
1737  "dbgdtrrxint",
1738  "dbgwfar",
1739  "dbgvcr",
1740  "dbgdtrrxext",
1741  "dbgdscrext",
1742  "dbgdtrtxext",
1743  "dbgoseccr",
1744  "dbgbvr0",
1745  "dbgbvr1",
1746  "dbgbvr2",
1747  "dbgbvr3",
1748  "dbgbvr4",
1749  "dbgbvr5",
1750  "dbgbvr6",
1751  "dbgbvr7",
1752  "dbgbvr8",
1753  "dbgbvr9",
1754  "dbgbvr10",
1755  "dbgbvr11",
1756  "dbgbvr12",
1757  "dbgbvr13",
1758  "dbgbvr14",
1759  "dbgbvr15",
1760  "dbgbcr0",
1761  "dbgbcr1",
1762  "dbgbcr2",
1763  "dbgbcr3",
1764  "dbgbcr4",
1765  "dbgbcr5",
1766  "dbgbcr6",
1767  "dbgbcr7",
1768  "dbgbcr8",
1769  "dbgbcr9",
1770  "dbgbcr10",
1771  "dbgbcr11",
1772  "dbgbcr12",
1773  "dbgbcr13",
1774  "dbgbcr14",
1775  "dbgbcr15",
1776  "dbgwvr0",
1777  "dbgwvr1",
1778  "dbgwvr2",
1779  "dbgwvr3",
1780  "dbgwvr4",
1781  "dbgwvr5",
1782  "dbgwvr6",
1783  "dbgwvr7",
1784  "dbgwvr8",
1785  "dbgwvr9",
1786  "dbgwvr10",
1787  "dbgwvr11",
1788  "dbgwvr12",
1789  "dbgwvr13",
1790  "dbgwvr14",
1791  "dbgwvr15",
1792  "dbgwcr0",
1793  "dbgwcr1",
1794  "dbgwcr2",
1795  "dbgwcr3",
1796  "dbgwcr4",
1797  "dbgwcr5",
1798  "dbgwcr6",
1799  "dbgwcr7",
1800  "dbgwcr8",
1801  "dbgwcr9",
1802  "dbgwcr10",
1803  "dbgwcr11",
1804  "dbgwcr12",
1805  "dbgwcr13",
1806  "dbgwcr14",
1807  "dbgwcr15",
1808  "dbgdrar",
1809  "dbgbxvr0",
1810  "dbgbxvr1",
1811  "dbgbxvr2",
1812  "dbgbxvr3",
1813  "dbgbxvr4",
1814  "dbgbxvr5",
1815  "dbgbxvr6",
1816  "dbgbxvr7",
1817  "dbgbxvr8",
1818  "dbgbxvr9",
1819  "dbgbxvr10",
1820  "dbgbxvr11",
1821  "dbgbxvr12",
1822  "dbgbxvr13",
1823  "dbgbxvr14",
1824  "dbgbxvr15",
1825  "dbgoslar",
1826  "dbgoslsr",
1827  "dbgosdlr",
1828  "dbgprcr",
1829  "dbgdsar",
1830  "dbgclaimset",
1831  "dbgclaimclr",
1832  "dbgauthstatus",
1833  "dbgdevid2",
1834  "dbgdevid1",
1835  "dbgdevid0",
1836  "teecr",
1837  "jidr",
1838  "teehbr",
1839  "joscr",
1840  "jmcr",
1841 
1842  // AArch32 CP15 registers
1843  "midr",
1844  "ctr",
1845  "tcmtr",
1846  "tlbtr",
1847  "mpidr",
1848  "revidr",
1849  "id_pfr0",
1850  "id_pfr1",
1851  "id_dfr0",
1852  "id_afr0",
1853  "id_mmfr0",
1854  "id_mmfr1",
1855  "id_mmfr2",
1856  "id_mmfr3",
1857  "id_mmfr4",
1858  "id_isar0",
1859  "id_isar1",
1860  "id_isar2",
1861  "id_isar3",
1862  "id_isar4",
1863  "id_isar5",
1864  "id_isar6",
1865  "ccsidr",
1866  "clidr",
1867  "aidr",
1868  "csselr",
1869  "csselr_ns",
1870  "csselr_s",
1871  "vpidr",
1872  "vmpidr",
1873  "sctlr",
1874  "sctlr_ns",
1875  "sctlr_s",
1876  "actlr",
1877  "actlr_ns",
1878  "actlr_s",
1879  "cpacr",
1880  "sdcr",
1881  "scr",
1882  "sder",
1883  "nsacr",
1884  "hsctlr",
1885  "hactlr",
1886  "hcr",
1887  "hcr2",
1888  "hdcr",
1889  "hcptr",
1890  "hstr",
1891  "hacr",
1892  "ttbr0",
1893  "ttbr0_ns",
1894  "ttbr0_s",
1895  "ttbr1",
1896  "ttbr1_ns",
1897  "ttbr1_s",
1898  "ttbcr",
1899  "ttbcr_ns",
1900  "ttbcr_s",
1901  "htcr",
1902  "vtcr",
1903  "dacr",
1904  "dacr_ns",
1905  "dacr_s",
1906  "dfsr",
1907  "dfsr_ns",
1908  "dfsr_s",
1909  "ifsr",
1910  "ifsr_ns",
1911  "ifsr_s",
1912  "adfsr",
1913  "adfsr_ns",
1914  "adfsr_s",
1915  "aifsr",
1916  "aifsr_ns",
1917  "aifsr_s",
1918  "hadfsr",
1919  "haifsr",
1920  "hsr",
1921  "dfar",
1922  "dfar_ns",
1923  "dfar_s",
1924  "ifar",
1925  "ifar_ns",
1926  "ifar_s",
1927  "hdfar",
1928  "hifar",
1929  "hpfar",
1930  "icialluis",
1931  "bpiallis",
1932  "par",
1933  "par_ns",
1934  "par_s",
1935  "iciallu",
1936  "icimvau",
1937  "cp15isb",
1938  "bpiall",
1939  "bpimva",
1940  "dcimvac",
1941  "dcisw",
1942  "ats1cpr",
1943  "ats1cpw",
1944  "ats1cur",
1945  "ats1cuw",
1946  "ats12nsopr",
1947  "ats12nsopw",
1948  "ats12nsour",
1949  "ats12nsouw",
1950  "dccmvac",
1951  "dccsw",
1952  "cp15dsb",
1953  "cp15dmb",
1954  "dccmvau",
1955  "dccimvac",
1956  "dccisw",
1957  "ats1hr",
1958  "ats1hw",
1959  "tlbiallis",
1960  "tlbimvais",
1961  "tlbiasidis",
1962  "tlbimvaais",
1963  "tlbimvalis",
1964  "tlbimvaalis",
1965  "itlbiall",
1966  "itlbimva",
1967  "itlbiasid",
1968  "dtlbiall",
1969  "dtlbimva",
1970  "dtlbiasid",
1971  "tlbiall",
1972  "tlbimva",
1973  "tlbiasid",
1974  "tlbimvaa",
1975  "tlbimval",
1976  "tlbimvaal",
1977  "tlbiipas2is",
1978  "tlbiipas2lis",
1979  "tlbiallhis",
1980  "tlbimvahis",
1981  "tlbiallnsnhis",
1982  "tlbimvalhis",
1983  "tlbiipas2",
1984  "tlbiipas2l",
1985  "tlbiallh",
1986  "tlbimvah",
1987  "tlbiallnsnh",
1988  "tlbimvalh",
1989  "pmcr",
1990  "pmcntenset",
1991  "pmcntenclr",
1992  "pmovsr",
1993  "pmswinc",
1994  "pmselr",
1995  "pmceid0",
1996  "pmceid1",
1997  "pmccntr",
1998  "pmxevtyper",
1999  "pmccfiltr",
2000  "pmxevcntr",
2001  "pmuserenr",
2002  "pmintenset",
2003  "pmintenclr",
2004  "pmovsset",
2005  "l2ctlr",
2006  "l2ectlr",
2007  "prrr",
2008  "prrr_ns",
2009  "prrr_s",
2010  "mair0",
2011  "mair0_ns",
2012  "mair0_s",
2013  "nmrr",
2014  "nmrr_ns",
2015  "nmrr_s",
2016  "mair1",
2017  "mair1_ns",
2018  "mair1_s",
2019  "amair0",
2020  "amair0_ns",
2021  "amair0_s",
2022  "amair1",
2023  "amair1_ns",
2024  "amair1_s",
2025  "hmair0",
2026  "hmair1",
2027  "hamair0",
2028  "hamair1",
2029  "vbar",
2030  "vbar_ns",
2031  "vbar_s",
2032  "mvbar",
2033  "rmr",
2034  "isr",
2035  "hvbar",
2036  "fcseidr",
2037  "contextidr",
2038  "contextidr_ns",
2039  "contextidr_s",
2040  "tpidrurw",
2041  "tpidrurw_ns",
2042  "tpidrurw_s",
2043  "tpidruro",
2044  "tpidruro_ns",
2045  "tpidruro_s",
2046  "tpidrprw",
2047  "tpidrprw_ns",
2048  "tpidrprw_s",
2049  "htpidr",
2050  "cntfrq",
2051  "cntpct",
2052  "cntvct",
2053  "cntp_ctl",
2054  "cntp_ctl_ns",
2055  "cntp_ctl_s",
2056  "cntp_cval",
2057  "cntp_cval_ns",
2058  "cntp_cval_s",
2059  "cntp_tval",
2060  "cntp_tval_ns",
2061  "cntp_tval_s",
2062  "cntv_ctl",
2063  "cntv_cval",
2064  "cntv_tval",
2065  "cntkctl",
2066  "cnthctl",
2067  "cnthp_ctl",
2068  "cnthp_cval",
2069  "cnthp_tval",
2070  "cntvoff",
2071  "il1data0",
2072  "il1data1",
2073  "il1data2",
2074  "il1data3",
2075  "dl1data0",
2076  "dl1data1",
2077  "dl1data2",
2078  "dl1data3",
2079  "dl1data4",
2080  "ramindex",
2081  "l2actlr",
2082  "cbar",
2083  "httbr",
2084  "vttbr",
2085  "cpumerrsr",
2086  "l2merrsr",
2087 
2088  // AArch64 registers (Op0=2)
2089  "mdccint_el1",
2090  "osdtrrx_el1",
2091  "mdscr_el1",
2092  "osdtrtx_el1",
2093  "oseccr_el1",
2094  "dbgbvr0_el1",
2095  "dbgbvr1_el1",
2096  "dbgbvr2_el1",
2097  "dbgbvr3_el1",
2098  "dbgbvr4_el1",
2099  "dbgbvr5_el1",
2100  "dbgbvr6_el1",
2101  "dbgbvr7_el1",
2102  "dbgbvr8_el1",
2103  "dbgbvr9_el1",
2104  "dbgbvr10_el1",
2105  "dbgbvr11_el1",
2106  "dbgbvr12_el1",
2107  "dbgbvr13_el1",
2108  "dbgbvr14_el1",
2109  "dbgbvr15_el1",
2110  "dbgbcr0_el1",
2111  "dbgbcr1_el1",
2112  "dbgbcr2_el1",
2113  "dbgbcr3_el1",
2114  "dbgbcr4_el1",
2115  "dbgbcr5_el1",
2116  "dbgbcr6_el1",
2117  "dbgbcr7_el1",
2118  "dbgbcr8_el1",
2119  "dbgbcr9_el1",
2120  "dbgbcr10_el1",
2121  "dbgbcr11_el1",
2122  "dbgbcr12_el1",
2123  "dbgbcr13_el1",
2124  "dbgbcr14_el1",
2125  "dbgbcr15_el1",
2126  "dbgwvr0_el1",
2127  "dbgwvr1_el1",
2128  "dbgwvr2_el1",
2129  "dbgwvr3_el1",
2130  "dbgwvr4_el1",
2131  "dbgwvr5_el1",
2132  "dbgwvr6_el1",
2133  "dbgwvr7_el1",
2134  "dbgwvr8_el1",
2135  "dbgwvr9_el1",
2136  "dbgwvr10_el1",
2137  "dbgwvr11_el1",
2138  "dbgwvr12_el1",
2139  "dbgwvr13_el1",
2140  "dbgwvr14_el1",
2141  "dbgwvr15_el1",
2142  "dbgwcr0_el1",
2143  "dbgwcr1_el1",
2144  "dbgwcr2_el1",
2145  "dbgwcr3_el1",
2146  "dbgwcr4_el1",
2147  "dbgwcr5_el1",
2148  "dbgwcr6_el1",
2149  "dbgwcr7_el1",
2150  "dbgwcr8_el1",
2151  "dbgwcr9_el1",
2152  "dbgwcr10_el1",
2153  "dbgwcr11_el1",
2154  "dbgwcr12_el1",
2155  "dbgwcr13_el1",
2156  "dbgwcr14_el1",
2157  "dbgwcr15_el1",
2158  "mdccsr_el0",
2159  "mddtr_el0",
2160  "mddtrtx_el0",
2161  "mddtrrx_el0",
2162  "dbgvcr32_el2",
2163  "mdrar_el1",
2164  "oslar_el1",
2165  "oslsr_el1",
2166  "osdlr_el1",
2167  "dbgprcr_el1",
2168  "dbgclaimset_el1",
2169  "dbgclaimclr_el1",
2170  "dbgauthstatus_el1",
2171  "teecr32_el1",
2172  "teehbr32_el1",
2173 
2174  // AArch64 registers (Op0=1,3)
2175  "midr_el1",
2176  "mpidr_el1",
2177  "revidr_el1",
2178  "id_pfr0_el1",
2179  "id_pfr1_el1",
2180  "id_dfr0_el1",
2181  "id_afr0_el1",
2182  "id_mmfr0_el1",
2183  "id_mmfr1_el1",
2184  "id_mmfr2_el1",
2185  "id_mmfr3_el1",
2186  "id_mmfr4_el1",
2187  "id_isar0_el1",
2188  "id_isar1_el1",
2189  "id_isar2_el1",
2190  "id_isar3_el1",
2191  "id_isar4_el1",
2192  "id_isar5_el1",
2193  "id_isar6_el1",
2194  "mvfr0_el1",
2195  "mvfr1_el1",
2196  "mvfr2_el1",
2197  "id_aa64pfr0_el1",
2198  "id_aa64pfr1_el1",
2199  "id_aa64dfr0_el1",
2200  "id_aa64dfr1_el1",
2201  "id_aa64afr0_el1",
2202  "id_aa64afr1_el1",
2203  "id_aa64isar0_el1",
2204  "id_aa64isar1_el1",
2205  "id_aa64mmfr0_el1",
2206  "id_aa64mmfr1_el1",
2207  "ccsidr_el1",
2208  "clidr_el1",
2209  "aidr_el1",
2210  "csselr_el1",
2211  "ctr_el0",
2212  "dczid_el0",
2213  "vpidr_el2",
2214  "vmpidr_el2",
2215  "sctlr_el1",
2216  "sctlr_el12",
2217  "actlr_el1",
2218  "cpacr_el1",
2219  "cpacr_el12",
2220  "sctlr_el2",
2221  "actlr_el2",
2222  "hcr_el2",
2223  "mdcr_el2",
2224  "cptr_el2",
2225  "hstr_el2",
2226  "hacr_el2",
2227  "sctlr_el3",
2228  "actlr_el3",
2229  "scr_el3",
2230  "sder32_el3",
2231  "cptr_el3",
2232  "mdcr_el3",
2233  "ttbr0_el1",
2234  "ttbr0_el12",
2235  "ttbr1_el1",
2236  "ttbr1_el12",
2237  "tcr_el1",
2238  "tcr_el12",
2239  "ttbr0_el2",
2240  "tcr_el2",
2241  "vttbr_el2",
2242  "vtcr_el2",
2243  "vsttbr_el2",
2244  "vstcr_el2",
2245  "ttbr0_el3",
2246  "tcr_el3",
2247  "dacr32_el2",
2248  "spsr_el1",
2249  "spsr_el12",
2250  "elr_el1",
2251  "elr_el12",
2252  "sp_el0",
2253  "spsel",
2254  "currentel",
2255  "nzcv",
2256  "daif",
2257  "fpcr",
2258  "fpsr",
2259  "dspsr_el0",
2260  "dlr_el0",
2261  "spsr_el2",
2262  "elr_el2",
2263  "sp_el1",
2264  "spsr_irq_aa64",
2265  "spsr_abt_aa64",
2266  "spsr_und_aa64",
2267  "spsr_fiq_aa64",
2268  "spsr_el3",
2269  "elr_el3",
2270  "sp_el2",
2271  "afsr0_el1",
2272  "afsr0_el12",
2273  "afsr1_el1",
2274  "afsr1_el12",
2275  "esr_el1",
2276  "esr_el12",
2277  "ifsr32_el2",
2278  "afsr0_el2",
2279  "afsr1_el2",
2280  "esr_el2",
2281  "fpexc32_el2",
2282  "afsr0_el3",
2283  "afsr1_el3",
2284  "esr_el3",
2285  "far_el1",
2286  "far_el12",
2287  "far_el2",
2288  "hpfar_el2",
2289  "far_el3",
2290  "ic_ialluis",
2291  "par_el1",
2292  "ic_iallu",
2293  "dc_ivac_xt",
2294  "dc_isw_xt",
2295  "at_s1e1r_xt",
2296  "at_s1e1w_xt",
2297  "at_s1e0r_xt",
2298  "at_s1e0w_xt",
2299  "dc_csw_xt",
2300  "dc_cisw_xt",
2301  "dc_zva_xt",
2302  "ic_ivau_xt",
2303  "dc_cvac_xt",
2304  "dc_cvau_xt",
2305  "dc_civac_xt",
2306  "at_s1e2r_xt",
2307  "at_s1e2w_xt",
2308  "at_s12e1r_xt",
2309  "at_s12e1w_xt",
2310  "at_s12e0r_xt",
2311  "at_s12e0w_xt",
2312  "at_s1e3r_xt",
2313  "at_s1e3w_xt",
2314  "tlbi_vmalle1is",
2315  "tlbi_vae1is_xt",
2316  "tlbi_aside1is_xt",
2317  "tlbi_vaae1is_xt",
2318  "tlbi_vale1is_xt",
2319  "tlbi_vaale1is_xt",
2320  "tlbi_vmalle1",
2321  "tlbi_vae1_xt",
2322  "tlbi_aside1_xt",
2323  "tlbi_vaae1_xt",
2324  "tlbi_vale1_xt",
2325  "tlbi_vaale1_xt",
2326  "tlbi_ipas2e1is_xt",
2327  "tlbi_ipas2le1is_xt",
2328  "tlbi_alle2is",
2329  "tlbi_vae2is_xt",
2330  "tlbi_alle1is",
2331  "tlbi_vale2is_xt",
2332  "tlbi_vmalls12e1is",
2333  "tlbi_ipas2e1_xt",
2334  "tlbi_ipas2le1_xt",
2335  "tlbi_alle2",
2336  "tlbi_vae2_xt",
2337  "tlbi_alle1",
2338  "tlbi_vale2_xt",
2339  "tlbi_vmalls12e1",
2340  "tlbi_alle3is",
2341  "tlbi_vae3is_xt",
2342  "tlbi_vale3is_xt",
2343  "tlbi_alle3",
2344  "tlbi_vae3_xt",
2345  "tlbi_vale3_xt",
2346  "pmintenset_el1",
2347  "pmintenclr_el1",
2348  "pmcr_el0",
2349  "pmcntenset_el0",
2350  "pmcntenclr_el0",
2351  "pmovsclr_el0",
2352  "pmswinc_el0",
2353  "pmselr_el0",
2354  "pmceid0_el0",
2355  "pmceid1_el0",
2356  "pmccntr_el0",
2357  "pmxevtyper_el0",
2358  "pmccfiltr_el0",
2359  "pmxevcntr_el0",
2360  "pmuserenr_el0",
2361  "pmovsset_el0",
2362  "mair_el1",
2363  "mair_el12",
2364  "amair_el1",
2365  "amair_el12",
2366  "mair_el2",
2367  "amair_el2",
2368  "mair_el3",
2369  "amair_el3",
2370  "l2ctlr_el1",
2371  "l2ectlr_el1",
2372  "vbar_el1",
2373  "vbar_el12",
2374  "rvbar_el1",
2375  "isr_el1",
2376  "vbar_el2",
2377  "rvbar_el2",
2378  "vbar_el3",
2379  "rvbar_el3",
2380  "rmr_el3",
2381  "contextidr_el1",
2382  "contextidr_el12",
2383  "tpidr_el1",
2384  "tpidr_el0",
2385  "tpidrro_el0",
2386  "tpidr_el2",
2387  "tpidr_el3",
2388  "cntfrq_el0",
2389  "cntpct_el0",
2390  "cntvct_el0",
2391  "cntp_ctl_el0",
2392  "cntp_cval_el0",
2393  "cntp_tval_el0",
2394  "cntv_ctl_el0",
2395  "cntv_cval_el0",
2396  "cntv_tval_el0",
2397  "cntp_ctl_el02",
2398  "cntp_cval_el02",
2399  "cntp_tval_el02",
2400  "cntv_ctl_el02",
2401  "cntv_cval_el02",
2402  "cntv_tval_el02",
2403  "cntkctl_el1",
2404  "cntkctl_el12",
2405  "cntps_ctl_el1",
2406  "cntps_cval_el1",
2407  "cntps_tval_el1",
2408  "cnthctl_el2",
2409  "cnthp_ctl_el2",
2410  "cnthp_cval_el2",
2411  "cnthp_tval_el2",
2412  "cnthps_ctl_el2",
2413  "cnthps_cval_el2",
2414  "cnthps_tval_el2",
2415  "cnthv_ctl_el2",
2416  "cnthv_cval_el2",
2417  "cnthv_tval_el2",
2418  "cnthvs_ctl_el2",
2419  "cnthvs_cval_el2",
2420  "cnthvs_tval_el2",
2421  "cntvoff_el2",
2422  "pmevcntr0_el0",
2423  "pmevcntr1_el0",
2424  "pmevcntr2_el0",
2425  "pmevcntr3_el0",
2426  "pmevcntr4_el0",
2427  "pmevcntr5_el0",
2428  "pmevtyper0_el0",
2429  "pmevtyper1_el0",
2430  "pmevtyper2_el0",
2431  "pmevtyper3_el0",
2432  "pmevtyper4_el0",
2433  "pmevtyper5_el0",
2434  "il1data0_el1",
2435  "il1data1_el1",
2436  "il1data2_el1",
2437  "il1data3_el1",
2438  "dl1data0_el1",
2439  "dl1data1_el1",
2440  "dl1data2_el1",
2441  "dl1data3_el1",
2442  "dl1data4_el1",
2443  "l2actlr_el1",
2444  "cpuactlr_el1",
2445  "cpuectlr_el1",
2446  "cpumerrsr_el1",
2447  "l2merrsr_el1",
2448  "cbar_el1",
2449  "contextidr_el2",
2450 
2451  "ttbr1_el2",
2452  "id_aa64mmfr2_el1",
2453 
2454  "apdakeyhi_el1",
2455  "apdakeylo_el1",
2456  "apdbkeyhi_el1",
2457  "apdbkeylo_el1",
2458  "apgakeyhi_el1",
2459  "apgakeylo_el1",
2460  "apiakeyhi_el1",
2461  "apiakeylo_el1",
2462  "apibkeyhi_el1",
2463  "apibkeylo_el1",
2464  // GICv3, CPU interface
2465  "icc_pmr_el1",
2466  "icc_iar0_el1",
2467  "icc_eoir0_el1",
2468  "icc_hppir0_el1",
2469  "icc_bpr0_el1",
2470  "icc_ap0r0_el1",
2471  "icc_ap0r1_el1",
2472  "icc_ap0r2_el1",
2473  "icc_ap0r3_el1",
2474  "icc_ap1r0_el1",
2475  "icc_ap1r0_el1_ns",
2476  "icc_ap1r0_el1_s",
2477  "icc_ap1r1_el1",
2478  "icc_ap1r1_el1_ns",
2479  "icc_ap1r1_el1_s",
2480  "icc_ap1r2_el1",
2481  "icc_ap1r2_el1_ns",
2482  "icc_ap1r2_el1_s",
2483  "icc_ap1r3_el1",
2484  "icc_ap1r3_el1_ns",
2485  "icc_ap1r3_el1_s",
2486  "icc_dir_el1",
2487  "icc_rpr_el1",
2488  "icc_sgi1r_el1",
2489  "icc_asgi1r_el1",
2490  "icc_sgi0r_el1",
2491  "icc_iar1_el1",
2492  "icc_eoir1_el1",
2493  "icc_hppir1_el1",
2494  "icc_bpr1_el1",
2495  "icc_bpr1_el1_ns",
2496  "icc_bpr1_el1_s",
2497  "icc_ctlr_el1",
2498  "icc_ctlr_el1_ns",
2499  "icc_ctlr_el1_s",
2500  "icc_sre_el1",
2501  "icc_sre_el1_ns",
2502  "icc_sre_el1_s",
2503  "icc_igrpen0_el1",
2504  "icc_igrpen1_el1",
2505  "icc_igrpen1_el1_ns",
2506  "icc_igrpen1_el1_s",
2507  "icc_sre_el2",
2508  "icc_ctlr_el3",
2509  "icc_sre_el3",
2510  "icc_igrpen1_el3",
2511 
2512  // GICv3, CPU interface, virtualization
2513  "ich_ap0r0_el2",
2514  "ich_ap0r1_el2",
2515  "ich_ap0r2_el2",
2516  "ich_ap0r3_el2",
2517  "ich_ap1r0_el2",
2518  "ich_ap1r1_el2",
2519  "ich_ap1r2_el2",
2520  "ich_ap1r3_el2",
2521  "ich_hcr_el2",
2522  "ich_vtr_el2",
2523  "ich_misr_el2",
2524  "ich_eisr_el2",
2525  "ich_elrsr_el2",
2526  "ich_vmcr_el2",
2527  "ich_lr0_el2",
2528  "ich_lr1_el2",
2529  "ich_lr2_el2",
2530  "ich_lr3_el2",
2531  "ich_lr4_el2",
2532  "ich_lr5_el2",
2533  "ich_lr6_el2",
2534  "ich_lr7_el2",
2535  "ich_lr8_el2",
2536  "ich_lr9_el2",
2537  "ich_lr10_el2",
2538  "ich_lr11_el2",
2539  "ich_lr12_el2",
2540  "ich_lr13_el2",
2541  "ich_lr14_el2",
2542  "ich_lr15_el2",
2543 
2544  "icv_pmr_el1",
2545  "icv_iar0_el1",
2546  "icv_eoir0_el1",
2547  "icv_hppir0_el1",
2548  "icv_bpr0_el1",
2549  "icv_ap0r0_el1",
2550  "icv_ap0r1_el1",
2551  "icv_ap0r2_el1",
2552  "icv_ap0r3_el1",
2553  "icv_ap1r0_el1",
2554  "icv_ap1r0_el1_ns",
2555  "icv_ap1r0_el1_s",
2556  "icv_ap1r1_el1",
2557  "icv_ap1r1_el1_ns",
2558  "icv_ap1r1_el1_s",
2559  "icv_ap1r2_el1",
2560  "icv_ap1r2_el1_ns",
2561  "icv_ap1r2_el1_s",
2562  "icv_ap1r3_el1",
2563  "icv_ap1r3_el1_ns",
2564  "icv_ap1r3_el1_s",
2565  "icv_dir_el1",
2566  "icv_rpr_el1",
2567  "icv_sgi1r_el1",
2568  "icv_asgi1r_el1",
2569  "icv_sgi0r_el1",
2570  "icv_iar1_el1",
2571  "icv_eoir1_el1",
2572  "icv_hppir1_el1",
2573  "icv_bpr1_el1",
2574  "icv_bpr1_el1_ns",
2575  "icv_bpr1_el1_s",
2576  "icv_ctlr_el1",
2577  "icv_ctlr_el1_ns",
2578  "icv_ctlr_el1_s",
2579  "icv_sre_el1",
2580  "icv_sre_el1_ns",
2581  "icv_sre_el1_s",
2582  "icv_igrpen0_el1",
2583  "icv_igrpen1_el1",
2584  "icv_igrpen1_el1_ns",
2585  "icv_igrpen1_el1_s",
2586 
2587  "icc_ap0r0",
2588  "icc_ap0r1",
2589  "icc_ap0r2",
2590  "icc_ap0r3",
2591  "icc_ap1r0",
2592  "icc_ap1r0_ns",
2593  "icc_ap1r0_s",
2594  "icc_ap1r1",
2595  "icc_ap1r1_ns",
2596  "icc_ap1r1_s",
2597  "icc_ap1r2",
2598  "icc_ap1r2_ns",
2599  "icc_ap1r2_s",
2600  "icc_ap1r3",
2601  "icc_ap1r3_ns",
2602  "icc_ap1r3_s",
2603  "icc_asgi1r",
2604  "icc_bpr0",
2605  "icc_bpr1",
2606  "icc_bpr1_ns",
2607  "icc_bpr1_s",
2608  "icc_ctlr",
2609  "icc_ctlr_ns",
2610  "icc_ctlr_s",
2611  "icc_dir",
2612  "icc_eoir0",
2613  "icc_eoir1",
2614  "icc_hppir0",
2615  "icc_hppir1",
2616  "icc_hsre",
2617  "icc_iar0",
2618  "icc_iar1",
2619  "icc_igrpen0",
2620  "icc_igrpen1",
2621  "icc_igrpen1_ns",
2622  "icc_igrpen1_s",
2623  "icc_mctlr",
2624  "icc_mgrpen1",
2625  "icc_msre",
2626  "icc_pmr",
2627  "icc_rpr",
2628  "icc_sgi0r",
2629  "icc_sgi1r",
2630  "icc_sre",
2631  "icc_sre_ns",
2632  "icc_sre_s",
2633 
2634  "ich_ap0r0",
2635  "ich_ap0r1",
2636  "ich_ap0r2",
2637  "ich_ap0r3",
2638  "ich_ap1r0",
2639  "ich_ap1r1",
2640  "ich_ap1r2",
2641  "ich_ap1r3",
2642  "ich_hcr",
2643  "ich_vtr",
2644  "ich_misr",
2645  "ich_eisr",
2646  "ich_elrsr",
2647  "ich_vmcr",
2648  "ich_lr0",
2649  "ich_lr1",
2650  "ich_lr2",
2651  "ich_lr3",
2652  "ich_lr4",
2653  "ich_lr5",
2654  "ich_lr6",
2655  "ich_lr7",
2656  "ich_lr8",
2657  "ich_lr9",
2658  "ich_lr10",
2659  "ich_lr11",
2660  "ich_lr12",
2661  "ich_lr13",
2662  "ich_lr14",
2663  "ich_lr15",
2664  "ich_lrc0",
2665  "ich_lrc1",
2666  "ich_lrc2",
2667  "ich_lrc3",
2668  "ich_lrc4",
2669  "ich_lrc5",
2670  "ich_lrc6",
2671  "ich_lrc7",
2672  "ich_lrc8",
2673  "ich_lrc9",
2674  "ich_lrc10",
2675  "ich_lrc11",
2676  "ich_lrc12",
2677  "ich_lrc13",
2678  "ich_lrc14",
2679  "ich_lrc15",
2680 
2681  "id_aa64zfr0_el1",
2682  "zcr_el3",
2683  "zcr_el2",
2684  "zcr_el12",
2685  "zcr_el1",
2686 
2687  "num_phys_regs",
2688 
2689  // Dummy registers
2690  "nop",
2691  "raz",
2692  "unknown",
2693  "impl_defined",
2694  "erridr_el1",
2695  "errselr_el1",
2696  "erxfr_el1",
2697  "erxctlr_el1",
2698  "erxstatus_el1",
2699  "erxaddr_el1",
2700  "erxmisc0_el1",
2701  "erxmisc1_el1",
2702  "disr_el1",
2703  "vsesr_el2",
2704  "vdisr_el2",
2705 
2706  // PSTATE
2707  "pan",
2708  "uao",
2709  };
2710 
2711  static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
2712  "The miscRegName array and NUM_MISCREGS are inconsistent.");
2713 
2715  {
2716  public:
2717  std::string
2718  regName(const RegId &id) const override
2719  {
2720  return miscRegName[id.index()];
2721  }
2722  };
2723 
2725 
2726  inline constexpr RegClass miscRegClass =
2728  debug::MiscRegs).
2729  ops(miscRegClassOps);
2730 
2731  // This mask selects bits of the CPSR that actually go in the CondCodes
2732  // integer register to allow renaming.
2733  static const uint32_t CondCodesMask = 0xF00F0000;
2734  static const uint32_t CpsrMaskQ = 0x08000000;
2735 
2736  // APSR (Application Program Status Register Mask). It is the user level
2737  // alias for the CPSR. The APSR is a subset of the CPSR. Although
2738  // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
2739  // APSR:
2740  // Bit[9] returns the value of CPSR.E.
2741  // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
2742  static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
2743 
2744  // CPSR (Current Program Status Register Mask).
2745  static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
2746 
2747  // This mask selects bits of the FPSCR that actually go in the FpCondCodes
2748  // integer register to allow renaming.
2749  static const uint32_t FpCondCodesMask = 0xF0000000;
2750  // This mask selects the cumulative saturation flag of the FPSCR.
2751  static const uint32_t FpscrQcMask = 0x08000000;
2752  // This mask selects the AHP bit of the FPSCR.
2753  static const uint32_t FpscrAhpMask = 0x04000000;
2754  // This mask selects the cumulative FP exception flags of the FPSCR.
2755  static const uint32_t FpscrExcMask = 0x0000009F;
2756 
2771  std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
2772  CPSR cpsr, ThreadContext *tc);
2773 
2788  std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
2789  CPSR cpsr, ThreadContext *tc);
2790 
2791  // Checks for UNDEFINED behaviours when accessing AArch32
2792  // Generic Timer system registers
2794 
2795  // Checks access permissions to AArch64 system registers
2797  ThreadContext *tc, const MiscRegOp64 &inst);
2798 
2799  // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
2800  // for MCR/MRC instructions
2801  int
2803 
2804  // Flattens a misc reg index using the specified security state. This is
2805  // used for opperations (eg address translations) where the security
2806  // state of the register access may differ from the current state of the
2807  // processor
2808  int
2810 
2811  int
2813 
2814  // Takes a misc reg index and returns the root reg if its one of a set of
2815  // banked registers
2816  void
2818 
2819  int
2820  unflattenMiscReg(int reg);
2821 
2822 } // namespace ArmISA
2823 } // namespace gem5
2824 
2825 namespace std
2826 {
2827 template<>
2828 struct hash<gem5::ArmISA::MiscRegNum32>
2829 {
2830  size_t
2832  {
2833  return reg.packed();
2834  }
2835 };
2836 
2837 template<>
2838 struct hash<gem5::ArmISA::MiscRegNum64>
2839 {
2840  size_t
2842  {
2843  return reg.packed();
2844  }
2845 };
2846 } // namespace std
2847 
2848 #endif // __ARCH_ARM_REGS_MISC_HH__
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Definition: misc.hh:2718
Metadata table accessible via the value of the register.
Definition: misc.hh:1201
chain userNonSecureWrite(bool v=true) const
Definition: misc.hh:1290
const MiscRegLUTEntryInitializer & chain
Definition: misc.hh:1203
chain userSecureWrite(bool v=true) const
Definition: misc.hh:1302
chain warnNotFail(bool v=true) const
Definition: misc.hh:1254
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition: misc.hh:1206
chain fault(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition: misc.hh:1557
chain userSecureRead(bool v=true) const
Definition: misc.hh:1296
chain implemented(bool v=true) const
Definition: misc.hh:1237
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
Definition: misc.hh:1568
chain highest(ArmSystem *const sys) const
Definition: misc.cc:2057
chain secure(bool v=true) const
Definition: misc.hh:1500
chain mutex(bool v=true) const
Definition: misc.hh:1260
chain hypNonSecureWrite(bool v=true) const
Definition: misc.hh:1394
chain priv(bool v=true) const
Definition: misc.hh:1355
chain raz(uint64_t mask) const
Definition: misc.hh:1225
chain hypSecureRead(bool v=true) const
Definition: misc.hh:1369
chain rao(uint64_t mask) const
Definition: misc.hh:1231
chain monSecure(bool v=true) const
Definition: misc.hh:1454
chain privSecure(bool v=true) const
Definition: misc.hh:1348
chain privSecureRead(bool v=true) const
Definition: misc.hh:1336
chain privNonSecure(bool v=true) const
Definition: misc.hh:1329
chain hypSecureWrite(bool v=true) const
Definition: misc.hh:1388
chain userNonSecureRead(bool v=true) const
Definition: misc.hh:1284
chain nonSecure(bool v=true) const
Definition: misc.hh:1487
chain privNonSecureRead(bool v=true) const
Definition: misc.hh:1317
chain monNonSecureWrite(bool v=true) const
Definition: misc.hh:1439
chain monNonSecureRead(bool v=true) const
Definition: misc.hh:1433
chain user(bool v=true) const
Definition: misc.hh:1308
chain unverifiable(bool v=true) const
Definition: misc.hh:1248
chain hypSecure(bool v=true) const
Definition: misc.hh:1407
chain banked(bool v=true) const
Definition: misc.hh:1266
chain privRead(bool v=true) const
Definition: misc.hh:1362
chain hypRead(bool v=true) const
Definition: misc.hh:1381
struct MiscRegLUTEntry & entry
Definition: misc.hh:1202
chain banked64(bool v=true) const
Definition: misc.hh:1272
chain fault(MiscRegLUTEntry::FaultCB cb) const
Definition: misc.hh:1563
chain res0(uint64_t mask) const
Definition: misc.hh:1213
chain bankedChild(bool v=true) const
Definition: misc.hh:1278
chain hypWrite(bool v=true) const
Definition: misc.hh:1400
chain allPrivileges(bool v=true) const
Definition: misc.hh:1468
chain monSecureRead(bool v=true) const
Definition: misc.hh:1421
chain privSecureWrite(bool v=true) const
Definition: misc.hh:1342
chain res1(uint64_t mask) const
Definition: misc.hh:1219
chain faultRead(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition: misc.hh:1543
chain hypNonSecureRead(bool v=true) const
Definition: misc.hh:1375
chain monNonSecure(bool v=true) const
Definition: misc.hh:1461
chain monSecureWrite(bool v=true) const
Definition: misc.hh:1427
chain mon(bool v=true) const
Definition: misc.hh:1445
chain privNonSecureWrite(bool v=true) const
Definition: misc.hh:1323
chain faultWrite(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition: misc.hh:1550
chain hyp(bool v=true) const
Definition: misc.hh:1414
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition: misc64.hh:125
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
ThreadContext is the external interface to all thread state for anything outside of the CPU.
STL vector class.
Definition: stl.hh:37
Bitfield< 28 > v
Definition: misc_types.hh:54
MiscRegNum64 encodeAArch64SysReg(MiscRegIndex misc_reg)
Definition: misc.cc:2001
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:658
static const uint32_t FpscrQcMask
Definition: misc.hh:2751
static MiscRegClassOps miscRegClassOps
Definition: misc.hh:2724
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
bool aarch64SysRegReadOnly(MiscRegIndex miscReg)
static const uint32_t CpsrMask
Definition: misc.hh:2745
static const uint32_t FpscrExcMask
Definition: misc.hh:2755
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: misc.cc:1975
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: misc.cc:533
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
Definition: misc.cc:728
static const uint32_t ApsrMask
Definition: misc.hh:2742
Bitfield< 7, 5 > opc2
Definition: types.hh:106
static const uint32_t CpsrMaskQ
Definition: misc.hh:2734
static const uint32_t FpCondCodesMask
Definition: misc.hh:2749
Bitfield< 9 > e
Definition: misc_types.hh:65
Bitfield< 0 > ns
Definition: misc_types.hh:338
void preUnflattenMiscReg()
Definition: misc.cc:706
Bitfield< 22 > u
Definition: misc_types.hh:359
static const uint32_t FpscrAhpMask
Definition: misc.hh:2753
MiscRegIndex
Definition: misc.hh:64
@ MISCREG_PMXEVTYPER_EL0
Definition: misc.hh:726
@ MISCREG_ERXSTATUS_EL1
Definition: misc.hh:1087
@ MISCREG_AMAIR_EL3
Definition: misc.hh:738
@ MISCREG_DBGWVR1_EL1
Definition: misc.hh:496
@ MISCREG_DBGDRAR
Definition: misc.hh:175
@ MISCREG_NSACR
Definition: misc.hh:250
@ MISCREG_DL1DATA1
Definition: misc.hh:445
@ MISCREG_ID_AA64PFR0_EL1
Definition: misc.hh:566
@ MISCREG_DBGWCR5
Definition: misc.hh:164
@ MISCREG_ICH_VMCR
Definition: misc.hh:1024
@ MISCREG_CSSELR_NS
Definition: misc.hh:236
@ MISCREG_HSTR_EL2
Definition: misc.hh:594
@ MISCREG_DBGWVR13_EL1
Definition: misc.hh:508
@ MISCREG_PMUSERENR
Definition: misc.hh:368
@ MISCREG_DBGBCR15
Definition: misc.hh:142
@ MISCREG_DBGOSLSR
Definition: misc.hh:193
@ MISCREG_DBGDTRRXext
Definition: misc.hh:107
@ MISCREG_ID_MMFR2_EL1
Definition: misc.hh:553
@ MISCREG_TTBR1_EL12
Definition: misc.hh:605
@ MISCREG_DCCISW
Definition: misc.hh:323
@ MISCREG_ERRIDR_EL1
Definition: misc.hh:1083
@ MISCREG_DACR_S
Definition: misc.hh:272
@ MISCREG_CNTV_CTL_EL0
Definition: misc.hh:764
@ MISCREG_ICH_LR7
Definition: misc.hh:1032
@ MISCREG_DBGWCR8
Definition: misc.hh:167
@ MISCREG_HCR
Definition: misc.hh:253
@ MISCREG_ICC_BPR1_EL1_NS
Definition: misc.hh:872
@ MISCREG_NMRR_NS
Definition: misc.hh:381
@ MISCREG_CPSR_MODE
Definition: misc.hh:82
@ MISCREG_PRRR_MAIR0
Definition: misc.hh:88
@ MISCREG_TLBI_ALLE3
Definition: misc.hh:712
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition: misc.hh:882
@ MISCREG_TLBI_ALLE1IS
Definition: misc.hh:699
@ MISCREG_ICV_BPR0_EL1
Definition: misc.hh:925
@ MISCREG_ICH_AP0R2_EL2
Definition: misc.hh:892
@ MISCREG_VSTCR_EL2
Definition: misc.hh:613
@ MISCREG_DBGWVR14
Definition: misc.hh:157
@ MISCREG_HDFAR
Definition: misc.hh:294
@ MISCREG_MPIDR_EL1
Definition: misc.hh:545
@ MISCREG_ICC_IGRPEN1
Definition: misc.hh:997
@ MISCREG_DFSR_S
Definition: misc.hh:275
@ MISCREG_IL1DATA1
Definition: misc.hh:441
@ MISCREG_DBGWVR10_EL1
Definition: misc.hh:505
@ MISCREG_DL1DATA0
Definition: misc.hh:444
@ MISCREG_CPUECTLR_EL1
Definition: misc.hh:818
@ MISCREG_ATS1HR
Definition: misc.hh:324
@ MISCREG_ERXCTLR_EL1
Definition: misc.hh:1086
@ MISCREG_SCTLR_EL2
Definition: misc.hh:589
@ MISCREG_PMSELR_EL0
Definition: misc.hh:722
@ MISCREG_ID_DFR0_EL1
Definition: misc.hh:549
@ MISCREG_CNTV_CVAL_EL02
Definition: misc.hh:771
@ MISCREG_TLBI_IPAS2E1IS_Xt
Definition: misc.hh:695
@ MISCREG_CP15ISB
Definition: misc.hh:304
@ MISCREG_CNTP_CTL_EL0
Definition: misc.hh:761
@ MISCREG_DFAR_NS
Definition: misc.hh:289
@ MISCREG_DBGBXVR8
Definition: misc.hh:184
@ MISCREG_TLBIMVALIS
Definition: misc.hh:330
@ MISCREG_PMOVSSET
Definition: misc.hh:371
@ MISCREG_FPEXC
Definition: misc.hh:79
@ MISCREG_DBGWCR1
Definition: misc.hh:160
@ MISCREG_NMRR_MAIR1_S
Definition: misc.hh:93
@ MISCREG_ICH_LR7_EL2
Definition: misc.hh:911
@ MISCREG_CNTP_CTL_EL02
Definition: misc.hh:767
@ MISCREG_ICC_IAR1_EL1
Definition: misc.hh:868
@ MISCREG_SPSEL
Definition: misc.hh:622
@ MISCREG_TCR_EL2
Definition: misc.hh:609
@ MISCREG_AT_S1E1W_Xt
Definition: misc.hh:665
@ MISCREG_ID_ISAR0_EL1
Definition: misc.hh:556
@ MISCREG_DBGWCR5_EL1
Definition: misc.hh:516
@ MISCREG_DBGWVR2
Definition: misc.hh:145
@ MISCREG_ICH_LR6_EL2
Definition: misc.hh:910
@ MISCREG_ICH_AP1R1
Definition: misc.hh:1016
@ MISCREG_DBGDSCRint
Definition: misc.hh:101
@ MISCREG_MVFR1
Definition: misc.hh:77
@ MISCREG_IL1DATA0_EL1
Definition: misc.hh:807
@ MISCREG_MIDR_EL1
Definition: misc.hh:544
@ MISCREG_SDER
Definition: misc.hh:249
@ MISCREG_DBGWCR12_EL1
Definition: misc.hh:523
@ MISCREG_OSDLR_EL1
Definition: misc.hh:535
@ MISCREG_ICV_RPR_EL1
Definition: misc.hh:943
@ MISCREG_ICV_IGRPEN1_EL1_S
Definition: misc.hh:962
@ MISCREG_DL1DATA3
Definition: misc.hh:447
@ MISCREG_HTPIDR
Definition: misc.hh:416
@ MISCREG_DBGBXVR15
Definition: misc.hh:191
@ MISCREG_TLBIMVAALIS
Definition: misc.hh:331
@ MISCREG_ICV_AP1R2_EL1
Definition: misc.hh:936
@ MISCREG_ICV_AP0R3_EL1
Definition: misc.hh:929
@ MISCREG_ICC_MGRPEN1
Definition: misc.hh:1001
@ MISCREG_ZCR_EL2
Definition: misc.hh:1061
@ MISCREG_ICC_IGRPEN1_EL3
Definition: misc.hh:887
@ MISCREG_SPSR_HYP
Definition: misc.hh:72
@ MISCREG_ID_AA64ZFR0_EL1
Definition: misc.hh:1059
@ MISCREG_DBGDEVID0
Definition: misc.hh:202
@ MISCREG_CNTFRQ
Definition: misc.hh:418
@ MISCREG_DBGDSAR
Definition: misc.hh:196
@ MISCREG_AFSR1_EL12
Definition: misc.hh:643
@ MISCREG_CPUMERRSR
Definition: misc.hh:454
@ MISCREG_CPSR_Q
Definition: misc.hh:83
@ MISCREG_DBGBVR5_EL1
Definition: misc.hh:468
@ MISCREG_MAIR_EL1
Definition: misc.hh:731
@ MISCREG_ICV_AP1R1_EL1_NS
Definition: misc.hh:934
@ MISCREG_TLBI_IPAS2E1_Xt
Definition: misc.hh:702
@ MISCREG_DBGBCR2_EL1
Definition: misc.hh:481
@ MISCREG_ID_ISAR2_EL1
Definition: misc.hh:558
@ MISCREG_TLBIMVAAL
Definition: misc.hh:343
@ MISCREG_DBGBVR1_EL1
Definition: misc.hh:464
@ MISCREG_PAR_NS
Definition: misc.hh:300
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition: misc.hh:883
@ MISCREG_HAMAIR1
Definition: misc.hh:395
@ MISCREG_PMXEVCNTR_EL0
Definition: misc.hh:728
@ MISCREG_ICC_IGRPEN1_NS
Definition: misc.hh:998
@ MISCREG_ICC_PMR_EL1
Definition: misc.hh:842
@ MISCREG_CONTEXTIDR_EL1
Definition: misc.hh:750
@ MISCREG_CNTV_TVAL
Definition: misc.hh:432
@ MISCREG_VBAR_EL3
Definition: misc.hh:747
@ MISCREG_ICV_CTLR_EL1
Definition: misc.hh:953
@ MISCREG_AIFSR_NS
Definition: misc.hh:283
@ MISCREG_DBGWCR10
Definition: misc.hh:169
@ MISCREG_DBGBXVR9
Definition: misc.hh:185
@ MISCREG_ICC_CTLR_NS
Definition: misc.hh:986
@ MISCREG_CNTPS_TVAL_EL1
Definition: misc.hh:777
@ MISCREG_ICC_AP1R3
Definition: misc.hh:977
@ MISCREG_ICC_MCTLR
Definition: misc.hh:1000
@ MISCREG_HCPTR
Definition: misc.hh:256
@ MISCREG_ICV_AP1R2_EL1_S
Definition: misc.hh:938
@ MISCREG_SPSR_EL2
Definition: misc.hh:630
@ MISCREG_ICH_LR8
Definition: misc.hh:1033
@ MISCREG_ICV_AP0R0_EL1
Definition: misc.hh:926
@ MISCREG_ICC_AP1R0_EL1
Definition: misc.hh:851
@ MISCREG_ICC_BPR0_EL1
Definition: misc.hh:846
@ MISCREG_DBGWFAR
Definition: misc.hh:105
@ MISCREG_IFAR
Definition: misc.hh:291
@ MISCREG_TLBI_ALLE1
Definition: misc.hh:706
@ MISCREG_FCSEIDR
Definition: misc.hh:403
@ MISCREG_DBGWVR7
Definition: misc.hh:150
@ NUM_MISCREGS
Definition: misc.hh:1100
@ MISCREG_ID_MMFR1
Definition: misc.hh:221
@ MISCREG_AT_S1E2W_Xt
Definition: misc.hh:676
@ MISCREG_PMEVTYPER1_EL0
Definition: misc.hh:802
@ MISCREG_LOCKFLAG
Definition: misc.hh:87
@ MISCREG_ICH_LR15_EL2
Definition: misc.hh:919
@ MISCREG_FPSID
Definition: misc.hh:75
@ MISCREG_DBGBXVR12
Definition: misc.hh:188
@ MISCREG_ICH_MISR
Definition: misc.hh:1021
@ MISCREG_DBGWCR6_EL1
Definition: misc.hh:517
@ MISCREG_ID_AFR0_EL1
Definition: misc.hh:550
@ MISCREG_DBGBVR2
Definition: misc.hh:113
@ MISCREG_MAIR_EL12
Definition: misc.hh:732
@ MISCREG_ICV_IGRPEN1_EL1_NS
Definition: misc.hh:961
@ MISCREG_DBGBVR7_EL1
Definition: misc.hh:470
@ MISCREG_ICH_LRC0
Definition: misc.hh:1041
@ MISCREG_SCTLR
Definition: misc.hh:240
@ MISCREG_PAR_EL1
Definition: misc.hh:660
@ MISCREG_TTBCR
Definition: misc.hh:265
@ MISCREG_DBGWVR3_EL1
Definition: misc.hh:498
@ MISCREG_ICH_LR5
Definition: misc.hh:1030
@ MISCREG_AT_S12E1W_Xt
Definition: misc.hh:678
@ MISCREG_SCTLR_RST
Definition: misc.hh:95
@ MISCREG_TLBIIPAS2
Definition: misc.hh:350
@ MISCREG_ICV_EOIR1_EL1
Definition: misc.hh:948
@ MISCREG_ATS12NSOUW
Definition: misc.hh:316
@ MISCREG_MAIR_EL2
Definition: misc.hh:735
@ MISCREG_ICV_IGRPEN0_EL1
Definition: misc.hh:959
@ MISCREG_CNTV_CVAL
Definition: misc.hh:431
@ MISCREG_APDBKeyLo_EL1
Definition: misc.hh:833
@ MISCREG_MDRAR_EL1
Definition: misc.hh:532
@ MISCREG_CSSELR
Definition: misc.hh:235
@ MISCREG_CPACR
Definition: misc.hh:246
@ MISCREG_TLBI_VAE2_Xt
Definition: misc.hh:705
@ MISCREG_HAMAIR0
Definition: misc.hh:394
@ MISCREG_TLBIIPAS2L
Definition: misc.hh:351
@ MISCREG_ICC_BPR1_S
Definition: misc.hh:984
@ MISCREG_DBGBVR8
Definition: misc.hh:119
@ MISCREG_ADFSR_S
Definition: misc.hh:281
@ MISCREG_ICH_LRC11
Definition: misc.hh:1052
@ MISCREG_SCR_EL3
Definition: misc.hh:598
@ MISCREG_TTBR0_S
Definition: misc.hh:261
@ MISCREG_TLBIALLHIS
Definition: misc.hh:346
@ MISCREG_TLBI_ASIDE1IS_Xt
Definition: misc.hh:685
@ MISCREG_IL1DATA1_EL1
Definition: misc.hh:808
@ MISCREG_CNTKCTL_EL12
Definition: misc.hh:774
@ MISCREG_APDAKeyHi_EL1
Definition: misc.hh:830
@ MISCREG_TLBIIPAS2LIS
Definition: misc.hh:345
@ MISCREG_TLBIASIDIS
Definition: misc.hh:328
@ MISCREG_ID_AA64DFR0_EL1
Definition: misc.hh:568
@ MISCREG_ID_ISAR6
Definition: misc.hh:231
@ MISCREG_DBGCLAIMCLR
Definition: misc.hh:198
@ MISCREG_TPIDRRO_EL0
Definition: misc.hh:754
@ MISCREG_DBGBVR3
Definition: misc.hh:114
@ MISCREG_DBGWVR5_EL1
Definition: misc.hh:500
@ MISCREG_DBGOSLAR
Definition: misc.hh:192
@ MISCREG_PMEVTYPER3_EL0
Definition: misc.hh:804
@ MISCREG_ICC_SRE_EL1_NS
Definition: misc.hh:878
@ MISCREG_DBGBCR10
Definition: misc.hh:137
@ MISCREG_SPSR_SVC
Definition: misc.hh:69
@ MISCREG_REVIDR_EL1
Definition: misc.hh:546
@ MISCREG_DBGDSCRext
Definition: misc.hh:108
@ MISCREG_TLBI_VAE2IS_Xt
Definition: misc.hh:698
@ MISCREG_TCR_EL3
Definition: misc.hh:615
@ MISCREG_FPSR
Definition: misc.hh:627
@ MISCREG_UAO
Definition: misc.hh:1097
@ MISCREG_DBGDIDR
Definition: misc.hh:100
@ MISCREG_DBGBVR9_EL1
Definition: misc.hh:472
@ MISCREG_ICH_HCR_EL2
Definition: misc.hh:898
@ MISCREG_CPACR_EL12
Definition: misc.hh:588
@ MISCREG_HDCR
Definition: misc.hh:255
@ MISCREG_AIFSR_S
Definition: misc.hh:284
@ MISCREG_ESR_EL1
Definition: misc.hh:644
@ MISCREG_DISR_EL1
Definition: misc.hh:1091
@ MISCREG_ADFSR
Definition: misc.hh:279
@ MISCREG_ICC_AP1R3_EL1_NS
Definition: misc.hh:861
@ MISCREG_PMCCNTR_EL0
Definition: misc.hh:725
@ MISCREG_CNTP_TVAL
Definition: misc.hh:427
@ MISCREG_MDCCSR_EL0
Definition: misc.hh:527
@ MISCREG_ICV_AP1R3_EL1_S
Definition: misc.hh:941
@ MISCREG_DTLBIMVA
Definition: misc.hh:336
@ MISCREG_SPSR_UND_AA64
Definition: misc.hh:635
@ MISCREG_DBGWVR13
Definition: misc.hh:156
@ MISCREG_AT_S12E0W_Xt
Definition: misc.hh:680
@ MISCREG_DBGBXVR4
Definition: misc.hh:180
@ MISCREG_TCR_EL1
Definition: misc.hh:606
@ MISCREG_NOP
Definition: misc.hh:1073
@ MISCREG_PMINTENSET
Definition: misc.hh:369
@ MISCREG_TTBCR_NS
Definition: misc.hh:266
@ MISCREG_PMXEVTYPER
Definition: misc.hh:365
@ MISCREG_DBGBCR13_EL1
Definition: misc.hh:492
@ MISCREG_TPIDR_EL3
Definition: misc.hh:756
@ MISCREG_DBGBVR11
Definition: misc.hh:122
@ MISCREG_ICC_AP0R3
Definition: misc.hh:967
@ MISCREG_VMPIDR
Definition: misc.hh:239
@ MISCREG_TLBI_VAAE1_Xt
Definition: misc.hh:692
@ MISCREG_TPIDRURW_S
Definition: misc.hh:409
@ MISCREG_CCSIDR_EL1
Definition: misc.hh:576
@ MISCREG_DBGBXVR5
Definition: misc.hh:181
@ MISCREG_CNTVCT
Definition: misc.hh:420
@ MISCREG_ESR_EL12
Definition: misc.hh:645
@ MISCREG_TLBIMVALH
Definition: misc.hh:355
@ MISCREG_DL1DATA1_EL1
Definition: misc.hh:812
@ MISCREG_ICC_AP1R0_EL1_S
Definition: misc.hh:853
@ MISCREG_DBGWCR8_EL1
Definition: misc.hh:519
@ MISCREG_ICC_IGRPEN1_S
Definition: misc.hh:999
@ MISCREG_AFSR0_EL1
Definition: misc.hh:640
@ MISCREG_ICC_AP1R0_S
Definition: misc.hh:970
@ MISCREG_SPSR_UND
Definition: misc.hh:73
@ MISCREG_TCMTR
Definition: misc.hh:212
@ MISCREG_DBGWCR13_EL1
Definition: misc.hh:524
@ MISCREG_DBGOSDLR
Definition: misc.hh:194
@ MISCREG_DBGBXVR3
Definition: misc.hh:179
@ MISCREG_DBGWCR11_EL1
Definition: misc.hh:522
@ MISCREG_DBGWVR11_EL1
Definition: misc.hh:506
@ MISCREG_TLBI_ALLE2IS
Definition: misc.hh:697
@ MISCREG_SPSR_IRQ
Definition: misc.hh:68
@ MISCREG_ID_ISAR5
Definition: misc.hh:230
@ MISCREG_BPIALL
Definition: misc.hh:305
@ MISCREG_DBGBVR10_EL1
Definition: misc.hh:473
@ MISCREG_ID_ISAR3_EL1
Definition: misc.hh:559
@ MISCREG_PMEVTYPER4_EL0
Definition: misc.hh:805
@ MISCREG_ATS1CUR
Definition: misc.hh:311
@ MISCREG_ICH_ELRSR_EL2
Definition: misc.hh:902
@ MISCREG_DC_CVAC_Xt
Definition: misc.hh:672
@ MISCREG_VPIDR_EL2
Definition: misc.hh:582
@ MISCREG_DBGWCR2
Definition: misc.hh:161
@ MISCREG_OSLAR_EL1
Definition: misc.hh:533
@ MISCREG_CNTPCT_EL0
Definition: misc.hh:759
@ MISCREG_DBGWCR4_EL1
Definition: misc.hh:515
@ MISCREG_ERXADDR_EL1
Definition: misc.hh:1088
@ MISCREG_AMAIR0_NS
Definition: misc.hh:387
@ MISCREG_DBGBCR14_EL1
Definition: misc.hh:493
@ MISCREG_ICH_AP1R3
Definition: misc.hh:1018
@ MISCREG_SPSR_ABT
Definition: misc.hh:71
@ MISCREG_DBGWVR0_EL1
Definition: misc.hh:495
@ MISCREG_AFSR1_EL2
Definition: misc.hh:648
@ MISCREG_CNTV_CTL_EL02
Definition: misc.hh:770
@ MISCREG_CP15DMB
Definition: misc.hh:320
@ MISCREG_DBGBCR0_EL1
Definition: misc.hh:479
@ MISCREG_DBGWVR15
Definition: misc.hh:158
@ MISCREG_TLBIMVA
Definition: misc.hh:339
@ MISCREG_PMEVCNTR4_EL0
Definition: misc.hh:799
@ MISCREG_CONTEXTIDR_NS
Definition: misc.hh:405
@ MISCREG_ICH_AP1R3_EL2
Definition: misc.hh:897
@ MISCREG_DBGBCR6_EL1
Definition: misc.hh:485
@ MISCREG_ID_ISAR4
Definition: misc.hh:229
@ MISCREG_DBGBCR3_EL1
Definition: misc.hh:482
@ MISCREG_ICC_AP1R1_EL1_S
Definition: misc.hh:856
@ MISCREG_SCTLR_EL1
Definition: misc.hh:584
@ MISCREG_CNTP_TVAL_EL02
Definition: misc.hh:769
@ MISCREG_ICH_AP0R3
Definition: misc.hh:1014
@ MISCREG_DBGWVR4_EL1
Definition: misc.hh:499
@ MISCREG_TPIDRPRW_NS
Definition: misc.hh:414
@ MISCREG_AIDR_EL1
Definition: misc.hh:578
@ MISCREG_DC_CIVAC_Xt
Definition: misc.hh:674
@ MISCREG_DBGDEVID1
Definition: misc.hh:201
@ MISCREG_PRRR
Definition: misc.hh:374
@ MISCREG_ICC_IGRPEN0
Definition: misc.hh:996
@ MISCREG_ICH_LRC7
Definition: misc.hh:1048
@ MISCREG_TEECR
Definition: misc.hh:203
@ MISCREG_DC_CVAU_Xt
Definition: misc.hh:673
@ MISCREG_DBGBXVR7
Definition: misc.hh:183
@ MISCREG_AMAIR1_S
Definition: misc.hh:391
@ MISCREG_DBGWVR7_EL1
Definition: misc.hh:502
@ MISCREG_DBGBVR9
Definition: misc.hh:120
@ MISCREG_PMEVTYPER0_EL0
Definition: misc.hh:801
@ MISCREG_ICH_LRC8
Definition: misc.hh:1049
@ MISCREG_CPTR_EL2
Definition: misc.hh:593
@ MISCREG_ICH_LR9_EL2
Definition: misc.hh:913
@ MISCREG_DBGBCR8_EL1
Definition: misc.hh:487
@ MISCREG_CCSIDR
Definition: misc.hh:232
@ MISCREG_ICV_SRE_EL1_NS
Definition: misc.hh:957
@ MISCREG_FAR_EL1
Definition: misc.hh:654
@ MISCREG_ERXMISC0_EL1
Definition: misc.hh:1089
@ MISCREG_TPIDR_EL1
Definition: misc.hh:752
@ MISCREG_PMUSERENR_EL0
Definition: misc.hh:729
@ MISCREG_TLBI_VAAE1IS_Xt
Definition: misc.hh:686
@ MISCREG_APIAKeyLo_EL1
Definition: misc.hh:837
@ MISCREG_DBGWCR0
Definition: misc.hh:159
@ MISCREG_AT_S1E2R_Xt
Definition: misc.hh:675
@ MISCREG_PMCR
Definition: misc.hh:356
@ MISCREG_CNTHV_CTL_EL2
Definition: misc.hh:786
@ MISCREG_ICC_DIR
Definition: misc.hh:988
@ MISCREG_CNTP_TVAL_NS
Definition: misc.hh:428
@ MISCREG_CNTV_CTL
Definition: misc.hh:430
@ MISCREG_AFSR1_EL3
Definition: misc.hh:652
@ MISCREG_ADFSR_NS
Definition: misc.hh:280
@ MISCREG_APIBKeyLo_EL1
Definition: misc.hh:839
@ MISCREG_DFAR
Definition: misc.hh:288
@ MISCREG_ICV_CTLR_EL1_NS
Definition: misc.hh:954
@ MISCREG_ID_AA64DFR1_EL1
Definition: misc.hh:569
@ MISCREG_DC_CSW_Xt
Definition: misc.hh:668
@ MISCREG_JMCR
Definition: misc.hh:207
@ MISCREG_RMR_EL3
Definition: misc.hh:749
@ MISCREG_ID_AA64ISAR1_EL1
Definition: misc.hh:573
@ MISCREG_TLBIMVAL
Definition: misc.hh:342
@ MISCREG_ELR_EL12
Definition: misc.hh:620
@ MISCREG_DL1DATA2_EL1
Definition: misc.hh:813
@ MISCREG_DBGBVR0
Definition: misc.hh:111
@ MISCREG_ICC_HSRE
Definition: misc.hh:993
@ MISCREG_ICH_LR1
Definition: misc.hh:1026
@ MISCREG_PMEVCNTR0_EL0
Definition: misc.hh:795
@ MISCREG_TEECR32_EL1
Definition: misc.hh:540
@ MISCREG_AFSR0_EL3
Definition: misc.hh:651
@ MISCREG_CSSELR_EL1
Definition: misc.hh:579
@ MISCREG_VBAR_EL12
Definition: misc.hh:742
@ MISCREG_MAIR_EL3
Definition: misc.hh:737
@ MISCREG_ITLBIALL
Definition: misc.hh:332
@ MISCREG_L2MERRSR
Definition: misc.hh:455
@ MISCREG_ID_AA64MMFR1_EL1
Definition: misc.hh:575
@ MISCREG_DBGPRCR_EL1
Definition: misc.hh:536
@ MISCREG_NMRR_MAIR1
Definition: misc.hh:91
@ MISCREG_ICH_LR4_EL2
Definition: misc.hh:908
@ MISCREG_UNKNOWN
Definition: misc.hh:1075
@ MISCREG_PMOVSR
Definition: misc.hh:359
@ MISCREG_ICH_ELRSR
Definition: misc.hh:1023
@ MISCREG_TLBIALLNSNH
Definition: misc.hh:354
@ MISCREG_TTBR0_EL12
Definition: misc.hh:603
@ MISCREG_CNTHP_TVAL
Definition: misc.hh:437
@ MISCREG_ATS12NSOUR
Definition: misc.hh:315
@ MISCREG_ELR_HYP
Definition: misc.hh:74
@ MISCREG_DBGWCR10_EL1
Definition: misc.hh:521
@ MISCREG_CNTVCT_EL0
Definition: misc.hh:760
@ MISCREG_DBGBVR14
Definition: misc.hh:125
@ MISCREG_TLBI_VMALLE1
Definition: misc.hh:689
@ MISCREG_DBGBVR8_EL1
Definition: misc.hh:471
@ MISCREG_ICH_LR11_EL2
Definition: misc.hh:915
@ MISCREG_CBAR_EL1
Definition: misc.hh:821
@ MISCREG_ICC_AP1R1_EL1
Definition: misc.hh:854
@ MISCREG_ICV_AP1R1_EL1_S
Definition: misc.hh:935
@ MISCREG_DL1DATA3_EL1
Definition: misc.hh:814
@ MISCREG_RVBAR_EL2
Definition: misc.hh:746
@ MISCREG_DBGDEVID2
Definition: misc.hh:200
@ MISCREG_SP_EL0
Definition: misc.hh:621
@ MISCREG_PMCNTENCLR
Definition: misc.hh:358
@ MISCREG_ERRSELR_EL1
Definition: misc.hh:1084
@ MISCREG_TLBI_VMALLS12E1
Definition: misc.hh:708
@ MISCREG_DFAR_S
Definition: misc.hh:290
@ MISCREG_DBGBVR0_EL1
Definition: misc.hh:463
@ MISCREG_ICC_AP1R2_NS
Definition: misc.hh:975
@ MISCREG_DBGBCR4_EL1
Definition: misc.hh:483
@ MISCREG_CPSR
Definition: misc.hh:65
@ MISCREG_FPCR
Definition: misc.hh:626
@ MISCREG_SDCR
Definition: misc.hh:247
@ MISCREG_DBGWCR4
Definition: misc.hh:163
@ MISCREG_ICH_LR14_EL2
Definition: misc.hh:918
@ MISCREG_ICV_SRE_EL1_S
Definition: misc.hh:958
@ MISCREG_RMR
Definition: misc.hh:400
@ MISCREG_CPACR_EL1
Definition: misc.hh:587
@ MISCREG_HACR
Definition: misc.hh:258
@ MISCREG_ICC_RPR_EL1
Definition: misc.hh:864
@ MISCREG_DBGBXVR13
Definition: misc.hh:189
@ MISCREG_IFSR_NS
Definition: misc.hh:277
@ MISCREG_ID_MMFR0
Definition: misc.hh:220
@ MISCREG_PMEVTYPER5_EL0
Definition: misc.hh:806
@ MISCREG_CNTP_CVAL
Definition: misc.hh:424
@ MISCREG_ID_ISAR0
Definition: misc.hh:225
@ MISCREG_DBGBVR2_EL1
Definition: misc.hh:465
@ MISCREG_ICC_AP1R3_EL1_S
Definition: misc.hh:862
@ MISCREG_DL1DATA4
Definition: misc.hh:448
@ MISCREG_CNTKCTL_EL1
Definition: misc.hh:773
@ MISCREG_HMAIR0
Definition: misc.hh:392
@ MISCREG_DBGWVR11
Definition: misc.hh:154
@ MISCREG_ICC_AP0R3_EL1
Definition: misc.hh:850
@ MISCREG_ICC_BPR1_NS
Definition: misc.hh:983
@ MISCREG_CNTPCT
Definition: misc.hh:419
@ MISCREG_ICH_LR10_EL2
Definition: misc.hh:914
@ MISCREG_SP_EL2
Definition: misc.hh:639
@ MISCREG_ICC_AP0R1
Definition: misc.hh:965
@ MISCREG_PMCCFILTR_EL0
Definition: misc.hh:727
@ MISCREG_ICH_LR10
Definition: misc.hh:1035
@ MISCREG_CNTPS_CTL_EL1
Definition: misc.hh:775
@ MISCREG_TLBI_VALE2_Xt
Definition: misc.hh:707
@ MISCREG_TLBI_VMALLS12E1IS
Definition: misc.hh:701
@ MISCREG_NMRR
Definition: misc.hh:380
@ MISCREG_ICC_SRE_EL1
Definition: misc.hh:877
@ MISCREG_DBGBVR12_EL1
Definition: misc.hh:475
@ MISCREG_PMSWINC_EL0
Definition: misc.hh:721
@ MISCREG_SCTLR_EL12
Definition: misc.hh:585
@ MISCREG_DBGBVR10
Definition: misc.hh:121
@ MISCREG_TTBR1_EL1
Definition: misc.hh:604
@ MISCREG_PMEVTYPER2_EL0
Definition: misc.hh:803
@ MISCREG_MAIR1
Definition: misc.hh:383
@ MISCREG_TLBI_VAE3IS_Xt
Definition: misc.hh:710
@ MISCREG_DAIF
Definition: misc.hh:625
@ MISCREG_SPSR_ABT_AA64
Definition: misc.hh:634
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:96
@ MISCREG_SPSR_EL12
Definition: misc.hh:618
@ MISCREG_ICV_AP1R0_EL1_NS
Definition: misc.hh:931
@ MISCREG_CNTP_CVAL_EL02
Definition: misc.hh:768
@ MISCREG_ACTLR_NS
Definition: misc.hh:244
@ MISCREG_PMINTENSET_EL1
Definition: misc.hh:715
@ MISCREG_ICC_AP1R1_S
Definition: misc.hh:973
@ MISCREG_PMINTENCLR_EL1
Definition: misc.hh:716
@ MISCREG_CNTHPS_CVAL_EL2
Definition: misc.hh:783
@ MISCREG_REVIDR
Definition: misc.hh:215
@ MISCREG_DBGBCR9
Definition: misc.hh:136
@ MISCREG_DL1DATA0_EL1
Definition: misc.hh:811
@ MISCREG_TLBI_VAE1IS_Xt
Definition: misc.hh:684
@ MISCREG_PMCCFILTR
Definition: misc.hh:366
@ MISCREG_ICV_AP0R2_EL1
Definition: misc.hh:928
@ MISCREG_ACTLR_EL3
Definition: misc.hh:597
@ MISCREG_ID_PFR1_EL1
Definition: misc.hh:548
@ MISCREG_DBGBCR11_EL1
Definition: misc.hh:490
@ MISCREG_DBGBCR1_EL1
Definition: misc.hh:480
@ MISCREG_TLBIIPAS2IS
Definition: misc.hh:344
@ MISCREG_DBGBVR11_EL1
Definition: misc.hh:474
@ MISCREG_ICV_BPR1_EL1_S
Definition: misc.hh:952
@ MISCREG_DBGBCR14
Definition: misc.hh:141
@ MISCREG_DBGBCR11
Definition: misc.hh:138
@ MISCREG_APDBKeyHi_EL1
Definition: misc.hh:832
@ MISCREG_TEEHBR32_EL1
Definition: misc.hh:541
@ MISCREG_DBGBVR13
Definition: misc.hh:124
@ MISCREG_ID_MMFR3
Definition: misc.hh:223
@ MISCREG_CSSELR_S
Definition: misc.hh:237
@ MISCREG_DBGBCR12
Definition: misc.hh:139
@ MISCREG_ICH_LRC15
Definition: misc.hh:1056
@ MISCREG_ICC_SRE_EL2
Definition: misc.hh:884
@ MISCREG_ICH_HCR
Definition: misc.hh:1019
@ MISCREG_ICC_IAR0
Definition: misc.hh:994
@ MISCREG_ICV_IAR0_EL1
Definition: misc.hh:922
@ MISCREG_ICC_ASGI1R_EL1
Definition: misc.hh:866
@ MISCREG_DBGVCR32_EL2
Definition: misc.hh:531
@ MISCREG_DBGWVR9_EL1
Definition: misc.hh:504
@ MISCREG_L2ECTLR
Definition: misc.hh:373
@ MISCREG_ID_PFR0_EL1
Definition: misc.hh:547
@ MISCREG_ICC_CTLR
Definition: misc.hh:985
@ MISCREG_ICV_SGI0R_EL1
Definition: misc.hh:946
@ MISCREG_ICH_LR2_EL2
Definition: misc.hh:906
@ MISCREG_DL1DATA4_EL1
Definition: misc.hh:815
@ MISCREG_TLBIMVAAIS
Definition: misc.hh:329
@ MISCREG_ICC_EOIR0
Definition: misc.hh:989
@ MISCREG_CNTP_CVAL_NS
Definition: misc.hh:425
@ MISCREG_OSECCR_EL1
Definition: misc.hh:462
@ MISCREG_RVBAR_EL1
Definition: misc.hh:743
@ MISCREG_ISR
Definition: misc.hh:401
@ MISCREG_DBGWCR7_EL1
Definition: misc.hh:518
@ MISCREG_HAIFSR
Definition: misc.hh:286
@ MISCREG_ID_ISAR5_EL1
Definition: misc.hh:561
@ MISCREG_CONTEXTIDR
Definition: misc.hh:404
@ MISCREG_PMCEID1
Definition: misc.hh:363
@ MISCREG_TLBI_ALLE3IS
Definition: misc.hh:709
@ MISCREG_DBGBVR15_EL1
Definition: misc.hh:478
@ MISCREG_ID_ISAR4_EL1
Definition: misc.hh:560
@ MISCREG_CNTHPS_TVAL_EL2
Definition: misc.hh:784
@ MISCREG_SCR
Definition: misc.hh:248
@ MISCREG_DC_IVAC_Xt
Definition: misc.hh:662
@ MISCREG_ICC_AP1R0
Definition: misc.hh:968
@ MISCREG_ICC_HPPIR0_EL1
Definition: misc.hh:845
@ MISCREG_TLBI_IPAS2LE1IS_Xt
Definition: misc.hh:696
@ MISCREG_PMCNTENSET
Definition: misc.hh:357
@ MISCREG_ICV_CTLR_EL1_S
Definition: misc.hh:955
@ MISCREG_DBGBVR7
Definition: misc.hh:118
@ MISCREG_ICC_SGI1R_EL1
Definition: misc.hh:865
@ MISCREG_DBGWVR9
Definition: misc.hh:152
@ MISCREG_ELR_EL2
Definition: misc.hh:631
@ MISCREG_MAIR0_S
Definition: misc.hh:379
@ MISCREG_ICH_LR5_EL2
Definition: misc.hh:909
@ MISCREG_CONTEXTIDR_EL2
Definition: misc.hh:822
@ MISCREG_CNTP_TVAL_S
Definition: misc.hh:429
@ MISCREG_TCR_EL12
Definition: misc.hh:607
@ MISCREG_ICV_PMR_EL1
Definition: misc.hh:921
@ MISCREG_CNTHCTL_EL2
Definition: misc.hh:778
@ MISCREG_DBGBXVR6
Definition: misc.hh:182
@ MISCREG_DBGBXVR0
Definition: misc.hh:176
@ MISCREG_TEEHBR
Definition: misc.hh:205
@ MISCREG_ERXMISC1_EL1
Definition: misc.hh:1090
@ MISCREG_MDSCR_EL1
Definition: misc.hh:460
@ MISCREG_AMAIR1_NS
Definition: misc.hh:390
@ MISCREG_DL1DATA2
Definition: misc.hh:446
@ MISCREG_DBGWCR2_EL1
Definition: misc.hh:513
@ MISCREG_ID_MMFR4_EL1
Definition: misc.hh:555
@ MISCREG_PAR_S
Definition: misc.hh:301
@ MISCREG_DBGBCR12_EL1
Definition: misc.hh:491
@ MISCREG_ID_DFR0
Definition: misc.hh:218
@ MISCREG_CNTP_CTL_S
Definition: misc.hh:423
@ MISCREG_ICC_AP1R1_EL1_NS
Definition: misc.hh:855
@ MISCREG_TTBR1_EL2
Definition: misc.hh:825
@ MISCREG_ICC_SGI1R
Definition: misc.hh:1006
@ MISCREG_DBGDTRTXint
Definition: misc.hh:103
@ MISCREG_ID_AA64MMFR0_EL1
Definition: misc.hh:574
@ MISCREG_HPFAR
Definition: misc.hh:296
@ MISCREG_ICC_PMR
Definition: misc.hh:1003
@ MISCREG_PAN
Definition: misc.hh:1096
@ MISCREG_ICH_LRC5
Definition: misc.hh:1046
@ MISCREG_TPIDRPRW_S
Definition: misc.hh:415
@ MISCREG_ICH_LR6
Definition: misc.hh:1031
@ MISCREG_TLBIMVAHIS
Definition: misc.hh:347
@ MISCREG_IC_IALLU
Definition: misc.hh:661
@ MISCREG_ICC_AP1R2
Definition: misc.hh:974
@ MISCREG_DBGWCR9
Definition: misc.hh:168
@ MISCREG_APIAKeyHi_EL1
Definition: misc.hh:836
@ MISCREG_SPSR_EL3
Definition: misc.hh:637
@ MISCREG_APDAKeyLo_EL1
Definition: misc.hh:831
@ MISCREG_AT_S1E1R_Xt
Definition: misc.hh:664
@ MISCREG_ICH_AP1R2_EL2
Definition: misc.hh:896
@ MISCREG_DTLBIALL
Definition: misc.hh:335
@ MISCREG_TLBIALLIS
Definition: misc.hh:326
@ MISCREG_AMAIR_EL1
Definition: misc.hh:733
@ MISCREG_ICC_CTLR_EL1_NS
Definition: misc.hh:875
@ MISCREG_ICC_CTLR_S
Definition: misc.hh:987
@ MISCREG_ESR_EL3
Definition: misc.hh:653
@ MISCREG_IL1DATA0
Definition: misc.hh:440
@ MISCREG_ATS1HW
Definition: misc.hh:325
@ MISCREG_ICH_VTR
Definition: misc.hh:1020
@ MISCREG_VBAR_S
Definition: misc.hh:398
@ MISCREG_ICH_AP0R1_EL2
Definition: misc.hh:891
@ MISCREG_AT_S1E3R_Xt
Definition: misc.hh:681
@ MISCREG_ICC_SRE
Definition: misc.hh:1007
@ MISCREG_DC_ZVA_Xt
Definition: misc.hh:670
@ MISCREG_CNTHVS_TVAL_EL2
Definition: misc.hh:791
@ MISCREG_ATS1CPR
Definition: misc.hh:309
@ MISCREG_TLBIASID
Definition: misc.hh:340
@ MISCREG_ICV_AP1R0_EL1_S
Definition: misc.hh:932
@ MISCREG_ICH_LRC12
Definition: misc.hh:1053
@ MISCREG_DBGBXVR10
Definition: misc.hh:186
@ MISCREG_APGAKeyLo_EL1
Definition: misc.hh:835
@ MISCREG_ITLBIMVA
Definition: misc.hh:333
@ MISCREG_NZCV
Definition: misc.hh:624
@ MISCREG_ICV_AP1R1_EL1
Definition: misc.hh:933
@ MISCREG_HTTBR
Definition: misc.hh:452
@ MISCREG_IFSR32_EL2
Definition: misc.hh:646
@ MISCREG_ICH_LRC9
Definition: misc.hh:1050
@ MISCREG_ICV_BPR1_EL1_NS
Definition: misc.hh:951
@ MISCREG_SPSR_EL1
Definition: misc.hh:617
@ MISCREG_APIBKeyHi_EL1
Definition: misc.hh:838
@ MISCREG_FAR_EL12
Definition: misc.hh:655
@ MISCREG_MAIR0_NS
Definition: misc.hh:378
@ MISCREG_CP15DSB
Definition: misc.hh:319
@ MISCREG_ICH_LR13_EL2
Definition: misc.hh:917
@ MISCREG_ICC_CTLR_EL3
Definition: misc.hh:885
@ MISCREG_DBGDCCINT
Definition: misc.hh:102
@ MISCREG_ICC_CTLR_EL1
Definition: misc.hh:874
@ MISCREG_TLBIALLNSNHIS
Definition: misc.hh:348
@ MISCREG_CNTP_CVAL_EL0
Definition: misc.hh:762
@ MISCREG_HCR_EL2
Definition: misc.hh:591
@ MISCREG_ICV_IAR1_EL1
Definition: misc.hh:947
@ MISCREG_CNTHVS_CVAL_EL2
Definition: misc.hh:790
@ MISCREG_L2ACTLR_EL1
Definition: misc.hh:816
@ MISCREG_ICV_HPPIR0_EL1
Definition: misc.hh:924
@ MISCREG_DCIMVAC
Definition: misc.hh:307
@ MISCREG_ATS1CPW
Definition: misc.hh:310
@ MISCREG_TTBR1
Definition: misc.hh:262
@ MISCREG_AT_S12E0R_Xt
Definition: misc.hh:679
@ MISCREG_ICH_AP1R0
Definition: misc.hh:1015
@ MISCREG_MPIDR
Definition: misc.hh:214
@ MISCREG_ICC_AP0R2
Definition: misc.hh:966
@ MISCREG_DBGCLAIMSET
Definition: misc.hh:197
@ MISCREG_TLBIMVALHIS
Definition: misc.hh:349
@ MISCREG_ICV_DIR_EL1
Definition: misc.hh:942
@ MISCREG_PRRR_NS
Definition: misc.hh:375
@ MISCREG_ZCR_EL1
Definition: misc.hh:1063
@ MISCREG_PMCEID0_EL0
Definition: misc.hh:723
@ MISCREG_ID_AA64MMFR2_EL1
Definition: misc.hh:827
@ MISCREG_ICC_DIR_EL1
Definition: misc.hh:863
@ MISCREG_SDER32_EL3
Definition: misc.hh:599
@ MISCREG_TPIDR_EL0
Definition: misc.hh:753
@ MISCREG_DBGDTRTXext
Definition: misc.hh:109
@ MISCREG_DBGOSECCR
Definition: misc.hh:110
@ MISCREG_ICC_SRE_EL3
Definition: misc.hh:886
@ MISCREG_VTCR_EL2
Definition: misc.hh:611
@ MISCREG_ICV_BPR1_EL1
Definition: misc.hh:950
@ MISCREG_DBGWCR3
Definition: misc.hh:162
@ MISCREG_ELR_EL3
Definition: misc.hh:638
@ MISCREG_ITLBIASID
Definition: misc.hh:334
@ MISCREG_ICH_LR12
Definition: misc.hh:1037
@ MISCREG_DBGWCR11
Definition: misc.hh:170
@ MISCREG_DBGCLAIMSET_EL1
Definition: misc.hh:537
@ MISCREG_ICH_LR3_EL2
Definition: misc.hh:907
@ MISCREG_VTTBR
Definition: misc.hh:453
@ MISCREG_MDDTRRX_EL0
Definition: misc.hh:530
@ MISCREG_ICV_AP1R0_EL1
Definition: misc.hh:930
@ MISCREG_CNTVOFF_EL2
Definition: misc.hh:793
@ MISCREG_AIFSR
Definition: misc.hh:282
@ MISCREG_DBGWCR6
Definition: misc.hh:165
@ MISCREG_ICH_AP1R1_EL2
Definition: misc.hh:895
@ MISCREG_TLBI_VAALE1_Xt
Definition: misc.hh:694
@ MISCREG_VPIDR
Definition: misc.hh:238
@ MISCREG_ICH_AP1R2
Definition: misc.hh:1017
@ MISCREG_BPIALLIS
Definition: misc.hh:298
@ MISCREG_ICC_AP1R0_EL1_NS
Definition: misc.hh:852
@ MISCREG_ICV_AP1R2_EL1_NS
Definition: misc.hh:937
@ MISCREG_DBGWCR15
Definition: misc.hh:174
@ MISCREG_CNTHCTL
Definition: misc.hh:434
@ MISCREG_ICC_EOIR0_EL1
Definition: misc.hh:844
@ MISCREG_TTBR1_NS
Definition: misc.hh:263
@ MISCREG_FAR_EL3
Definition: misc.hh:658
@ MISCREG_ACTLR_EL1
Definition: misc.hh:586
@ MISCREG_ICH_LR8_EL2
Definition: misc.hh:912
@ MISCREG_CNTHPS_CTL_EL2
Definition: misc.hh:782
@ MISCREG_DBGBVR3_EL1
Definition: misc.hh:466
@ MISCREG_DBGVCR
Definition: misc.hh:106
@ MISCREG_MDCCINT_EL1
Definition: misc.hh:458
@ MISCREG_DBGBVR6_EL1
Definition: misc.hh:469
@ MISCREG_DBGWCR9_EL1
Definition: misc.hh:520
@ MISCREG_ICC_IAR1
Definition: misc.hh:995
@ MISCREG_IL1DATA3_EL1
Definition: misc.hh:810
@ MISCREG_ICH_LR15
Definition: misc.hh:1040
@ MISCREG_DC_CISW_Xt
Definition: misc.hh:669
@ MISCREG_ICH_AP0R0
Definition: misc.hh:1011
@ MISCREG_VBAR_EL2
Definition: misc.hh:745
@ MISCREG_ICC_AP1R2_EL1_S
Definition: misc.hh:859
@ MISCREG_DBGBCR7_EL1
Definition: misc.hh:486
@ MISCREG_ICC_EOIR1_EL1
Definition: misc.hh:869
@ MISCREG_ICIMVAU
Definition: misc.hh:303
@ MISCREG_ICH_AP0R3_EL2
Definition: misc.hh:893
@ MISCREG_DBGWCR14
Definition: misc.hh:173
@ MISCREG_DBGBCR5_EL1
Definition: misc.hh:484
@ MISCREG_L2ACTLR
Definition: misc.hh:450
@ MISCREG_ACTLR_EL2
Definition: misc.hh:590
@ MISCREG_CPUMERRSR_EL1
Definition: misc.hh:819
@ MISCREG_IFAR_NS
Definition: misc.hh:292
@ MISCREG_DBGWVR15_EL1
Definition: misc.hh:510
@ MISCREG_CTR
Definition: misc.hh:211
@ MISCREG_HPFAR_EL2
Definition: misc.hh:657
@ MISCREG_TPIDRURW
Definition: misc.hh:407
@ MISCREG_DBGBXVR11
Definition: misc.hh:187
@ MISCREG_ICH_LRC6
Definition: misc.hh:1047
@ MISCREG_ICH_LR1_EL2
Definition: misc.hh:905
@ MISCREG_CLIDR
Definition: misc.hh:233
@ MISCREG_SCTLR_S
Definition: misc.hh:242
@ MISCREG_DBGDTRRXint
Definition: misc.hh:104
@ MISCREG_ICH_AP0R1
Definition: misc.hh:1012
@ MISCREG_MDCR_EL2
Definition: misc.hh:592
@ MISCREG_VBAR
Definition: misc.hh:396