gem5 v24.0.0.0
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misc.hh
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1/*
2 * Copyright (c) 2010-2023 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef __ARCH_ARM_REGS_MISC_HH__
42#define __ARCH_ARM_REGS_MISC_HH__
43
44#include <array>
45#include <bitset>
46#include <optional>
47#include <tuple>
48
50#include "arch/arm/types.hh"
51#include "base/compiler.hh"
52#include "cpu/reg_class.hh"
53#include "debug/MiscRegs.hh"
55
56namespace gem5
57{
58
59class ArmSystem;
60class ThreadContext;
61class MiscRegOp64;
62
63namespace ArmISA
64{
66 {
82
83 // Helper registers
99
100 // AArch32 CP14 registers (debug/trace control)
204 MISCREG_TEECR, // not in ARM DDI 0487A.b+
206 MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
209
210 // AArch32 CP15 registers (system control)
418 // BEGIN Generic Timer (AArch32)
440 // END Generic Timer (AArch32)
457
458 // AArch64 registers (Op0=2)
541 MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
542 MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
543
544 // AArch64 registers (Op0=1,3)
812 // BEGIN Generic Timer (AArch64)
840 // IF Armv8.1-VHE
847 // ENDIF Armv8.1-VHE
849 // END Generic Timer (AArch64)
878
879 // Introduced in ARMv8.1
881
884
885 //PAuth Key Regsiters
896
897 // GICv3, CPU interface
944
945 // GICv3, CPU interface, virtualization
976
1019
1066
1113
1114 // SVE
1120
1121 // SME
1133
1134 // FEAT_RNG
1137
1138 // FEAT_FGT
1144
1145 // FEAT_MPAM
1162
1163 // NUM_PHYS_MISCREGS specifies the number of actual physical
1164 // registers, not considering the following pseudo-registers
1165 // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
1166 // Checkpointing should use this physical index when
1167 // saving/restoring register values.
1169
1170 // Dummy registers
1174
1175 // Implementation defined register: this represent
1176 // a pool of unimplemented registers whose access can throw
1177 // either UNDEFINED or hypervisor trap exception.
1179
1180 // RAS extension (unimplemented)
1192
1193 // PSTATE
1196
1197 // Total number of Misc Registers: Physical + Dummy
1200
1202 {
1204 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
1205 // arch generic counter)
1206 MISCREG_UNSERIALIZE, // Should the checkpointed value be restored?
1207 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
1208 // tells whether the instruction should raise a
1209 // warning or fail
1210 MISCREG_MUTEX, // True if the register corresponds to a pair of
1211 // mutually exclusive registers
1212 MISCREG_BANKED, // True if the register is banked between the two
1213 // security states, and this is the parent node of the
1214 // two banked registers
1215 MISCREG_BANKED64, // True if the register is banked between the two
1216 // security states, and this is the parent node of
1217 // the two banked registers. Used in AA64 only.
1218 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
1219 // forms a banked set of regs (along with the
1220 // other child regs)
1221
1222 // Access permissions
1223 // User mode
1228 // Privileged modes other than hypervisor or monitor
1233 // Hypervisor mode
1238 // Monitor mode, SCR.NS == 0
1241 // Monitor mode, SCR.NS == 1
1244
1247
1250 {
1251 uint32_t lower; // Lower half mapped to this register
1252 uint32_t upper; // Upper half mapped to this register
1253 uint64_t _reset; // value taken on reset (i.e. initialization)
1254 uint64_t _res0; // reserved
1255 uint64_t _res1; // reserved
1256 uint64_t _raz; // read as zero (fixed at 0)
1257 uint64_t _rao; // read as one (fixed at 1)
1258 std::bitset<NUM_MISCREG_INFOS> info;
1259
1260 using FaultCB = std::function<
1261 Fault(const MiscRegLUTEntry &entry, ThreadContext *tc,
1262 const MiscRegOp64 &inst)
1263 >;
1264
1265 std::array<FaultCB, EL3 + 1> faultRead;
1266 std::array<FaultCB, EL3 + 1> faultWrite;
1267
1268 Fault checkFault(ThreadContext *tc, const MiscRegOp64 &inst,
1270
1271 protected:
1272 template <MiscRegInfo Sec, MiscRegInfo NonSec>
1273 static Fault defaultFault(const MiscRegLUTEntry &entry,
1274 ThreadContext *tc, const MiscRegOp64 &inst);
1275
1276 public:
1289 uint64_t reset() const { return _reset; }
1290 uint64_t res0() const { return _res0; }
1291 uint64_t res1() const { return _res1; }
1292 uint64_t raz() const { return _raz; }
1293 uint64_t rao() const { return _rao; }
1294 // raz/rao implies writes ignored
1295 uint64_t wi() const { return _raz | _rao; }
1296 };
1297
1300 {
1303 public:
1304 chain
1305 mapsTo(uint32_t l, uint32_t u = 0) const
1306 {
1307 entry.lower = l;
1308 entry.upper = u;
1309 return *this;
1310 }
1311 chain
1312 reset(uint64_t res_val) const
1313 {
1314 entry._reset = res_val;
1315 return *this;
1316 }
1317 chain
1318 res0(uint64_t mask) const
1319 {
1320 entry._res0 = mask;
1321 return *this;
1322 }
1323 chain
1324 res1(uint64_t mask) const
1325 {
1326 entry._res1 = mask;
1327 return *this;
1328 }
1329 chain
1330 raz(uint64_t mask = (uint64_t)-1) const
1331 {
1332 entry._raz = mask;
1333 return *this;
1334 }
1335 chain
1336 rao(uint64_t mask = (uint64_t)-1) const
1337 {
1338 entry._rao = mask;
1339 return *this;
1340 }
1341 chain
1342 implemented(bool v = true) const
1343 {
1345 return *this;
1346 }
1347 chain
1349 {
1350 return implemented(false);
1351 }
1352 chain
1353 unverifiable(bool v = true) const
1354 {
1356 return *this;
1357 }
1358 chain
1359 unserialize(bool v = true) const
1360 {
1362 return *this;
1363 }
1364 chain
1365 warnNotFail(bool v = true) const
1366 {
1368 return *this;
1369 }
1370 chain
1371 mutex(bool v = true) const
1372 {
1374 return *this;
1375 }
1376 chain
1377 banked(bool v = true) const
1378 {
1380 return *this;
1381 }
1382 chain
1383 banked64(bool v = true) const
1384 {
1386 return *this;
1387 }
1388 chain
1389 bankedChild(bool v = true) const
1390 {
1392 return *this;
1393 }
1394 chain
1395 userNonSecureRead(bool v = true) const
1396 {
1398 return *this;
1399 }
1400 chain
1401 userNonSecureWrite(bool v = true) const
1402 {
1404 return *this;
1405 }
1406 chain
1407 userSecureRead(bool v = true) const
1408 {
1410 return *this;
1411 }
1412 chain
1413 userSecureWrite(bool v = true) const
1414 {
1416 return *this;
1417 }
1418 chain
1419 user(bool v = true) const
1420 {
1425 return *this;
1426 }
1427 chain
1428 privNonSecureRead(bool v = true) const
1429 {
1431 return *this;
1432 }
1433 chain
1434 privNonSecureWrite(bool v = true) const
1435 {
1437 return *this;
1438 }
1439 chain
1440 privNonSecure(bool v = true) const
1441 {
1444 return *this;
1445 }
1446 chain
1447 privSecureRead(bool v = true) const
1448 {
1450 return *this;
1451 }
1452 chain
1453 privSecureWrite(bool v = true) const
1454 {
1456 return *this;
1457 }
1458 chain
1459 privSecure(bool v = true) const
1460 {
1463 return *this;
1464 }
1465 chain
1466 priv(bool v = true) const
1467 {
1468 privSecure(v);
1470 return *this;
1471 }
1472 chain
1473 privRead(bool v = true) const
1474 {
1477 return *this;
1478 }
1479 chain
1480 hypSecureRead(bool v = true) const
1481 {
1483 return *this;
1484 }
1485 chain
1486 hypNonSecureRead(bool v = true) const
1487 {
1489 return *this;
1490 }
1491 chain
1492 hypRead(bool v = true) const
1493 {
1496 return *this;
1497 }
1498 chain
1499 hypSecureWrite(bool v = true) const
1500 {
1502 return *this;
1503 }
1504 chain
1505 hypNonSecureWrite(bool v = true) const
1506 {
1508 return *this;
1509 }
1510 chain
1511 hypWrite(bool v = true) const
1512 {
1515 return *this;
1516 }
1517 chain
1518 hypSecure(bool v = true) const
1519 {
1522 return *this;
1523 }
1524 chain
1525 hyp(bool v = true) const
1526 {
1527 hypRead(v);
1528 hypWrite(v);
1529 return *this;
1530 }
1531 chain
1532 monSecureRead(bool v = true) const
1533 {
1535 return *this;
1536 }
1537 chain
1538 monSecureWrite(bool v = true) const
1539 {
1541 return *this;
1542 }
1543 chain
1544 monNonSecureRead(bool v = true) const
1545 {
1547 return *this;
1548 }
1549 chain
1550 monNonSecureWrite(bool v = true) const
1551 {
1553 return *this;
1554 }
1555 chain
1556 mon(bool v = true) const
1557 {
1562 return *this;
1563 }
1564 chain
1565 monWrite(bool v = true) const
1566 {
1569 return *this;
1570 }
1571 chain
1572 monSecure(bool v = true) const
1573 {
1576 return *this;
1577 }
1578 chain
1579 monNonSecure(bool v = true) const
1580 {
1583 return *this;
1584 }
1585 chain
1586 allPrivileges(bool v = true) const
1587 {
1596 hypRead(v);
1597 hypWrite(v);
1602 return *this;
1603 }
1604 chain
1605 nonSecure(bool v = true) const
1606 {
1611 hypRead(v);
1612 hypWrite(v);
1615 return *this;
1616 }
1617 chain
1618 secure(bool v = true) const
1619 {
1626 return *this;
1627 }
1628 chain
1629 reads(bool v) const
1630 {
1635 hypRead(v);
1638 return *this;
1639 }
1640 chain
1641 writes(bool v) const
1642 {
1647 hypWrite(v);
1650 return *this;
1651 }
1652 chain
1654 {
1655 user(0);
1656 return *this;
1657 }
1658 chain highest(ArmSystem *const sys) const;
1659
1660 chain
1662 {
1663 entry.faultRead[el] = cb;
1664 return *this;
1665 }
1666
1667 chain
1669 {
1670 entry.faultWrite[el] = cb;
1671 return *this;
1672 }
1673
1674 chain
1676 {
1677 return faultRead(el, cb).faultWrite(el, cb);
1678 }
1679
1680 chain
1682 {
1683 return fault(EL0, cb).fault(EL1, cb).fault(EL2, cb).fault(EL3, cb);
1684 }
1685
1687 : entry(e)
1688 {
1689 // force unimplemented registers to be thusly declared
1691 }
1692 };
1693
1695
1697 {
1698 MiscRegNum32(unsigned _coproc, unsigned _opc1,
1699 unsigned _crn, unsigned _crm,
1700 unsigned _opc2)
1701 : reg64(0), coproc(_coproc), opc1(_opc1), crn(_crn),
1702 crm(_crm), opc2(_opc2)
1703 {
1704 // MCR/MRC CP14 or CP15 register
1705 assert(coproc == 0b1110 || coproc == 0b1111);
1706 assert(opc1 < 8 && crn < 16 && crm < 16 && opc2 < 8);
1707 }
1708
1709 MiscRegNum32(unsigned _coproc, unsigned _opc1,
1710 unsigned _crm)
1711 : reg64(1), coproc(_coproc), opc1(_opc1), crn(0),
1712 crm(_crm), opc2(0)
1713 {
1714 // MCRR/MRRC CP14 or CP15 register
1715 assert(coproc == 0b1110 || coproc == 0b1111);
1716 assert(opc1 < 16 && crm < 16);
1717 }
1718
1719 MiscRegNum32(const MiscRegNum32& rhs) = default;
1720
1721 bool
1722 operator==(const MiscRegNum32 &other) const
1723 {
1724 return reg64 == other.reg64 &&
1725 coproc == other.coproc &&
1726 opc1 == other.opc1 &&
1727 crn == other.crn &&
1728 crm == other.crm &&
1729 opc2 == other.opc2;
1730 }
1731
1732 uint32_t
1733 packed() const
1734 {
1735 return reg64 << 19 |
1736 coproc << 15 |
1737 opc1 << 11 |
1738 crn << 7 |
1739 crm << 3 |
1740 opc2;
1741 }
1742
1743 // 1 if the register is 64bit wide (accessed through MCRR/MRCC)
1744 // 0 otherwise. We need this when generating the hash as there
1745 // might be collisions between 32 and 64 bit registers
1746 const unsigned reg64;
1747
1748 unsigned coproc;
1749 unsigned opc1;
1750 unsigned crn;
1751 unsigned crm;
1752 unsigned opc2;
1753 };
1754
1756 {
1757 MiscRegNum64(unsigned _op0, unsigned _op1,
1758 unsigned _crn, unsigned _crm,
1759 unsigned _op2)
1760 : op0(_op0), op1(_op1), crn(_crn),
1761 crm(_crm), op2(_op2)
1762 {
1763 assert(op0 < 4 && op1 < 8 && crn < 16 && crm < 16 && op2 < 8);
1764 }
1765
1766 MiscRegNum64(const MiscRegNum64& rhs) = default;
1767
1768 bool
1769 operator==(const MiscRegNum64 &other) const
1770 {
1771 return op0 == other.op0 &&
1772 op1 == other.op1 &&
1773 crn == other.crn &&
1774 crm == other.crm &&
1775 op2 == other.op2;
1776 }
1777
1778 uint32_t
1779 packed() const
1780 {
1781 return op0 << 14 |
1782 op1 << 11 |
1783 crn << 7 |
1784 crm << 3 |
1785 op2;
1786 }
1787
1788 unsigned op0;
1789 unsigned op1;
1790 unsigned crn;
1791 unsigned crm;
1792 unsigned op2;
1793 };
1794
1795 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
1796 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
1797 unsigned crm, unsigned opc2);
1798 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
1799 unsigned crn, unsigned crm,
1800 unsigned op2);
1802 std::optional<MiscRegNum64> encodeAArch64SysReg(MiscRegIndex misc_reg);
1803
1804 // Whether a particular AArch64 system register is -always- read only.
1806
1807 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
1808 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
1809 unsigned crm, unsigned opc2);
1810
1811 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
1812 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
1813
1814
1815 const char * const miscRegName[] = {
1816 "cpsr",
1817 "spsr",
1818 "spsr_fiq",
1819 "spsr_irq",
1820 "spsr_svc",
1821 "spsr_mon",
1822 "spsr_abt",
1823 "spsr_hyp",
1824 "spsr_und",
1825 "elr_hyp",
1826 "fpsid",
1827 "fpscr",
1828 "mvfr1",
1829 "mvfr0",
1830 "fpexc",
1831
1832 // Helper registers
1833 "cpsr_mode",
1834 "cpsr_q",
1835 "fpscr_exc",
1836 "fpscr_qc",
1837 "lockaddr",
1838 "lockflag",
1839 "prrr_mair0",
1840 "prrr_mair0_ns",
1841 "prrr_mair0_s",
1842 "nmrr_mair1",
1843 "nmrr_mair1_ns",
1844 "nmrr_mair1_s",
1845 "pmxevtyper_pmccfiltr",
1846 "sev_mailbox",
1847 "tlbi_needsync",
1848
1849 // AArch32 CP14 registers
1850 "dbgdidr",
1851 "dbgdscrint",
1852 "dbgdccint",
1853 "dbgdtrtxint",
1854 "dbgdtrrxint",
1855 "dbgwfar",
1856 "dbgvcr",
1857 "dbgdtrrxext",
1858 "dbgdscrext",
1859 "dbgdtrtxext",
1860 "dbgoseccr",
1861 "dbgbvr0",
1862 "dbgbvr1",
1863 "dbgbvr2",
1864 "dbgbvr3",
1865 "dbgbvr4",
1866 "dbgbvr5",
1867 "dbgbvr6",
1868 "dbgbvr7",
1869 "dbgbvr8",
1870 "dbgbvr9",
1871 "dbgbvr10",
1872 "dbgbvr11",
1873 "dbgbvr12",
1874 "dbgbvr13",
1875 "dbgbvr14",
1876 "dbgbvr15",
1877 "dbgbcr0",
1878 "dbgbcr1",
1879 "dbgbcr2",
1880 "dbgbcr3",
1881 "dbgbcr4",
1882 "dbgbcr5",
1883 "dbgbcr6",
1884 "dbgbcr7",
1885 "dbgbcr8",
1886 "dbgbcr9",
1887 "dbgbcr10",
1888 "dbgbcr11",
1889 "dbgbcr12",
1890 "dbgbcr13",
1891 "dbgbcr14",
1892 "dbgbcr15",
1893 "dbgwvr0",
1894 "dbgwvr1",
1895 "dbgwvr2",
1896 "dbgwvr3",
1897 "dbgwvr4",
1898 "dbgwvr5",
1899 "dbgwvr6",
1900 "dbgwvr7",
1901 "dbgwvr8",
1902 "dbgwvr9",
1903 "dbgwvr10",
1904 "dbgwvr11",
1905 "dbgwvr12",
1906 "dbgwvr13",
1907 "dbgwvr14",
1908 "dbgwvr15",
1909 "dbgwcr0",
1910 "dbgwcr1",
1911 "dbgwcr2",
1912 "dbgwcr3",
1913 "dbgwcr4",
1914 "dbgwcr5",
1915 "dbgwcr6",
1916 "dbgwcr7",
1917 "dbgwcr8",
1918 "dbgwcr9",
1919 "dbgwcr10",
1920 "dbgwcr11",
1921 "dbgwcr12",
1922 "dbgwcr13",
1923 "dbgwcr14",
1924 "dbgwcr15",
1925 "dbgdrar",
1926 "dbgbxvr0",
1927 "dbgbxvr1",
1928 "dbgbxvr2",
1929 "dbgbxvr3",
1930 "dbgbxvr4",
1931 "dbgbxvr5",
1932 "dbgbxvr6",
1933 "dbgbxvr7",
1934 "dbgbxvr8",
1935 "dbgbxvr9",
1936 "dbgbxvr10",
1937 "dbgbxvr11",
1938 "dbgbxvr12",
1939 "dbgbxvr13",
1940 "dbgbxvr14",
1941 "dbgbxvr15",
1942 "dbgoslar",
1943 "dbgoslsr",
1944 "dbgosdlr",
1945 "dbgprcr",
1946 "dbgdsar",
1947 "dbgclaimset",
1948 "dbgclaimclr",
1949 "dbgauthstatus",
1950 "dbgdevid2",
1951 "dbgdevid1",
1952 "dbgdevid0",
1953 "teecr",
1954 "jidr",
1955 "teehbr",
1956 "joscr",
1957 "jmcr",
1958
1959 // AArch32 CP15 registers
1960 "midr",
1961 "ctr",
1962 "tcmtr",
1963 "tlbtr",
1964 "mpidr",
1965 "revidr",
1966 "id_pfr0",
1967 "id_pfr1",
1968 "id_dfr0",
1969 "id_afr0",
1970 "id_mmfr0",
1971 "id_mmfr1",
1972 "id_mmfr2",
1973 "id_mmfr3",
1974 "id_mmfr4",
1975 "id_isar0",
1976 "id_isar1",
1977 "id_isar2",
1978 "id_isar3",
1979 "id_isar4",
1980 "id_isar5",
1981 "id_isar6",
1982 "ccsidr",
1983 "clidr",
1984 "aidr",
1985 "csselr",
1986 "csselr_ns",
1987 "csselr_s",
1988 "vpidr",
1989 "vmpidr",
1990 "sctlr",
1991 "sctlr_ns",
1992 "sctlr_s",
1993 "actlr",
1994 "actlr_ns",
1995 "actlr_s",
1996 "cpacr",
1997 "sdcr",
1998 "scr",
1999 "sder",
2000 "nsacr",
2001 "hsctlr",
2002 "hactlr",
2003 "hcr",
2004 "hcr2",
2005 "hdcr",
2006 "hcptr",
2007 "hstr",
2008 "hacr",
2009 "ttbr0",
2010 "ttbr0_ns",
2011 "ttbr0_s",
2012 "ttbr1",
2013 "ttbr1_ns",
2014 "ttbr1_s",
2015 "ttbcr",
2016 "ttbcr_ns",
2017 "ttbcr_s",
2018 "htcr",
2019 "vtcr",
2020 "dacr",
2021 "dacr_ns",
2022 "dacr_s",
2023 "dfsr",
2024 "dfsr_ns",
2025 "dfsr_s",
2026 "ifsr",
2027 "ifsr_ns",
2028 "ifsr_s",
2029 "adfsr",
2030 "adfsr_ns",
2031 "adfsr_s",
2032 "aifsr",
2033 "aifsr_ns",
2034 "aifsr_s",
2035 "hadfsr",
2036 "haifsr",
2037 "hsr",
2038 "dfar",
2039 "dfar_ns",
2040 "dfar_s",
2041 "ifar",
2042 "ifar_ns",
2043 "ifar_s",
2044 "hdfar",
2045 "hifar",
2046 "hpfar",
2047 "icialluis",
2048 "bpiallis",
2049 "par",
2050 "par_ns",
2051 "par_s",
2052 "iciallu",
2053 "icimvau",
2054 "cp15isb",
2055 "bpiall",
2056 "bpimva",
2057 "dcimvac",
2058 "dcisw",
2059 "ats1cpr",
2060 "ats1cpw",
2061 "ats1cur",
2062 "ats1cuw",
2063 "ats12nsopr",
2064 "ats12nsopw",
2065 "ats12nsour",
2066 "ats12nsouw",
2067 "dccmvac",
2068 "dccsw",
2069 "cp15dsb",
2070 "cp15dmb",
2071 "dccmvau",
2072 "dccimvac",
2073 "dccisw",
2074 "ats1hr",
2075 "ats1hw",
2076 "tlbiallis",
2077 "tlbimvais",
2078 "tlbiasidis",
2079 "tlbimvaais",
2080 "tlbimvalis",
2081 "tlbimvaalis",
2082 "itlbiall",
2083 "itlbimva",
2084 "itlbiasid",
2085 "dtlbiall",
2086 "dtlbimva",
2087 "dtlbiasid",
2088 "tlbiall",
2089 "tlbimva",
2090 "tlbiasid",
2091 "tlbimvaa",
2092 "tlbimval",
2093 "tlbimvaal",
2094 "tlbiipas2is",
2095 "tlbiipas2lis",
2096 "tlbiallhis",
2097 "tlbimvahis",
2098 "tlbiallnsnhis",
2099 "tlbimvalhis",
2100 "tlbiipas2",
2101 "tlbiipas2l",
2102 "tlbiallh",
2103 "tlbimvah",
2104 "tlbiallnsnh",
2105 "tlbimvalh",
2106 "pmcr",
2107 "pmcntenset",
2108 "pmcntenclr",
2109 "pmovsr",
2110 "pmswinc",
2111 "pmselr",
2112 "pmceid0",
2113 "pmceid1",
2114 "pmccntr",
2115 "pmxevtyper",
2116 "pmccfiltr",
2117 "pmxevcntr",
2118 "pmuserenr",
2119 "pmintenset",
2120 "pmintenclr",
2121 "pmovsset",
2122 "l2ctlr",
2123 "l2ectlr",
2124 "prrr",
2125 "prrr_ns",
2126 "prrr_s",
2127 "mair0",
2128 "mair0_ns",
2129 "mair0_s",
2130 "nmrr",
2131 "nmrr_ns",
2132 "nmrr_s",
2133 "mair1",
2134 "mair1_ns",
2135 "mair1_s",
2136 "amair0",
2137 "amair0_ns",
2138 "amair0_s",
2139 "amair1",
2140 "amair1_ns",
2141 "amair1_s",
2142 "hmair0",
2143 "hmair1",
2144 "hamair0",
2145 "hamair1",
2146 "vbar",
2147 "vbar_ns",
2148 "vbar_s",
2149 "mvbar",
2150 "rmr",
2151 "isr",
2152 "hvbar",
2153 "fcseidr",
2154 "contextidr",
2155 "contextidr_ns",
2156 "contextidr_s",
2157 "tpidrurw",
2158 "tpidrurw_ns",
2159 "tpidrurw_s",
2160 "tpidruro",
2161 "tpidruro_ns",
2162 "tpidruro_s",
2163 "tpidrprw",
2164 "tpidrprw_ns",
2165 "tpidrprw_s",
2166 "htpidr",
2167 "cntfrq",
2168 "cntpct",
2169 "cntvct",
2170 "cntp_ctl",
2171 "cntp_ctl_ns",
2172 "cntp_ctl_s",
2173 "cntp_cval",
2174 "cntp_cval_ns",
2175 "cntp_cval_s",
2176 "cntp_tval",
2177 "cntp_tval_ns",
2178 "cntp_tval_s",
2179 "cntv_ctl",
2180 "cntv_cval",
2181 "cntv_tval",
2182 "cntkctl",
2183 "cnthctl",
2184 "cnthp_ctl",
2185 "cnthp_cval",
2186 "cnthp_tval",
2187 "cntvoff",
2188 "il1data0",
2189 "il1data1",
2190 "il1data2",
2191 "il1data3",
2192 "dl1data0",
2193 "dl1data1",
2194 "dl1data2",
2195 "dl1data3",
2196 "dl1data4",
2197 "ramindex",
2198 "l2actlr",
2199 "cbar",
2200 "httbr",
2201 "vttbr",
2202 "cpumerrsr",
2203 "l2merrsr",
2204
2205 // AArch64 registers (Op0=2)
2206 "mdccint_el1",
2207 "osdtrrx_el1",
2208 "mdscr_el1",
2209 "osdtrtx_el1",
2210 "oseccr_el1",
2211 "dbgbvr0_el1",
2212 "dbgbvr1_el1",
2213 "dbgbvr2_el1",
2214 "dbgbvr3_el1",
2215 "dbgbvr4_el1",
2216 "dbgbvr5_el1",
2217 "dbgbvr6_el1",
2218 "dbgbvr7_el1",
2219 "dbgbvr8_el1",
2220 "dbgbvr9_el1",
2221 "dbgbvr10_el1",
2222 "dbgbvr11_el1",
2223 "dbgbvr12_el1",
2224 "dbgbvr13_el1",
2225 "dbgbvr14_el1",
2226 "dbgbvr15_el1",
2227 "dbgbcr0_el1",
2228 "dbgbcr1_el1",
2229 "dbgbcr2_el1",
2230 "dbgbcr3_el1",
2231 "dbgbcr4_el1",
2232 "dbgbcr5_el1",
2233 "dbgbcr6_el1",
2234 "dbgbcr7_el1",
2235 "dbgbcr8_el1",
2236 "dbgbcr9_el1",
2237 "dbgbcr10_el1",
2238 "dbgbcr11_el1",
2239 "dbgbcr12_el1",
2240 "dbgbcr13_el1",
2241 "dbgbcr14_el1",
2242 "dbgbcr15_el1",
2243 "dbgwvr0_el1",
2244 "dbgwvr1_el1",
2245 "dbgwvr2_el1",
2246 "dbgwvr3_el1",
2247 "dbgwvr4_el1",
2248 "dbgwvr5_el1",
2249 "dbgwvr6_el1",
2250 "dbgwvr7_el1",
2251 "dbgwvr8_el1",
2252 "dbgwvr9_el1",
2253 "dbgwvr10_el1",
2254 "dbgwvr11_el1",
2255 "dbgwvr12_el1",
2256 "dbgwvr13_el1",
2257 "dbgwvr14_el1",
2258 "dbgwvr15_el1",
2259 "dbgwcr0_el1",
2260 "dbgwcr1_el1",
2261 "dbgwcr2_el1",
2262 "dbgwcr3_el1",
2263 "dbgwcr4_el1",
2264 "dbgwcr5_el1",
2265 "dbgwcr6_el1",
2266 "dbgwcr7_el1",
2267 "dbgwcr8_el1",
2268 "dbgwcr9_el1",
2269 "dbgwcr10_el1",
2270 "dbgwcr11_el1",
2271 "dbgwcr12_el1",
2272 "dbgwcr13_el1",
2273 "dbgwcr14_el1",
2274 "dbgwcr15_el1",
2275 "mdccsr_el0",
2276 "mddtr_el0",
2277 "mddtrtx_el0",
2278 "mddtrrx_el0",
2279 "dbgvcr32_el2",
2280 "mdrar_el1",
2281 "oslar_el1",
2282 "oslsr_el1",
2283 "osdlr_el1",
2284 "dbgprcr_el1",
2285 "dbgclaimset_el1",
2286 "dbgclaimclr_el1",
2287 "dbgauthstatus_el1",
2288 "teecr32_el1",
2289 "teehbr32_el1",
2290
2291 // AArch64 registers (Op0=1,3)
2292 "midr_el1",
2293 "mpidr_el1",
2294 "revidr_el1",
2295 "id_pfr0_el1",
2296 "id_pfr1_el1",
2297 "id_dfr0_el1",
2298 "id_afr0_el1",
2299 "id_mmfr0_el1",
2300 "id_mmfr1_el1",
2301 "id_mmfr2_el1",
2302 "id_mmfr3_el1",
2303 "id_mmfr4_el1",
2304 "id_isar0_el1",
2305 "id_isar1_el1",
2306 "id_isar2_el1",
2307 "id_isar3_el1",
2308 "id_isar4_el1",
2309 "id_isar5_el1",
2310 "id_isar6_el1",
2311 "mvfr0_el1",
2312 "mvfr1_el1",
2313 "mvfr2_el1",
2314 "id_aa64pfr0_el1",
2315 "id_aa64pfr1_el1",
2316 "id_aa64dfr0_el1",
2317 "id_aa64dfr1_el1",
2318 "id_aa64afr0_el1",
2319 "id_aa64afr1_el1",
2320 "id_aa64isar0_el1",
2321 "id_aa64isar1_el1",
2322 "id_aa64mmfr0_el1",
2323 "id_aa64mmfr1_el1",
2324 "ccsidr_el1",
2325 "clidr_el1",
2326 "aidr_el1",
2327 "csselr_el1",
2328 "ctr_el0",
2329 "dczid_el0",
2330 "vpidr_el2",
2331 "vmpidr_el2",
2332 "sctlr_el1",
2333 "sctlr_el12",
2334 "sctlr2_el1",
2335 "sctlr2_el12",
2336 "actlr_el1",
2337 "cpacr_el1",
2338 "cpacr_el12",
2339 "sctlr_el2",
2340 "sctlr2_el2",
2341 "actlr_el2",
2342 "hcr_el2",
2343 "hcrx_el2",
2344 "mdcr_el2",
2345 "cptr_el2",
2346 "hstr_el2",
2347 "hacr_el2",
2348 "sctlr_el3",
2349 "sctlr2_el3",
2350 "actlr_el3",
2351 "scr_el3",
2352 "sder32_el3",
2353 "cptr_el3",
2354 "mdcr_el3",
2355 "ttbr0_el1",
2356 "ttbr0_el12",
2357 "ttbr1_el1",
2358 "ttbr1_el12",
2359 "tcr_el1",
2360 "tcr_el12",
2361 "tcr2_el1",
2362 "tcr2_el12",
2363 "ttbr0_el2",
2364 "tcr_el2",
2365 "tcr2_el2",
2366 "vttbr_el2",
2367 "vtcr_el2",
2368 "vsttbr_el2",
2369 "vstcr_el2",
2370 "ttbr0_el3",
2371 "tcr_el3",
2372 "dacr32_el2",
2373 "spsr_el1",
2374 "spsr_el12",
2375 "elr_el1",
2376 "elr_el12",
2377 "sp_el0",
2378 "spsel",
2379 "currentel",
2380 "nzcv",
2381 "daif",
2382 "fpcr",
2383 "fpsr",
2384 "dspsr_el0",
2385 "dlr_el0",
2386 "spsr_el2",
2387 "elr_el2",
2388 "sp_el1",
2389 "spsr_irq_aa64",
2390 "spsr_abt_aa64",
2391 "spsr_und_aa64",
2392 "spsr_fiq_aa64",
2393 "spsr_el3",
2394 "elr_el3",
2395 "sp_el2",
2396 "afsr0_el1",
2397 "afsr0_el12",
2398 "afsr1_el1",
2399 "afsr1_el12",
2400 "esr_el1",
2401 "esr_el12",
2402 "ifsr32_el2",
2403 "afsr0_el2",
2404 "afsr1_el2",
2405 "esr_el2",
2406 "fpexc32_el2",
2407 "afsr0_el3",
2408 "afsr1_el3",
2409 "esr_el3",
2410 "far_el1",
2411 "far_el12",
2412 "far_el2",
2413 "hpfar_el2",
2414 "far_el3",
2415 "ic_ialluis",
2416 "par_el1",
2417 "ic_iallu",
2418 "dc_ivac_xt",
2419 "dc_isw_xt",
2420 "at_s1e1r_xt",
2421 "at_s1e1w_xt",
2422 "at_s1e0r_xt",
2423 "at_s1e0w_xt",
2424 "dc_csw_xt",
2425 "dc_cisw_xt",
2426 "dc_zva_xt",
2427 "ic_ivau_xt",
2428 "dc_cvac_xt",
2429 "dc_cvau_xt",
2430 "dc_civac_xt",
2431 "at_s1e2r_xt",
2432 "at_s1e2w_xt",
2433 "at_s12e1r_xt",
2434 "at_s12e1w_xt",
2435 "at_s12e0r_xt",
2436 "at_s12e0w_xt",
2437 "at_s1e3r_xt",
2438 "at_s1e3w_xt",
2439 "tlbi_vmalle1is",
2440 "tlbi_vmalle1os",
2441 "tlbi_vae1is",
2442 "tlbi_vae1os",
2443 "lbi_aside1is_xt",
2444 "tlbi_aside1os",
2445 "tlbi_vaae1is",
2446 "tlbi_vaae1os",
2447 "tlbi_vale1is",
2448 "tlbi_vale1os",
2449 "tlbi_vaale1is",
2450 "tlbi_vaale1os",
2451 "tlbi_vmalle1",
2452 "tlbi_vae1",
2453 "tlbi_aside1",
2454 "tlbi_vaae1",
2455 "tlbi_vale1",
2456 "tlbi_vaale1",
2457 "tlbi_ipas2e1is",
2458 "tlbi_ipas2e1os",
2459 "tlbi_ipas2le1is",
2460 "tlbi_ipas2le1os",
2461 "tlbi_alle2is",
2462 "tlbi_alle2os",
2463 "tlbi_vae2is",
2464 "tlbi_vae2os",
2465 "tlbi_alle1is",
2466 "tlbi_alle1os",
2467 "tlbi_vale2is",
2468 "tlbi_vale2os",
2469 "tlbi_vmalls12e1is",
2470 "tlbi_vmalls12e1os",
2471 "tlbi_ipas2e1",
2472 "tlbi_ipas2le1",
2473 "tlbi_alle2",
2474 "tlbi_vae2",
2475 "tlbi_alle1",
2476 "tlbi_vale2",
2477 "tlbi_vmalls12e1",
2478 "tlbi_alle3is",
2479 "tlbi_alle3os",
2480 "tlbi_vae3is",
2481 "tlbi_vae3os",
2482 "tlbi_vale3is",
2483 "tlbi_vale3os",
2484 "tlbi_alle3",
2485 "tlbi_vae3",
2486 "tlbi_vale3",
2487 "tlbi_rvae1",
2488 "tlbi_rvaae1",
2489 "tlbi_rvale1",
2490 "tlbi_rvaale1",
2491 "tlbi_ripas2e1",
2492 "tlbi_ripas2le1",
2493 "tlbi_rvae2",
2494 "tlbi_rvale2",
2495 "tlbi_rvae3",
2496 "tlbi_rvale3",
2497 "tlbi_rvae1is",
2498 "tlbi_rvaae1is",
2499 "tlbi_rvale1is",
2500 "tlbi_rvaale1is",
2501 "tlbi_ripas2e1is",
2502 "tlbi_ripas2le1is",
2503 "tlbi_rvae2is",
2504 "tlbi_rvale2is",
2505 "tlbi_rvae3is",
2506 "tlbi_rvale3is",
2507 "tlbi_rvae1os",
2508 "tlbi_rvaae1os",
2509 "tlbi_rvale1os",
2510 "tlbi_rvaale1os",
2511 "tlbi_ripas2e1os",
2512 "tlbi_ripas2le1os",
2513 "tlbi_rvae2os",
2514 "tlbi_rvale2os",
2515 "tlbi_rvae3os",
2516 "tlbi_rvale3os",
2517 "pmintenset_el1",
2518 "pmintenclr_el1",
2519 "pmcr_el0",
2520 "pmcntenset_el0",
2521 "pmcntenclr_el0",
2522 "pmovsclr_el0",
2523 "pmswinc_el0",
2524 "pmselr_el0",
2525 "pmceid0_el0",
2526 "pmceid1_el0",
2527 "pmccntr_el0",
2528 "pmxevtyper_el0",
2529 "pmccfiltr_el0",
2530 "pmxevcntr_el0",
2531 "pmuserenr_el0",
2532 "pmovsset_el0",
2533 "mair_el1",
2534 "mair_el12",
2535 "amair_el1",
2536 "amair_el12",
2537 "mair_el2",
2538 "amair_el2",
2539 "mair_el3",
2540 "amair_el3",
2541 "l2ctlr_el1",
2542 "l2ectlr_el1",
2543 "vbar_el1",
2544 "vbar_el12",
2545 "rvbar_el1",
2546 "isr_el1",
2547 "vbar_el2",
2548 "rvbar_el2",
2549 "vbar_el3",
2550 "rvbar_el3",
2551 "rmr_el3",
2552 "contextidr_el1",
2553 "contextidr_el12",
2554 "tpidr_el1",
2555 "tpidr_el0",
2556 "tpidrro_el0",
2557 "tpidr_el2",
2558 "tpidr_el3",
2559 "cntfrq_el0",
2560 "cntpct_el0",
2561 "cntvct_el0",
2562 "cntp_ctl_el0",
2563 "cntp_cval_el0",
2564 "cntp_tval_el0",
2565 "cntv_ctl_el0",
2566 "cntv_cval_el0",
2567 "cntv_tval_el0",
2568 "cntp_ctl_el02",
2569 "cntp_cval_el02",
2570 "cntp_tval_el02",
2571 "cntv_ctl_el02",
2572 "cntv_cval_el02",
2573 "cntv_tval_el02",
2574 "cntkctl_el1",
2575 "cntkctl_el12",
2576 "cntps_ctl_el1",
2577 "cntps_cval_el1",
2578 "cntps_tval_el1",
2579 "cnthctl_el2",
2580 "cnthp_ctl_el2",
2581 "cnthp_cval_el2",
2582 "cnthp_tval_el2",
2583 "cnthps_ctl_el2",
2584 "cnthps_cval_el2",
2585 "cnthps_tval_el2",
2586 "cnthv_ctl_el2",
2587 "cnthv_cval_el2",
2588 "cnthv_tval_el2",
2589 "cnthvs_ctl_el2",
2590 "cnthvs_cval_el2",
2591 "cnthvs_tval_el2",
2592 "cntvoff_el2",
2593 "pmevcntr0_el0",
2594 "pmevcntr1_el0",
2595 "pmevcntr2_el0",
2596 "pmevcntr3_el0",
2597 "pmevcntr4_el0",
2598 "pmevcntr5_el0",
2599 "pmevtyper0_el0",
2600 "pmevtyper1_el0",
2601 "pmevtyper2_el0",
2602 "pmevtyper3_el0",
2603 "pmevtyper4_el0",
2604 "pmevtyper5_el0",
2605 "il1data0_el1",
2606 "il1data1_el1",
2607 "il1data2_el1",
2608 "il1data3_el1",
2609 "dl1data0_el1",
2610 "dl1data1_el1",
2611 "dl1data2_el1",
2612 "dl1data3_el1",
2613 "dl1data4_el1",
2614 "l2actlr_el1",
2615 "cpuactlr_el1",
2616 "cpuectlr_el1",
2617 "cpumerrsr_el1",
2618 "l2merrsr_el1",
2619 "cbar_el1",
2620 "contextidr_el2",
2621
2622 "ttbr1_el2",
2623 "id_aa64mmfr2_el1",
2624 "id_aa64mmfr3_el1",
2625
2626 "apdakeyhi_el1",
2627 "apdakeylo_el1",
2628 "apdbkeyhi_el1",
2629 "apdbkeylo_el1",
2630 "apgakeyhi_el1",
2631 "apgakeylo_el1",
2632 "apiakeyhi_el1",
2633 "apiakeylo_el1",
2634 "apibkeyhi_el1",
2635 "apibkeylo_el1",
2636 // GICv3, CPU interface
2637 "icc_pmr_el1",
2638 "icc_iar0_el1",
2639 "icc_eoir0_el1",
2640 "icc_hppir0_el1",
2641 "icc_bpr0_el1",
2642 "icc_ap0r0_el1",
2643 "icc_ap0r1_el1",
2644 "icc_ap0r2_el1",
2645 "icc_ap0r3_el1",
2646 "icc_ap1r0_el1",
2647 "icc_ap1r0_el1_ns",
2648 "icc_ap1r0_el1_s",
2649 "icc_ap1r1_el1",
2650 "icc_ap1r1_el1_ns",
2651 "icc_ap1r1_el1_s",
2652 "icc_ap1r2_el1",
2653 "icc_ap1r2_el1_ns",
2654 "icc_ap1r2_el1_s",
2655 "icc_ap1r3_el1",
2656 "icc_ap1r3_el1_ns",
2657 "icc_ap1r3_el1_s",
2658 "icc_dir_el1",
2659 "icc_rpr_el1",
2660 "icc_sgi1r_el1",
2661 "icc_asgi1r_el1",
2662 "icc_sgi0r_el1",
2663 "icc_iar1_el1",
2664 "icc_eoir1_el1",
2665 "icc_hppir1_el1",
2666 "icc_bpr1_el1",
2667 "icc_bpr1_el1_ns",
2668 "icc_bpr1_el1_s",
2669 "icc_ctlr_el1",
2670 "icc_ctlr_el1_ns",
2671 "icc_ctlr_el1_s",
2672 "icc_sre_el1",
2673 "icc_sre_el1_ns",
2674 "icc_sre_el1_s",
2675 "icc_igrpen0_el1",
2676 "icc_igrpen1_el1",
2677 "icc_igrpen1_el1_ns",
2678 "icc_igrpen1_el1_s",
2679 "icc_sre_el2",
2680 "icc_ctlr_el3",
2681 "icc_sre_el3",
2682 "icc_igrpen1_el3",
2683
2684 // GICv3, CPU interface, virtualization
2685 "ich_ap0r0_el2",
2686 "ich_ap0r1_el2",
2687 "ich_ap0r2_el2",
2688 "ich_ap0r3_el2",
2689 "ich_ap1r0_el2",
2690 "ich_ap1r1_el2",
2691 "ich_ap1r2_el2",
2692 "ich_ap1r3_el2",
2693 "ich_hcr_el2",
2694 "ich_vtr_el2",
2695 "ich_misr_el2",
2696 "ich_eisr_el2",
2697 "ich_elrsr_el2",
2698 "ich_vmcr_el2",
2699 "ich_lr0_el2",
2700 "ich_lr1_el2",
2701 "ich_lr2_el2",
2702 "ich_lr3_el2",
2703 "ich_lr4_el2",
2704 "ich_lr5_el2",
2705 "ich_lr6_el2",
2706 "ich_lr7_el2",
2707 "ich_lr8_el2",
2708 "ich_lr9_el2",
2709 "ich_lr10_el2",
2710 "ich_lr11_el2",
2711 "ich_lr12_el2",
2712 "ich_lr13_el2",
2713 "ich_lr14_el2",
2714 "ich_lr15_el2",
2715
2716 "icv_pmr_el1",
2717 "icv_iar0_el1",
2718 "icv_eoir0_el1",
2719 "icv_hppir0_el1",
2720 "icv_bpr0_el1",
2721 "icv_ap0r0_el1",
2722 "icv_ap0r1_el1",
2723 "icv_ap0r2_el1",
2724 "icv_ap0r3_el1",
2725 "icv_ap1r0_el1",
2726 "icv_ap1r0_el1_ns",
2727 "icv_ap1r0_el1_s",
2728 "icv_ap1r1_el1",
2729 "icv_ap1r1_el1_ns",
2730 "icv_ap1r1_el1_s",
2731 "icv_ap1r2_el1",
2732 "icv_ap1r2_el1_ns",
2733 "icv_ap1r2_el1_s",
2734 "icv_ap1r3_el1",
2735 "icv_ap1r3_el1_ns",
2736 "icv_ap1r3_el1_s",
2737 "icv_dir_el1",
2738 "icv_rpr_el1",
2739 "icv_sgi1r_el1",
2740 "icv_asgi1r_el1",
2741 "icv_sgi0r_el1",
2742 "icv_iar1_el1",
2743 "icv_eoir1_el1",
2744 "icv_hppir1_el1",
2745 "icv_bpr1_el1",
2746 "icv_bpr1_el1_ns",
2747 "icv_bpr1_el1_s",
2748 "icv_ctlr_el1",
2749 "icv_ctlr_el1_ns",
2750 "icv_ctlr_el1_s",
2751 "icv_sre_el1",
2752 "icv_sre_el1_ns",
2753 "icv_sre_el1_s",
2754 "icv_igrpen0_el1",
2755 "icv_igrpen1_el1",
2756 "icv_igrpen1_el1_ns",
2757 "icv_igrpen1_el1_s",
2758
2759 "icc_ap0r0",
2760 "icc_ap0r1",
2761 "icc_ap0r2",
2762 "icc_ap0r3",
2763 "icc_ap1r0",
2764 "icc_ap1r0_ns",
2765 "icc_ap1r0_s",
2766 "icc_ap1r1",
2767 "icc_ap1r1_ns",
2768 "icc_ap1r1_s",
2769 "icc_ap1r2",
2770 "icc_ap1r2_ns",
2771 "icc_ap1r2_s",
2772 "icc_ap1r3",
2773 "icc_ap1r3_ns",
2774 "icc_ap1r3_s",
2775 "icc_asgi1r",
2776 "icc_bpr0",
2777 "icc_bpr1",
2778 "icc_bpr1_ns",
2779 "icc_bpr1_s",
2780 "icc_ctlr",
2781 "icc_ctlr_ns",
2782 "icc_ctlr_s",
2783 "icc_dir",
2784 "icc_eoir0",
2785 "icc_eoir1",
2786 "icc_hppir0",
2787 "icc_hppir1",
2788 "icc_hsre",
2789 "icc_iar0",
2790 "icc_iar1",
2791 "icc_igrpen0",
2792 "icc_igrpen1",
2793 "icc_igrpen1_ns",
2794 "icc_igrpen1_s",
2795 "icc_mctlr",
2796 "icc_mgrpen1",
2797 "icc_msre",
2798 "icc_pmr",
2799 "icc_rpr",
2800 "icc_sgi0r",
2801 "icc_sgi1r",
2802 "icc_sre",
2803 "icc_sre_ns",
2804 "icc_sre_s",
2805
2806 "ich_ap0r0",
2807 "ich_ap0r1",
2808 "ich_ap0r2",
2809 "ich_ap0r3",
2810 "ich_ap1r0",
2811 "ich_ap1r1",
2812 "ich_ap1r2",
2813 "ich_ap1r3",
2814 "ich_hcr",
2815 "ich_vtr",
2816 "ich_misr",
2817 "ich_eisr",
2818 "ich_elrsr",
2819 "ich_vmcr",
2820 "ich_lr0",
2821 "ich_lr1",
2822 "ich_lr2",
2823 "ich_lr3",
2824 "ich_lr4",
2825 "ich_lr5",
2826 "ich_lr6",
2827 "ich_lr7",
2828 "ich_lr8",
2829 "ich_lr9",
2830 "ich_lr10",
2831 "ich_lr11",
2832 "ich_lr12",
2833 "ich_lr13",
2834 "ich_lr14",
2835 "ich_lr15",
2836 "ich_lrc0",
2837 "ich_lrc1",
2838 "ich_lrc2",
2839 "ich_lrc3",
2840 "ich_lrc4",
2841 "ich_lrc5",
2842 "ich_lrc6",
2843 "ich_lrc7",
2844 "ich_lrc8",
2845 "ich_lrc9",
2846 "ich_lrc10",
2847 "ich_lrc11",
2848 "ich_lrc12",
2849 "ich_lrc13",
2850 "ich_lrc14",
2851 "ich_lrc15",
2852
2853 "id_aa64zfr0_el1",
2854 "zcr_el3",
2855 "zcr_el2",
2856 "zcr_el12",
2857 "zcr_el1",
2858
2859 "id_aa64smfr0_el1",
2860 "svcr",
2861 "smidr_el1",
2862 "smpri_el1",
2863 "smprimap_el2",
2864 "smcr_el3",
2865 "smcr_el2",
2866 "smcr_el12",
2867 "smcr_el1",
2868 "tpidr2_el0",
2869 "mpamsm_el1",
2870
2871 "rndr",
2872 "rndrrs",
2873
2874 "hfgitr_el2",
2875 "hfgrtr_el2",
2876 "hfgwtr_el2",
2877 "hdfgrtr_el2",
2878 "hdfgwtr_el2",
2879
2880 // FEAT_MPAM
2881 "mpamidr_el1",
2882 "mpam0_el1",
2883 "mpam1_el1",
2884 "mpam2_el2",
2885 "mpam3_el3",
2886 "mpam1_el12",
2887 "mpamhcr_el2",
2888 "mpamvpmv_el2",
2889 "mpamvpm0_el2",
2890 "mpamvpm1_el2",
2891 "mpamvpm2_el2",
2892 "mpamvpm3_el2",
2893 "mpamvpm4_el2",
2894 "mpamvpm5_el2",
2895 "mpamvpm6_el2",
2896 "mpamvpm7_el2",
2897
2898 "num_phys_regs",
2899
2900 // Dummy registers
2901 "nop",
2902 "raz",
2903 "unknown",
2904 "impl_defined",
2905 "erridr_el1",
2906 "errselr_el1",
2907 "erxfr_el1",
2908 "erxctlr_el1",
2909 "erxstatus_el1",
2910 "erxaddr_el1",
2911 "erxmisc0_el1",
2912 "erxmisc1_el1",
2913 "disr_el1",
2914 "vsesr_el2",
2915 "vdisr_el2",
2916
2917 // PSTATE
2918 "pan",
2919 "uao",
2920 };
2921
2922 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
2923 "The miscRegName array and NUM_MISCREGS are inconsistent.");
2924
2926 {
2927 public:
2928 std::string
2929 regName(const RegId &id) const override
2930 {
2931 return miscRegName[id.index()];
2932 }
2933 };
2934
2936
2937 inline constexpr RegClass miscRegClass =
2939 debug::MiscRegs).
2940 ops(miscRegClassOps);
2941
2942 // This mask selects bits of the CPSR that actually go in the CondCodes
2943 // integer register to allow renaming.
2944 static const uint32_t CondCodesMask = 0xF00F0000;
2945 static const uint32_t CpsrMaskQ = 0x08000000;
2946
2947 // APSR (Application Program Status Register Mask). It is the user level
2948 // alias for the CPSR. The APSR is a subset of the CPSR. Although
2949 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
2950 // APSR:
2951 // Bit[9] returns the value of CPSR.E.
2952 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
2953 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
2954
2955 // CPSR (Current Program Status Register Mask).
2956 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
2957
2958 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
2959 // integer register to allow renaming.
2960 static const uint32_t FpCondCodesMask = 0xF0000000;
2961 // This mask selects the cumulative saturation flag of the FPSCR.
2962 static const uint32_t FpscrQcMask = 0x08000000;
2963 // This mask selects the AHP bit of the FPSCR.
2964 static const uint32_t FpscrAhpMask = 0x04000000;
2965 // This mask selects the cumulative FP exception flags of the FPSCR.
2966 static const uint32_t FpscrExcMask = 0x0000009F;
2967
2982 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
2983 CPSR cpsr, ThreadContext *tc);
2984
2999 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
3000 CPSR cpsr, ThreadContext *tc);
3001
3002 // Checks for UNDEFINED behaviours when accessing AArch32
3003 // Generic Timer system registers
3005
3006 // Checks access permissions to AArch64 system registers
3008 ThreadContext *tc, const MiscRegOp64 &inst);
3009
3010 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
3011 // for MCR/MRC instructions
3012 int
3014
3015 // Flattens a misc reg index using the specified security state. This is
3016 // used for opperations (eg address translations) where the security
3017 // state of the register access may differ from the current state of the
3018 // processor
3019 int
3021
3022 int
3024
3025 // Takes a misc reg index and returns the root reg if its one of a set of
3026 // banked registers
3027 void
3029
3030 int
3031 unflattenMiscReg(int reg);
3032
3033} // namespace ArmISA
3034} // namespace gem5
3035
3036namespace std
3037{
3038template<>
3039struct hash<gem5::ArmISA::MiscRegNum32>
3040{
3041 size_t
3043 {
3044 return reg.packed();
3045 }
3046};
3047
3048template<>
3049struct hash<gem5::ArmISA::MiscRegNum64>
3050{
3051 size_t
3053 {
3054 return reg.packed();
3055 }
3056};
3057} // namespace std
3058
3059#endif // __ARCH_ARM_REGS_MISC_HH__
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Definition misc.hh:2929
Metadata table accessible via the value of the register.
Definition misc.hh:1300
chain userNonSecureWrite(bool v=true) const
Definition misc.hh:1401
const MiscRegLUTEntryInitializer & chain
Definition misc.hh:1302
chain userSecureWrite(bool v=true) const
Definition misc.hh:1413
chain warnNotFail(bool v=true) const
Definition misc.hh:1365
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition misc.hh:1305
chain fault(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1675
chain userSecureRead(bool v=true) const
Definition misc.hh:1407
chain implemented(bool v=true) const
Definition misc.hh:1342
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
Definition misc.hh:1686
chain highest(ArmSystem *const sys) const
Definition misc.cc:2831
chain secure(bool v=true) const
Definition misc.hh:1618
chain mutex(bool v=true) const
Definition misc.hh:1371
chain hypNonSecureWrite(bool v=true) const
Definition misc.hh:1505
chain priv(bool v=true) const
Definition misc.hh:1466
chain raz(uint64_t mask=(uint64_t) -1) const
Definition misc.hh:1330
chain hypSecureRead(bool v=true) const
Definition misc.hh:1480
chain monSecure(bool v=true) const
Definition misc.hh:1572
chain privSecure(bool v=true) const
Definition misc.hh:1459
chain privSecureRead(bool v=true) const
Definition misc.hh:1447
chain privNonSecure(bool v=true) const
Definition misc.hh:1440
chain hypSecureWrite(bool v=true) const
Definition misc.hh:1499
chain userNonSecureRead(bool v=true) const
Definition misc.hh:1395
chain nonSecure(bool v=true) const
Definition misc.hh:1605
chain privNonSecureRead(bool v=true) const
Definition misc.hh:1428
chain monNonSecureWrite(bool v=true) const
Definition misc.hh:1550
chain reset(uint64_t res_val) const
Definition misc.hh:1312
chain monNonSecureRead(bool v=true) const
Definition misc.hh:1544
chain monWrite(bool v=true) const
Definition misc.hh:1565
chain user(bool v=true) const
Definition misc.hh:1419
chain unverifiable(bool v=true) const
Definition misc.hh:1353
chain hypSecure(bool v=true) const
Definition misc.hh:1518
chain banked(bool v=true) const
Definition misc.hh:1377
chain privRead(bool v=true) const
Definition misc.hh:1473
chain hypRead(bool v=true) const
Definition misc.hh:1492
struct MiscRegLUTEntry & entry
Definition misc.hh:1301
chain banked64(bool v=true) const
Definition misc.hh:1383
chain fault(MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1681
chain res0(uint64_t mask) const
Definition misc.hh:1318
chain bankedChild(bool v=true) const
Definition misc.hh:1389
chain hypWrite(bool v=true) const
Definition misc.hh:1511
chain allPrivileges(bool v=true) const
Definition misc.hh:1586
chain monSecureRead(bool v=true) const
Definition misc.hh:1532
chain privSecureWrite(bool v=true) const
Definition misc.hh:1453
chain res1(uint64_t mask) const
Definition misc.hh:1324
chain faultRead(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1661
chain hypNonSecureRead(bool v=true) const
Definition misc.hh:1486
chain monNonSecure(bool v=true) const
Definition misc.hh:1579
chain monSecureWrite(bool v=true) const
Definition misc.hh:1538
chain rao(uint64_t mask=(uint64_t) -1) const
Definition misc.hh:1336
chain mon(bool v=true) const
Definition misc.hh:1556
chain privNonSecureWrite(bool v=true) const
Definition misc.hh:1434
chain unserialize(bool v=true) const
Definition misc.hh:1359
chain faultWrite(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1668
chain hyp(bool v=true) const
Definition misc.hh:1525
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition misc64.hh:158
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
ThreadContext is the external interface to all thread state for anything outside of the CPU.
STL vector class.
Definition stl.hh:37
Bitfield< 28 > v
Definition misc_types.hh:54
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:660
static const uint32_t FpscrQcMask
Definition misc.hh:2962
static MiscRegClassOps miscRegClassOps
Definition misc.hh:2935
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
bool aarch64SysRegReadOnly(MiscRegIndex miscReg)
static const uint32_t CpsrMask
Definition misc.hh:2956
static const uint32_t FpscrExcMask
Definition misc.hh:2966
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition misc.cc:2749
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition misc.cc:535
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:730
static const uint32_t ApsrMask
Definition misc.hh:2953
Bitfield< 7, 5 > opc2
Definition types.hh:106
static const uint32_t CpsrMaskQ
Definition misc.hh:2945
static const uint32_t FpCondCodesMask
Definition misc.hh:2960
Bitfield< 9 > e
Definition misc_types.hh:65
Bitfield< 0 > ns
void preUnflattenMiscReg()
Definition misc.cc:708
Bitfield< 22 > u
static const uint32_t FpscrAhpMask
Definition misc.hh:2964
@ MISCREG_TLBI_VAE3
Definition misc.hh:738
@ MISCREG_PMXEVTYPER_EL0
Definition misc.hh:781
@ MISCREG_ERXSTATUS_EL1
Definition misc.hh:1185
@ MISCREG_AMAIR_EL3
Definition misc.hh:793
@ MISCREG_DBGWVR1_EL1
Definition misc.hh:497
@ MISCREG_DBGDRAR
Definition misc.hh:176
@ MISCREG_NSACR
Definition misc.hh:251
@ MISCREG_DL1DATA1
Definition misc.hh:446
@ MISCREG_ID_AA64PFR0_EL1
Definition misc.hh:567
@ MISCREG_DBGWCR5
Definition misc.hh:165
@ MISCREG_ICH_VMCR
Definition misc.hh:1080
@ MISCREG_CSSELR_NS
Definition misc.hh:237
@ MISCREG_HSTR_EL2
Definition misc.hh:599
@ MISCREG_DBGWVR13_EL1
Definition misc.hh:509
@ MISCREG_PMUSERENR
Definition misc.hh:369
@ MISCREG_DBGBCR15
Definition misc.hh:143
@ MISCREG_TLBI_VALE2OS
Definition misc.hh:721
@ MISCREG_DBGOSLSR
Definition misc.hh:194
@ MISCREG_DBGDTRRXext
Definition misc.hh:108
@ MISCREG_ID_MMFR2_EL1
Definition misc.hh:554
@ MISCREG_TTBR1_EL12
Definition misc.hh:611
@ MISCREG_DCCISW
Definition misc.hh:324
@ MISCREG_ERRIDR_EL1
Definition misc.hh:1181
@ MISCREG_DACR_S
Definition misc.hh:273
@ MISCREG_CNTV_CTL_EL0
Definition misc.hh:819
@ MISCREG_ICH_LR7
Definition misc.hh:1088
@ MISCREG_DBGWCR8
Definition misc.hh:168
@ MISCREG_HCR
Definition misc.hh:254
@ MISCREG_ICC_BPR1_EL1_NS
Definition misc.hh:928
@ MISCREG_NMRR_NS
Definition misc.hh:382
@ MISCREG_CPSR_MODE
Definition misc.hh:84
@ MISCREG_TLBI_RVALE2IS
Definition misc.hh:757
@ MISCREG_PRRR_MAIR0
Definition misc.hh:90
@ MISCREG_TLBI_ALLE3
Definition misc.hh:737
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition misc.hh:938
@ MISCREG_TLBI_ALLE1IS
Definition misc.hh:718
@ MISCREG_ICV_BPR0_EL1
Definition misc.hh:981
@ MISCREG_ICH_AP0R2_EL2
Definition misc.hh:948
@ MISCREG_VSTCR_EL2
Definition misc.hh:622
@ MISCREG_DBGWVR14
Definition misc.hh:158
@ MISCREG_TLBI_VMALLE1OS
Definition misc.hh:693
@ MISCREG_HDFAR
Definition misc.hh:295
@ MISCREG_MPIDR_EL1
Definition misc.hh:546
@ MISCREG_ICC_IGRPEN1
Definition misc.hh:1053
@ MISCREG_DFSR_S
Definition misc.hh:276
@ MISCREG_IL1DATA1
Definition misc.hh:442
@ MISCREG_DBGWVR10_EL1
Definition misc.hh:506
@ MISCREG_DL1DATA0
Definition misc.hh:445
@ MISCREG_TLBI_RVAE1IS
Definition misc.hh:750
@ MISCREG_CPUECTLR_EL1
Definition misc.hh:873
@ MISCREG_ATS1HR
Definition misc.hh:325
@ MISCREG_ERXCTLR_EL1
Definition misc.hh:1184
@ MISCREG_SCTLR_EL2
Definition misc.hh:592
@ MISCREG_PMSELR_EL0
Definition misc.hh:777
@ MISCREG_TLBI_ALLE2OS
Definition misc.hh:715
@ MISCREG_ID_DFR0_EL1
Definition misc.hh:550
@ MISCREG_CNTV_CVAL_EL02
Definition misc.hh:826
@ MISCREG_CP15ISB
Definition misc.hh:305
@ MISCREG_CNTP_CTL_EL0
Definition misc.hh:816
@ MISCREG_DFAR_NS
Definition misc.hh:290
@ MISCREG_DBGBXVR8
Definition misc.hh:185
@ MISCREG_TLBIMVALIS
Definition misc.hh:331
@ MISCREG_PMOVSSET
Definition misc.hh:372
@ MISCREG_FPEXC
Definition misc.hh:81
@ MISCREG_DBGWCR1
Definition misc.hh:161
@ MISCREG_MPAMVPM2_EL2
Definition misc.hh:1156
@ MISCREG_NMRR_MAIR1_S
Definition misc.hh:95
@ MISCREG_ICH_LR7_EL2
Definition misc.hh:967
@ MISCREG_CNTP_CTL_EL02
Definition misc.hh:822
@ MISCREG_ICC_IAR1_EL1
Definition misc.hh:924
@ MISCREG_TLBI_VALE2IS
Definition misc.hh:720
@ MISCREG_SPSEL
Definition misc.hh:631
@ MISCREG_TLBI_VAALE1OS
Definition misc.hh:703
@ MISCREG_TCR_EL2
Definition misc.hh:617
@ MISCREG_AT_S1E1W_Xt
Definition misc.hh:674
@ MISCREG_ID_ISAR0_EL1
Definition misc.hh:557
@ MISCREG_DBGWCR5_EL1
Definition misc.hh:517
@ MISCREG_RNDRRS
Definition misc.hh:1136
@ MISCREG_TLBI_ASIDE1
Definition misc.hh:706
@ MISCREG_DBGWVR2
Definition misc.hh:146
@ MISCREG_ICH_LR6_EL2
Definition misc.hh:966
@ MISCREG_TLBI_RVAE3IS
Definition misc.hh:758
@ MISCREG_TLBI_RVAE3OS
Definition misc.hh:768
@ MISCREG_ICH_AP1R1
Definition misc.hh:1072
@ MISCREG_DBGDSCRint
Definition misc.hh:102
@ MISCREG_TLBI_IPAS2E1IS
Definition misc.hh:710
@ MISCREG_MVFR1
Definition misc.hh:79
@ MISCREG_IL1DATA0_EL1
Definition misc.hh:862
@ MISCREG_MIDR_EL1
Definition misc.hh:545
@ MISCREG_TLBI_RIPAS2E1
Definition misc.hh:744
@ MISCREG_SDER
Definition misc.hh:250
@ MISCREG_DBGWCR12_EL1
Definition misc.hh:524
@ MISCREG_OSDLR_EL1
Definition misc.hh:536
@ MISCREG_ICV_RPR_EL1
Definition misc.hh:999
@ MISCREG_ICV_IGRPEN1_EL1_S
Definition misc.hh:1018
@ MISCREG_DL1DATA3
Definition misc.hh:448
@ MISCREG_HTPIDR
Definition misc.hh:417
@ MISCREG_DBGBXVR15
Definition misc.hh:192
@ MISCREG_TLBIMVAALIS
Definition misc.hh:332
@ MISCREG_ICV_AP1R2_EL1
Definition misc.hh:992
@ MISCREG_ICV_AP0R3_EL1
Definition misc.hh:985
@ MISCREG_TLBI_RVALE3IS
Definition misc.hh:759
@ MISCREG_ICC_MGRPEN1
Definition misc.hh:1057
@ MISCREG_ZCR_EL2
Definition misc.hh:1117
@ MISCREG_ICC_IGRPEN1_EL3
Definition misc.hh:943
@ MISCREG_SPSR_HYP
Definition misc.hh:74
@ MISCREG_ID_AA64ZFR0_EL1
Definition misc.hh:1115
@ MISCREG_MPAMVPM7_EL2
Definition misc.hh:1161
@ MISCREG_TLBI_VAE3OS
Definition misc.hh:734
@ MISCREG_TLBI_RVAAE1
Definition misc.hh:741
@ MISCREG_DBGDEVID0
Definition misc.hh:203
@ MISCREG_TLBI_IPAS2E1OS
Definition misc.hh:711
@ MISCREG_CNTFRQ
Definition misc.hh:419
@ MISCREG_DBGDSAR
Definition misc.hh:197
@ MISCREG_AFSR1_EL12
Definition misc.hh:652
@ MISCREG_CPUMERRSR
Definition misc.hh:455
@ MISCREG_CPSR_Q
Definition misc.hh:85
@ MISCREG_DBGBVR5_EL1
Definition misc.hh:469
@ MISCREG_MAIR_EL1
Definition misc.hh:786
@ MISCREG_ICV_AP1R1_EL1_NS
Definition misc.hh:990
@ MISCREG_DBGBCR2_EL1
Definition misc.hh:482
@ MISCREG_ID_ISAR2_EL1
Definition misc.hh:559
@ MISCREG_TLBIMVAAL
Definition misc.hh:344
@ MISCREG_DBGBVR1_EL1
Definition misc.hh:465
@ MISCREG_PAR_NS
Definition misc.hh:301
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition misc.hh:939
@ MISCREG_HAMAIR1
Definition misc.hh:396
@ MISCREG_PMXEVCNTR_EL0
Definition misc.hh:783
@ MISCREG_ICC_IGRPEN1_NS
Definition misc.hh:1054
@ MISCREG_ICC_PMR_EL1
Definition misc.hh:898
@ MISCREG_CONTEXTIDR_EL1
Definition misc.hh:805
@ MISCREG_CNTV_TVAL
Definition misc.hh:433
@ MISCREG_VBAR_EL3
Definition misc.hh:802
@ MISCREG_ICV_CTLR_EL1
Definition misc.hh:1009
@ MISCREG_AIFSR_NS
Definition misc.hh:284
@ MISCREG_DBGWCR10
Definition misc.hh:170
@ MISCREG_DBGBXVR9
Definition misc.hh:186
@ MISCREG_ICC_CTLR_NS
Definition misc.hh:1042
@ MISCREG_CNTPS_TVAL_EL1
Definition misc.hh:832
@ MISCREG_ICC_AP1R3
Definition misc.hh:1033
@ MISCREG_ICC_MCTLR
Definition misc.hh:1056
@ MISCREG_HCPTR
Definition misc.hh:257
@ MISCREG_ICV_AP1R2_EL1_S
Definition misc.hh:994
@ MISCREG_SPSR_EL2
Definition misc.hh:639
@ MISCREG_ICH_LR8
Definition misc.hh:1089
@ MISCREG_ICV_AP0R0_EL1
Definition misc.hh:982
@ MISCREG_MPAMVPM4_EL2
Definition misc.hh:1158
@ MISCREG_ICC_AP1R0_EL1
Definition misc.hh:907
@ MISCREG_TLBI_IPAS2LE1IS
Definition misc.hh:712
@ MISCREG_ICC_BPR0_EL1
Definition misc.hh:902
@ MISCREG_DBGWFAR
Definition misc.hh:106
@ MISCREG_IFAR
Definition misc.hh:292
@ MISCREG_TLBI_ALLE1
Definition misc.hh:728
@ MISCREG_FCSEIDR
Definition misc.hh:404
@ MISCREG_DBGWVR7
Definition misc.hh:151
@ MISCREG_TLBI_RVALE1
Definition misc.hh:742
@ MISCREG_ID_MMFR1
Definition misc.hh:222
@ MISCREG_AT_S1E2W_Xt
Definition misc.hh:685
@ MISCREG_PMEVTYPER1_EL0
Definition misc.hh:857
@ MISCREG_LOCKFLAG
Definition misc.hh:89
@ MISCREG_ICH_LR15_EL2
Definition misc.hh:975
@ MISCREG_FPSID
Definition misc.hh:77
@ MISCREG_MPAM3_EL3
Definition misc.hh:1150
@ MISCREG_DBGBXVR12
Definition misc.hh:189
@ MISCREG_ICH_MISR
Definition misc.hh:1077
@ MISCREG_DBGWCR6_EL1
Definition misc.hh:518
@ MISCREG_ID_AFR0_EL1
Definition misc.hh:551
@ MISCREG_DBGBVR2
Definition misc.hh:114
@ MISCREG_TLBI_RVALE3OS
Definition misc.hh:769
@ MISCREG_MAIR_EL12
Definition misc.hh:787
@ MISCREG_ICV_IGRPEN1_EL1_NS
Definition misc.hh:1017
@ MISCREG_DBGBVR7_EL1
Definition misc.hh:471
@ MISCREG_ICH_LRC0
Definition misc.hh:1097
@ MISCREG_SMIDR_EL1
Definition misc.hh:1124
@ MISCREG_TLBI_VMALLS12E1OS
Definition misc.hh:723
@ MISCREG_SCTLR
Definition misc.hh:241
@ MISCREG_PAR_EL1
Definition misc.hh:669
@ MISCREG_TTBCR
Definition misc.hh:266
@ MISCREG_DBGWVR3_EL1
Definition misc.hh:499
@ MISCREG_ICH_LR5
Definition misc.hh:1086
@ MISCREG_AT_S12E1W_Xt
Definition misc.hh:687
@ MISCREG_TLBIIPAS2
Definition misc.hh:351
@ MISCREG_ICV_EOIR1_EL1
Definition misc.hh:1004
@ MISCREG_ATS12NSOUW
Definition misc.hh:317
@ MISCREG_MAIR_EL2
Definition misc.hh:790
@ MISCREG_ICV_IGRPEN0_EL1
Definition misc.hh:1015
@ MISCREG_CNTV_CVAL
Definition misc.hh:432
@ MISCREG_APDBKeyLo_EL1
Definition misc.hh:889
@ MISCREG_MDRAR_EL1
Definition misc.hh:533
@ MISCREG_CSSELR
Definition misc.hh:236
@ MISCREG_CPACR
Definition misc.hh:247
@ MISCREG_HAMAIR0
Definition misc.hh:395
@ MISCREG_TLBIIPAS2L
Definition misc.hh:352
@ MISCREG_ICC_BPR1_S
Definition misc.hh:1040
@ MISCREG_DBGBVR8
Definition misc.hh:120
@ MISCREG_ADFSR_S
Definition misc.hh:282
@ MISCREG_ICH_LRC11
Definition misc.hh:1108
@ MISCREG_SCR_EL3
Definition misc.hh:604
@ MISCREG_TTBR0_S
Definition misc.hh:262
@ MISCREG_TLBIALLHIS
Definition misc.hh:347
@ MISCREG_IL1DATA1_EL1
Definition misc.hh:863
@ MISCREG_CNTKCTL_EL12
Definition misc.hh:829
@ MISCREG_APDAKeyHi_EL1
Definition misc.hh:886
@ MISCREG_TLBIIPAS2LIS
Definition misc.hh:346
@ MISCREG_TLBIASIDIS
Definition misc.hh:329
@ MISCREG_ID_AA64DFR0_EL1
Definition misc.hh:569
@ MISCREG_ID_ISAR6
Definition misc.hh:232
@ MISCREG_DBGCLAIMCLR
Definition misc.hh:199
@ MISCREG_TPIDRRO_EL0
Definition misc.hh:809
@ MISCREG_DBGBVR3
Definition misc.hh:115
@ MISCREG_DBGWVR5_EL1
Definition misc.hh:501
@ MISCREG_DBGOSLAR
Definition misc.hh:193
@ MISCREG_PMEVTYPER3_EL0
Definition misc.hh:859
@ MISCREG_ICC_SRE_EL1_NS
Definition misc.hh:934
@ MISCREG_DBGBCR10
Definition misc.hh:138
@ MISCREG_SPSR_SVC
Definition misc.hh:71
@ MISCREG_REVIDR_EL1
Definition misc.hh:547
@ MISCREG_DBGDSCRext
Definition misc.hh:109
@ MISCREG_SCTLR2_EL12
Definition misc.hh:588
@ MISCREG_SCTLR2_EL1
Definition misc.hh:587
@ MISCREG_TLBI_VAE2
Definition misc.hh:727
@ MISCREG_TCR_EL3
Definition misc.hh:624
@ MISCREG_SCTLR2_EL3
Definition misc.hh:602
@ MISCREG_SMCR_EL1
Definition misc.hh:1130
@ MISCREG_FPSR
Definition misc.hh:636
@ MISCREG_TLBI_RVALE3
Definition misc.hh:749
@ MISCREG_DBGDIDR
Definition misc.hh:101
@ MISCREG_DBGBVR9_EL1
Definition misc.hh:473
@ MISCREG_ICH_HCR_EL2
Definition misc.hh:954
@ MISCREG_CPACR_EL12
Definition misc.hh:591
@ MISCREG_HDCR
Definition misc.hh:256
@ MISCREG_AIFSR_S
Definition misc.hh:285
@ MISCREG_ESR_EL1
Definition misc.hh:653
@ MISCREG_DISR_EL1
Definition misc.hh:1189
@ MISCREG_ADFSR
Definition misc.hh:280
@ MISCREG_ICC_AP1R3_EL1_NS
Definition misc.hh:917
@ MISCREG_PMCCNTR_EL0
Definition misc.hh:780
@ MISCREG_CNTP_TVAL
Definition misc.hh:428
@ MISCREG_MDCCSR_EL0
Definition misc.hh:528
@ MISCREG_ICV_AP1R3_EL1_S
Definition misc.hh:997
@ MISCREG_DTLBIMVA
Definition misc.hh:337
@ MISCREG_SPSR_UND_AA64
Definition misc.hh:644
@ MISCREG_TLBI_IPAS2E1
Definition misc.hh:724
@ MISCREG_DBGWVR13
Definition misc.hh:157
@ MISCREG_TLBI_RVAE1OS
Definition misc.hh:760
@ MISCREG_TLBI_VALE3
Definition misc.hh:739
@ MISCREG_AT_S12E0W_Xt
Definition misc.hh:689
@ MISCREG_DBGBXVR4
Definition misc.hh:181
@ MISCREG_TCR_EL1
Definition misc.hh:612
@ MISCREG_PMINTENSET
Definition misc.hh:370
@ MISCREG_TTBCR_NS
Definition misc.hh:267
@ MISCREG_PMXEVTYPER
Definition misc.hh:366
@ MISCREG_DBGBCR13_EL1
Definition misc.hh:493
@ MISCREG_TPIDR_EL3
Definition misc.hh:811
@ MISCREG_DBGBVR11
Definition misc.hh:123
@ MISCREG_HFGRTR_EL2
Definition misc.hh:1140
@ MISCREG_ICC_AP0R3
Definition misc.hh:1023
@ MISCREG_VMPIDR
Definition misc.hh:240
@ MISCREG_TPIDRURW_S
Definition misc.hh:410
@ MISCREG_CCSIDR_EL1
Definition misc.hh:577
@ MISCREG_DBGBXVR5
Definition misc.hh:182
@ MISCREG_CNTVCT
Definition misc.hh:421
@ MISCREG_ESR_EL12
Definition misc.hh:654
@ MISCREG_TLBIMVALH
Definition misc.hh:356
@ MISCREG_DL1DATA1_EL1
Definition misc.hh:867
@ MISCREG_ICC_AP1R0_EL1_S
Definition misc.hh:909
@ MISCREG_DBGWCR8_EL1
Definition misc.hh:520
@ MISCREG_ICC_IGRPEN1_S
Definition misc.hh:1055
@ MISCREG_AFSR0_EL1
Definition misc.hh:649
@ MISCREG_ICC_AP1R0_S
Definition misc.hh:1026
@ MISCREG_SPSR_UND
Definition misc.hh:75
@ MISCREG_TLBI_VAAE1OS
Definition misc.hh:699
@ MISCREG_TCMTR
Definition misc.hh:213
@ MISCREG_DBGWCR13_EL1
Definition misc.hh:525
@ MISCREG_DBGOSDLR
Definition misc.hh:195
@ MISCREG_DBGBXVR3
Definition misc.hh:180
@ MISCREG_DBGWCR11_EL1
Definition misc.hh:523
@ MISCREG_DBGWVR11_EL1
Definition misc.hh:507
@ MISCREG_TLBI_ALLE2IS
Definition misc.hh:714
@ MISCREG_TLBI_ALLE1OS
Definition misc.hh:719
@ MISCREG_SPSR_IRQ
Definition misc.hh:70
@ MISCREG_ID_ISAR5
Definition misc.hh:231
@ MISCREG_BPIALL
Definition misc.hh:306
@ MISCREG_DBGBVR10_EL1
Definition misc.hh:474
@ MISCREG_ID_ISAR3_EL1
Definition misc.hh:560
@ MISCREG_PMEVTYPER4_EL0
Definition misc.hh:860
@ MISCREG_ATS1CUR
Definition misc.hh:312
@ MISCREG_ICH_ELRSR_EL2
Definition misc.hh:958
@ MISCREG_DC_CVAC_Xt
Definition misc.hh:681
@ MISCREG_VPIDR_EL2
Definition misc.hh:583
@ MISCREG_DBGWCR2
Definition misc.hh:162
@ MISCREG_OSLAR_EL1
Definition misc.hh:534
@ MISCREG_CNTPCT_EL0
Definition misc.hh:814
@ MISCREG_DBGWCR4_EL1
Definition misc.hh:516
@ MISCREG_ERXADDR_EL1
Definition misc.hh:1186
@ MISCREG_TLBI_RVAALE1OS
Definition misc.hh:763
@ MISCREG_AMAIR0_NS
Definition misc.hh:388
@ MISCREG_DBGBCR14_EL1
Definition misc.hh:494
@ MISCREG_ICH_AP1R3
Definition misc.hh:1074
@ MISCREG_MPAM1_EL1
Definition misc.hh:1148
@ MISCREG_SPSR_ABT
Definition misc.hh:73
@ MISCREG_DBGWVR0_EL1
Definition misc.hh:496
@ MISCREG_AFSR1_EL2
Definition misc.hh:657
@ MISCREG_CNTV_CTL_EL02
Definition misc.hh:825
@ MISCREG_CP15DMB
Definition misc.hh:321
@ MISCREG_DBGBCR0_EL1
Definition misc.hh:480
@ MISCREG_SCTLR2_EL2
Definition misc.hh:593
@ MISCREG_DBGWVR15
Definition misc.hh:159
@ MISCREG_TLBIMVA
Definition misc.hh:340
@ MISCREG_PMEVCNTR4_EL0
Definition misc.hh:854
@ MISCREG_CONTEXTIDR_NS
Definition misc.hh:406
@ MISCREG_ICH_AP1R3_EL2
Definition misc.hh:953
@ MISCREG_DBGBCR6_EL1
Definition misc.hh:486
@ MISCREG_HFGITR_EL2
Definition misc.hh:1139
@ MISCREG_ID_ISAR4
Definition misc.hh:230
@ MISCREG_DBGBCR3_EL1
Definition misc.hh:483
@ MISCREG_TLBI_VAAE1IS
Definition misc.hh:698
@ MISCREG_ICC_AP1R1_EL1_S
Definition misc.hh:912
@ MISCREG_SCTLR_EL1
Definition misc.hh:585
@ MISCREG_CNTP_TVAL_EL02
Definition misc.hh:824
@ MISCREG_ICH_AP0R3
Definition misc.hh:1070
@ MISCREG_DBGWVR4_EL1
Definition misc.hh:500
@ MISCREG_TPIDRPRW_NS
Definition misc.hh:415
@ MISCREG_AIDR_EL1
Definition misc.hh:579
@ MISCREG_DC_CIVAC_Xt
Definition misc.hh:683
@ MISCREG_DBGDEVID1
Definition misc.hh:202
@ MISCREG_TLBI_ASIDE1OS
Definition misc.hh:697
@ MISCREG_PRRR
Definition misc.hh:375
@ MISCREG_ICC_IGRPEN0
Definition misc.hh:1052
@ MISCREG_ICH_LRC7
Definition misc.hh:1104
@ MISCREG_TEECR
Definition misc.hh:204
@ MISCREG_DC_CVAU_Xt
Definition misc.hh:682
@ MISCREG_DBGBXVR7
Definition misc.hh:184
@ MISCREG_AMAIR1_S
Definition misc.hh:392
@ MISCREG_DBGWVR7_EL1
Definition misc.hh:503
@ MISCREG_DBGBVR9
Definition misc.hh:121
@ MISCREG_PMEVTYPER0_EL0
Definition misc.hh:856
@ MISCREG_ICH_LRC8
Definition misc.hh:1105
@ MISCREG_TLBI_VAE2OS
Definition misc.hh:717
@ MISCREG_CPTR_EL2
Definition misc.hh:598
@ MISCREG_ICH_LR9_EL2
Definition misc.hh:969
@ MISCREG_DBGBCR8_EL1
Definition misc.hh:488
@ MISCREG_CCSIDR
Definition misc.hh:233
@ MISCREG_ICV_SRE_EL1_NS
Definition misc.hh:1013
@ MISCREG_FAR_EL1
Definition misc.hh:663
@ MISCREG_ERXMISC0_EL1
Definition misc.hh:1187
@ MISCREG_TLBI_IPAS2LE1
Definition misc.hh:725
@ MISCREG_TPIDR_EL1
Definition misc.hh:807
@ MISCREG_PMUSERENR_EL0
Definition misc.hh:784
@ MISCREG_APIAKeyLo_EL1
Definition misc.hh:893
@ MISCREG_DBGWCR0
Definition misc.hh:160
@ MISCREG_AT_S1E2R_Xt
Definition misc.hh:684
@ MISCREG_PMCR
Definition misc.hh:357
@ MISCREG_CNTHV_CTL_EL2
Definition misc.hh:841
@ MISCREG_TLBI_VAALE1
Definition misc.hh:709
@ MISCREG_ICC_DIR
Definition misc.hh:1044
@ MISCREG_CNTP_TVAL_NS
Definition misc.hh:429
@ MISCREG_TLBI_RVAE2OS
Definition misc.hh:766
@ MISCREG_CNTV_CTL
Definition misc.hh:431
@ MISCREG_AFSR1_EL3
Definition misc.hh:661
@ MISCREG_ADFSR_NS
Definition misc.hh:281
@ MISCREG_APIBKeyLo_EL1
Definition misc.hh:895
@ MISCREG_DFAR
Definition misc.hh:289
@ MISCREG_ICV_CTLR_EL1_NS
Definition misc.hh:1010
@ MISCREG_ID_AA64DFR1_EL1
Definition misc.hh:570
@ MISCREG_DC_CSW_Xt
Definition misc.hh:677
@ MISCREG_JMCR
Definition misc.hh:208
@ MISCREG_RMR_EL3
Definition misc.hh:804
@ MISCREG_ID_AA64ISAR1_EL1
Definition misc.hh:574
@ MISCREG_TLBIMVAL
Definition misc.hh:343
@ MISCREG_SMCR_EL3
Definition misc.hh:1127
@ MISCREG_ELR_EL12
Definition misc.hh:629
@ MISCREG_DL1DATA2_EL1
Definition misc.hh:868
@ MISCREG_DBGBVR0
Definition misc.hh:112
@ MISCREG_ICC_HSRE
Definition misc.hh:1049
@ MISCREG_ICH_LR1
Definition misc.hh:1082
@ MISCREG_PMEVCNTR0_EL0
Definition misc.hh:850
@ MISCREG_TEECR32_EL1
Definition misc.hh:541
@ MISCREG_AFSR0_EL3
Definition misc.hh:660
@ MISCREG_CSSELR_EL1
Definition misc.hh:580
@ MISCREG_VBAR_EL12
Definition misc.hh:797
@ MISCREG_MAIR_EL3
Definition misc.hh:792
@ MISCREG_ITLBIALL
Definition misc.hh:333
@ MISCREG_L2MERRSR
Definition misc.hh:456
@ MISCREG_ID_AA64MMFR1_EL1
Definition misc.hh:576
@ MISCREG_DBGPRCR_EL1
Definition misc.hh:537
@ MISCREG_NMRR_MAIR1
Definition misc.hh:93
@ MISCREG_ICH_LR4_EL2
Definition misc.hh:964
@ MISCREG_UNKNOWN
Definition misc.hh:1173
@ MISCREG_PMOVSR
Definition misc.hh:360
@ MISCREG_ICH_ELRSR
Definition misc.hh:1079
@ MISCREG_TLBIALLNSNH
Definition misc.hh:355
@ MISCREG_TTBR0_EL12
Definition misc.hh:609
@ MISCREG_CNTHP_TVAL
Definition misc.hh:438
@ MISCREG_ATS12NSOUR
Definition misc.hh:316
@ MISCREG_ELR_HYP
Definition misc.hh:76
@ MISCREG_TLBI_RVALE1OS
Definition misc.hh:762
@ MISCREG_DBGWCR10_EL1
Definition misc.hh:522
@ MISCREG_CNTVCT_EL0
Definition misc.hh:815
@ MISCREG_DBGBVR14
Definition misc.hh:126
@ MISCREG_TLBI_VMALLE1
Definition misc.hh:704
@ MISCREG_DBGBVR8_EL1
Definition misc.hh:472
@ MISCREG_ICH_LR11_EL2
Definition misc.hh:971
@ MISCREG_CBAR_EL1
Definition misc.hh:876
@ MISCREG_ICC_AP1R1_EL1
Definition misc.hh:910
@ MISCREG_ICV_AP1R1_EL1_S
Definition misc.hh:991
@ MISCREG_DL1DATA3_EL1
Definition misc.hh:869
@ MISCREG_RVBAR_EL2
Definition misc.hh:801
@ MISCREG_DBGDEVID2
Definition misc.hh:201
@ MISCREG_SP_EL0
Definition misc.hh:630
@ MISCREG_PMCNTENCLR
Definition misc.hh:359
@ MISCREG_ERRSELR_EL1
Definition misc.hh:1182
@ MISCREG_TLBI_VMALLS12E1
Definition misc.hh:730
@ MISCREG_DFAR_S
Definition misc.hh:291
@ MISCREG_DBGBVR0_EL1
Definition misc.hh:464
@ MISCREG_ICC_AP1R2_NS
Definition misc.hh:1031
@ MISCREG_DBGBCR4_EL1
Definition misc.hh:484
@ MISCREG_CPSR
Definition misc.hh:67
@ MISCREG_FPCR
Definition misc.hh:635
@ MISCREG_SDCR
Definition misc.hh:248
@ MISCREG_DBGWCR4
Definition misc.hh:164
@ MISCREG_ICH_LR14_EL2
Definition misc.hh:974
@ MISCREG_ICV_SRE_EL1_S
Definition misc.hh:1014
@ MISCREG_TLBI_VAE2IS
Definition misc.hh:716
@ MISCREG_RMR
Definition misc.hh:401
@ MISCREG_CPACR_EL1
Definition misc.hh:590
@ MISCREG_HACR
Definition misc.hh:259
@ MISCREG_ICC_RPR_EL1
Definition misc.hh:920
@ MISCREG_DBGBXVR13
Definition misc.hh:190
@ MISCREG_IFSR_NS
Definition misc.hh:278
@ MISCREG_SMPRI_EL1
Definition misc.hh:1125
@ MISCREG_ID_MMFR0
Definition misc.hh:221
@ MISCREG_PMEVTYPER5_EL0
Definition misc.hh:861
@ MISCREG_CNTP_CVAL
Definition misc.hh:425
@ MISCREG_ID_ISAR0
Definition misc.hh:226
@ MISCREG_DBGBVR2_EL1
Definition misc.hh:466
@ MISCREG_ICC_AP1R3_EL1_S
Definition misc.hh:918
@ MISCREG_DL1DATA4
Definition misc.hh:449
@ MISCREG_CNTKCTL_EL1
Definition misc.hh:828
@ MISCREG_HMAIR0
Definition misc.hh:393
@ MISCREG_DBGWVR11
Definition misc.hh:155
@ MISCREG_ICC_AP0R3_EL1
Definition misc.hh:906
@ MISCREG_MPAMHCR_EL2
Definition misc.hh:1152
@ MISCREG_ICC_BPR1_NS
Definition misc.hh:1039
@ MISCREG_CNTPCT
Definition misc.hh:420
@ MISCREG_ICH_LR10_EL2
Definition misc.hh:970
@ MISCREG_SP_EL2
Definition misc.hh:648
@ MISCREG_ICC_AP0R1
Definition misc.hh:1021
@ MISCREG_PMCCFILTR_EL0
Definition misc.hh:782
@ MISCREG_ICH_LR10
Definition misc.hh:1091
@ MISCREG_CNTPS_CTL_EL1
Definition misc.hh:830
@ MISCREG_TLBI_VMALLS12E1IS
Definition misc.hh:722
@ MISCREG_ID_AA64MMFR3_EL1
Definition misc.hh:883
@ MISCREG_NMRR
Definition misc.hh:381
@ MISCREG_MPAMVPMV_EL2
Definition misc.hh:1153
@ MISCREG_ICC_SRE_EL1
Definition misc.hh:933
@ MISCREG_DBGBVR12_EL1
Definition misc.hh:476
@ MISCREG_PMSWINC_EL0
Definition misc.hh:776
@ MISCREG_SCTLR_EL12
Definition misc.hh:586
@ MISCREG_DBGBVR10
Definition misc.hh:122
@ MISCREG_TTBR1_EL1
Definition misc.hh:610
@ MISCREG_PMEVTYPER2_EL0
Definition misc.hh:858
@ MISCREG_MAIR1
Definition misc.hh:384
@ MISCREG_DAIF
Definition misc.hh:634
@ MISCREG_SPSR_ABT_AA64
Definition misc.hh:643
@ MISCREG_SEV_MAILBOX
Definition misc.hh:97
@ MISCREG_SPSR_EL12
Definition misc.hh:627
@ MISCREG_ICV_AP1R0_EL1_NS
Definition misc.hh:987
@ MISCREG_CNTP_CVAL_EL02
Definition misc.hh:823
@ MISCREG_ACTLR_NS
Definition misc.hh:245
@ MISCREG_PMINTENSET_EL1
Definition misc.hh:770
@ MISCREG_ICC_AP1R1_S
Definition misc.hh:1029
@ MISCREG_PMINTENCLR_EL1
Definition misc.hh:771
@ MISCREG_CNTHPS_CVAL_EL2
Definition misc.hh:838
@ MISCREG_REVIDR
Definition misc.hh:216
@ MISCREG_DBGBCR9
Definition misc.hh:137
@ MISCREG_MPAMVPM0_EL2
Definition misc.hh:1154
@ MISCREG_DL1DATA0_EL1
Definition misc.hh:866
@ MISCREG_PMCCFILTR
Definition misc.hh:367
@ MISCREG_ICV_AP0R2_EL1
Definition misc.hh:984
@ MISCREG_ACTLR_EL3
Definition