41#ifndef __ARCH_ARM_REGS_MISC_HH__
42#define __ARCH_ARM_REGS_MISC_HH__
53#include "debug/MiscRegs.hh"
1258 std::bitset<NUM_MISCREG_INFOS>
info;
1272 template <MiscRegInfo Sec, MiscRegInfo NonSec>
1699 unsigned _crn,
unsigned _crm,
1716 assert(
opc1 < 16 &&
crm < 16);
1735 return reg64 << 19 |
1758 unsigned _crn,
unsigned _crm,
1771 return op0 == other.
op0 &&
1797 unsigned crm,
unsigned opc2);
1799 unsigned crn,
unsigned crm,
1809 unsigned crm,
unsigned opc2);
1845 "pmxevtyper_pmccfiltr",
2287 "dbgauthstatus_el1",
2469 "tlbi_vmalls12e1is",
2470 "tlbi_vmalls12e1os",
2677 "icc_igrpen1_el1_ns",
2678 "icc_igrpen1_el1_s",
2756 "icv_igrpen1_el1_ns",
2757 "icv_igrpen1_el1_s",
2923 "The miscRegName array and NUM_MISCREGS are inconsistent.");
3039struct hash<
gem5::ArmISA::MiscRegNum32>
3044 return reg.packed();
3049struct hash<
gem5::ArmISA::MiscRegNum64>
3054 return reg.packed();
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Metadata table accessible via the value of the register.
chain userNonSecureWrite(bool v=true) const
const MiscRegLUTEntryInitializer & chain
chain userSecureWrite(bool v=true) const
chain exceptUserMode() const
chain warnNotFail(bool v=true) const
chain mapsTo(uint32_t l, uint32_t u=0) const
chain fault(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
chain userSecureRead(bool v=true) const
chain implemented(bool v=true) const
chain reads(bool v) const
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
chain highest(ArmSystem *const sys) const
chain secure(bool v=true) const
chain mutex(bool v=true) const
chain hypNonSecureWrite(bool v=true) const
chain priv(bool v=true) const
chain raz(uint64_t mask=(uint64_t) -1) const
chain hypSecureRead(bool v=true) const
chain monSecure(bool v=true) const
chain privSecure(bool v=true) const
chain privSecureRead(bool v=true) const
chain privNonSecure(bool v=true) const
chain hypSecureWrite(bool v=true) const
chain userNonSecureRead(bool v=true) const
chain nonSecure(bool v=true) const
chain privNonSecureRead(bool v=true) const
chain monNonSecureWrite(bool v=true) const
chain reset(uint64_t res_val) const
chain monNonSecureRead(bool v=true) const
chain monWrite(bool v=true) const
chain user(bool v=true) const
chain unverifiable(bool v=true) const
chain hypSecure(bool v=true) const
chain banked(bool v=true) const
chain privRead(bool v=true) const
chain hypRead(bool v=true) const
struct MiscRegLUTEntry & entry
chain banked64(bool v=true) const
chain fault(MiscRegLUTEntry::FaultCB cb) const
chain res0(uint64_t mask) const
chain bankedChild(bool v=true) const
chain hypWrite(bool v=true) const
chain writes(bool v) const
chain allPrivileges(bool v=true) const
chain monSecureRead(bool v=true) const
chain privSecureWrite(bool v=true) const
chain res1(uint64_t mask) const
chain faultRead(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
chain hypNonSecureRead(bool v=true) const
chain monNonSecure(bool v=true) const
chain monSecureWrite(bool v=true) const
chain rao(uint64_t mask=(uint64_t) -1) const
chain mon(bool v=true) const
chain unimplemented() const
chain privNonSecureWrite(bool v=true) const
chain unserialize(bool v=true) const
chain faultWrite(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
chain hyp(bool v=true) const
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Register ID: describe an architectural register with its class and index.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
static const uint32_t FpscrQcMask
static MiscRegClassOps miscRegClassOps
bool aarch64SysRegReadOnly(MiscRegIndex miscReg)
static const uint32_t CpsrMask
static const uint32_t FpscrExcMask
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
static const uint32_t ApsrMask
static const uint32_t CpsrMaskQ
static const uint32_t FpCondCodesMask
void preUnflattenMiscReg()
static const uint32_t FpscrAhpMask
@ MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICV_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ICV_AP1R1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICV_AP1R2_EL1_S
@ MISCREG_TLBI_IPAS2LE1IS
@ MISCREG_ICV_IGRPEN1_EL1_NS
@ MISCREG_TLBI_VMALLS12E1OS
@ MISCREG_ICV_IGRPEN0_EL1
@ MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICV_AP1R3_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICV_CTLR_EL1_NS
@ MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ICV_AP1R1_EL1_S
@ MISCREG_TLBI_VMALLS12E1
@ MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_TLBI_VMALLS12E1IS
@ MISCREG_ID_AA64MMFR3_EL1
@ MISCREG_ICV_AP1R0_EL1_NS
@ MISCREG_CNTHPS_CVAL_EL2