gem5 v24.1.0.1
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misc.hh
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1/*
2 * Copyright (c) 2010-2024 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef __ARCH_ARM_REGS_MISC_HH__
42#define __ARCH_ARM_REGS_MISC_HH__
43
44#include <array>
45#include <bitset>
46#include <optional>
47#include <tuple>
48
49#include "arch/arm/regs/misc_types.hh"
50#include "arch/arm/types.hh"
51#include "base/compiler.hh"
52#include "cpu/reg_class.hh"
53#include "debug/MiscRegs.hh"
54#include "dev/arm/generic_timer_miscregs_types.hh"
55
56#define TLBI_VARIANTS(TLBI) \
57 TLBI, \
58 TLBI##NXS
59
60#define TLBI_CASE_VARIANTS(TLBI) \
61 case TLBI: \
62 case TLBI##NXS:
63
64#define TLBI_STR_VARIANTS(TLBI) \
65 #TLBI, \
66 #TLBI"nxs"
67
68namespace gem5
69{
70
71class ArmSystem;
72class ThreadContext;
73class MiscRegOp64;
74
75namespace ArmISA
76{
77 enum MiscRegIndex
78 {
79 MISCREG_CPSR = 0,
80 MISCREG_SPSR,
81 MISCREG_SPSR_FIQ,
82 MISCREG_SPSR_IRQ,
83 MISCREG_SPSR_SVC,
84 MISCREG_SPSR_MON,
85 MISCREG_SPSR_ABT,
86 MISCREG_SPSR_HYP,
87 MISCREG_SPSR_UND,
88 MISCREG_ELR_HYP,
89 MISCREG_FPSID,
90 MISCREG_FPSCR,
91 MISCREG_MVFR1,
92 MISCREG_MVFR0,
93 MISCREG_FPEXC,
94
95 // Helper registers
96 MISCREG_CPSR_MODE,
97 MISCREG_CPSR_Q,
98 MISCREG_FPSCR_EXC,
99 MISCREG_FPSCR_QC,
100 MISCREG_LOCKADDR,
101 MISCREG_LOCKFLAG,
102 MISCREG_PRRR_MAIR0,
103 MISCREG_PRRR_MAIR0_NS,
104 MISCREG_PRRR_MAIR0_S,
105 MISCREG_NMRR_MAIR1,
106 MISCREG_NMRR_MAIR1_NS,
107 MISCREG_NMRR_MAIR1_S,
108 MISCREG_PMXEVTYPER_PMCCFILTR,
109 MISCREG_SEV_MAILBOX,
110 MISCREG_TLBINEEDSYNC,
111
112 // AArch32 CP14 registers (debug/trace control)
113 MISCREG_DBGDIDR,
114 MISCREG_DBGDSCRint,
115 MISCREG_DBGDCCINT,
116 MISCREG_DBGDTRTXint,
117 MISCREG_DBGDTRRXint,
118 MISCREG_DBGWFAR,
119 MISCREG_DBGVCR,
120 MISCREG_DBGDTRRXext,
121 MISCREG_DBGDSCRext,
122 MISCREG_DBGDTRTXext,
123 MISCREG_DBGOSECCR,
124 MISCREG_DBGBVR0,
125 MISCREG_DBGBVR1,
126 MISCREG_DBGBVR2,
127 MISCREG_DBGBVR3,
128 MISCREG_DBGBVR4,
129 MISCREG_DBGBVR5,
130 MISCREG_DBGBVR6,
131 MISCREG_DBGBVR7,
132 MISCREG_DBGBVR8,
133 MISCREG_DBGBVR9,
134 MISCREG_DBGBVR10,
135 MISCREG_DBGBVR11,
136 MISCREG_DBGBVR12,
137 MISCREG_DBGBVR13,
138 MISCREG_DBGBVR14,
139 MISCREG_DBGBVR15,
140 MISCREG_DBGBCR0,
141 MISCREG_DBGBCR1,
142 MISCREG_DBGBCR2,
143 MISCREG_DBGBCR3,
144 MISCREG_DBGBCR4,
145 MISCREG_DBGBCR5,
146 MISCREG_DBGBCR6,
147 MISCREG_DBGBCR7,
148 MISCREG_DBGBCR8,
149 MISCREG_DBGBCR9,
150 MISCREG_DBGBCR10,
151 MISCREG_DBGBCR11,
152 MISCREG_DBGBCR12,
153 MISCREG_DBGBCR13,
154 MISCREG_DBGBCR14,
155 MISCREG_DBGBCR15,
156 MISCREG_DBGWVR0,
157 MISCREG_DBGWVR1,
158 MISCREG_DBGWVR2,
159 MISCREG_DBGWVR3,
160 MISCREG_DBGWVR4,
161 MISCREG_DBGWVR5,
162 MISCREG_DBGWVR6,
163 MISCREG_DBGWVR7,
164 MISCREG_DBGWVR8,
165 MISCREG_DBGWVR9,
166 MISCREG_DBGWVR10,
167 MISCREG_DBGWVR11,
168 MISCREG_DBGWVR12,
169 MISCREG_DBGWVR13,
170 MISCREG_DBGWVR14,
171 MISCREG_DBGWVR15,
172 MISCREG_DBGWCR0,
173 MISCREG_DBGWCR1,
174 MISCREG_DBGWCR2,
175 MISCREG_DBGWCR3,
176 MISCREG_DBGWCR4,
177 MISCREG_DBGWCR5,
178 MISCREG_DBGWCR6,
179 MISCREG_DBGWCR7,
180 MISCREG_DBGWCR8,
181 MISCREG_DBGWCR9,
182 MISCREG_DBGWCR10,
183 MISCREG_DBGWCR11,
184 MISCREG_DBGWCR12,
185 MISCREG_DBGWCR13,
186 MISCREG_DBGWCR14,
187 MISCREG_DBGWCR15,
188 MISCREG_DBGDRAR,
189 MISCREG_DBGBXVR0,
190 MISCREG_DBGBXVR1,
191 MISCREG_DBGBXVR2,
192 MISCREG_DBGBXVR3,
193 MISCREG_DBGBXVR4,
194 MISCREG_DBGBXVR5,
195 MISCREG_DBGBXVR6,
196 MISCREG_DBGBXVR7,
197 MISCREG_DBGBXVR8,
198 MISCREG_DBGBXVR9,
199 MISCREG_DBGBXVR10,
200 MISCREG_DBGBXVR11,
201 MISCREG_DBGBXVR12,
202 MISCREG_DBGBXVR13,
203 MISCREG_DBGBXVR14,
204 MISCREG_DBGBXVR15,
205 MISCREG_DBGOSLAR,
206 MISCREG_DBGOSLSR,
207 MISCREG_DBGOSDLR,
208 MISCREG_DBGPRCR,
209 MISCREG_DBGDSAR,
210 MISCREG_DBGCLAIMSET,
211 MISCREG_DBGCLAIMCLR,
212 MISCREG_DBGAUTHSTATUS,
213 MISCREG_DBGDEVID2,
214 MISCREG_DBGDEVID1,
215 MISCREG_DBGDEVID0,
216 MISCREG_TEECR, // not in ARM DDI 0487A.b+
217 MISCREG_JIDR,
218 MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
219 MISCREG_JOSCR,
220 MISCREG_JMCR,
221
222 // AArch32 CP15 registers (system control)
223 MISCREG_MIDR,
224 MISCREG_CTR,
225 MISCREG_TCMTR,
226 MISCREG_TLBTR,
227 MISCREG_MPIDR,
228 MISCREG_REVIDR,
229 MISCREG_ID_PFR0,
230 MISCREG_ID_PFR1,
231 MISCREG_ID_DFR0,
232 MISCREG_ID_AFR0,
233 MISCREG_ID_MMFR0,
234 MISCREG_ID_MMFR1,
235 MISCREG_ID_MMFR2,
236 MISCREG_ID_MMFR3,
237 MISCREG_ID_MMFR4,
238 MISCREG_ID_ISAR0,
239 MISCREG_ID_ISAR1,
240 MISCREG_ID_ISAR2,
241 MISCREG_ID_ISAR3,
242 MISCREG_ID_ISAR4,
243 MISCREG_ID_ISAR5,
244 MISCREG_ID_ISAR6,
245 MISCREG_CCSIDR,
246 MISCREG_CLIDR,
247 MISCREG_AIDR,
248 MISCREG_CSSELR,
249 MISCREG_CSSELR_NS,
250 MISCREG_CSSELR_S,
251 MISCREG_VPIDR,
252 MISCREG_VMPIDR,
253 MISCREG_SCTLR,
254 MISCREG_SCTLR_NS,
255 MISCREG_SCTLR_S,
256 MISCREG_ACTLR,
257 MISCREG_ACTLR_NS,
258 MISCREG_ACTLR_S,
259 MISCREG_CPACR,
260 MISCREG_SDCR,
261 MISCREG_SCR,
262 MISCREG_SDER,
263 MISCREG_NSACR,
264 MISCREG_HSCTLR,
265 MISCREG_HACTLR,
266 MISCREG_HCR,
267 MISCREG_HCR2,
268 MISCREG_HDCR,
269 MISCREG_HCPTR,
270 MISCREG_HSTR,
271 MISCREG_HACR,
272 MISCREG_TTBR0,
273 MISCREG_TTBR0_NS,
274 MISCREG_TTBR0_S,
275 MISCREG_TTBR1,
276 MISCREG_TTBR1_NS,
277 MISCREG_TTBR1_S,
278 MISCREG_TTBCR,
279 MISCREG_TTBCR_NS,
280 MISCREG_TTBCR_S,
281 MISCREG_HTCR,
282 MISCREG_VTCR,
283 MISCREG_DACR,
284 MISCREG_DACR_NS,
285 MISCREG_DACR_S,
286 MISCREG_DFSR,
287 MISCREG_DFSR_NS,
288 MISCREG_DFSR_S,
289 MISCREG_IFSR,
290 MISCREG_IFSR_NS,
291 MISCREG_IFSR_S,
292 MISCREG_ADFSR,
293 MISCREG_ADFSR_NS,
294 MISCREG_ADFSR_S,
295 MISCREG_AIFSR,
296 MISCREG_AIFSR_NS,
297 MISCREG_AIFSR_S,
298 MISCREG_HADFSR,
299 MISCREG_HAIFSR,
300 MISCREG_HSR,
301 MISCREG_DFAR,
302 MISCREG_DFAR_NS,
303 MISCREG_DFAR_S,
304 MISCREG_IFAR,
305 MISCREG_IFAR_NS,
306 MISCREG_IFAR_S,
307 MISCREG_HDFAR,
308 MISCREG_HIFAR,
309 MISCREG_HPFAR,
310 MISCREG_ICIALLUIS,
311 MISCREG_BPIALLIS,
312 MISCREG_PAR,
313 MISCREG_PAR_NS,
314 MISCREG_PAR_S,
315 MISCREG_ICIALLU,
316 MISCREG_ICIMVAU,
317 MISCREG_CP15ISB,
318 MISCREG_BPIALL,
319 MISCREG_BPIMVA,
320 MISCREG_DCIMVAC,
321 MISCREG_DCISW,
322 MISCREG_ATS1CPR,
323 MISCREG_ATS1CPW,
324 MISCREG_ATS1CUR,
325 MISCREG_ATS1CUW,
326 MISCREG_ATS12NSOPR,
327 MISCREG_ATS12NSOPW,
328 MISCREG_ATS12NSOUR,
329 MISCREG_ATS12NSOUW,
330 MISCREG_DCCMVAC,
331 MISCREG_DCCSW,
332 MISCREG_CP15DSB,
333 MISCREG_CP15DMB,
334 MISCREG_DCCMVAU,
335 MISCREG_DCCIMVAC,
336 MISCREG_DCCISW,
337 MISCREG_ATS1HR,
338 MISCREG_ATS1HW,
339 MISCREG_TLBIALLIS,
340 MISCREG_TLBIMVAIS,
341 MISCREG_TLBIASIDIS,
342 MISCREG_TLBIMVAAIS,
343 MISCREG_TLBIMVALIS,
344 MISCREG_TLBIMVAALIS,
345 MISCREG_ITLBIALL,
346 MISCREG_ITLBIMVA,
347 MISCREG_ITLBIASID,
348 MISCREG_DTLBIALL,
349 MISCREG_DTLBIMVA,
350 MISCREG_DTLBIASID,
351 MISCREG_TLBIALL,
352 MISCREG_TLBIMVA,
353 MISCREG_TLBIASID,
354 MISCREG_TLBIMVAA,
355 MISCREG_TLBIMVAL,
356 MISCREG_TLBIMVAAL,
357 MISCREG_TLBIIPAS2IS,
358 MISCREG_TLBIIPAS2LIS,
359 MISCREG_TLBIALLHIS,
360 MISCREG_TLBIMVAHIS,
361 MISCREG_TLBIALLNSNHIS,
362 MISCREG_TLBIMVALHIS,
363 MISCREG_TLBIIPAS2,
364 MISCREG_TLBIIPAS2L,
365 MISCREG_TLBIALLH,
366 MISCREG_TLBIMVAH,
367 MISCREG_TLBIALLNSNH,
368 MISCREG_TLBIMVALH,
369 MISCREG_PMCR,
370 MISCREG_PMCNTENSET,
371 MISCREG_PMCNTENCLR,
372 MISCREG_PMOVSR,
373 MISCREG_PMSWINC,
374 MISCREG_PMSELR,
375 MISCREG_PMCEID0,
376 MISCREG_PMCEID1,
377 MISCREG_PMCCNTR,
378 MISCREG_PMXEVTYPER,
379 MISCREG_PMEVCNTR0,
380 MISCREG_PMEVCNTR1,
381 MISCREG_PMEVCNTR2,
382 MISCREG_PMEVCNTR3,
383 MISCREG_PMEVCNTR4,
384 MISCREG_PMEVCNTR5,
385 MISCREG_PMEVTYPER0,
386 MISCREG_PMEVTYPER1,
387 MISCREG_PMEVTYPER2,
388 MISCREG_PMEVTYPER3,
389 MISCREG_PMEVTYPER4,
390 MISCREG_PMEVTYPER5,
391 MISCREG_PMCCFILTR,
392 MISCREG_PMXEVCNTR,
393 MISCREG_PMUSERENR,
394 MISCREG_PMINTENSET,
395 MISCREG_PMINTENCLR,
396 MISCREG_PMOVSSET,
397 MISCREG_L2CTLR,
398 MISCREG_L2ECTLR,
399 MISCREG_PRRR,
400 MISCREG_PRRR_NS,
401 MISCREG_PRRR_S,
402 MISCREG_MAIR0,
403 MISCREG_MAIR0_NS,
404 MISCREG_MAIR0_S,
405 MISCREG_NMRR,
406 MISCREG_NMRR_NS,
407 MISCREG_NMRR_S,
408 MISCREG_MAIR1,
409 MISCREG_MAIR1_NS,
410 MISCREG_MAIR1_S,
411 MISCREG_AMAIR0,
412 MISCREG_AMAIR0_NS,
413 MISCREG_AMAIR0_S,
414 MISCREG_AMAIR1,
415 MISCREG_AMAIR1_NS,
416 MISCREG_AMAIR1_S,
417 MISCREG_HMAIR0,
418 MISCREG_HMAIR1,
419 MISCREG_HAMAIR0,
420 MISCREG_HAMAIR1,
421 MISCREG_VBAR,
422 MISCREG_VBAR_NS,
423 MISCREG_VBAR_S,
424 MISCREG_MVBAR,
425 MISCREG_RMR,
426 MISCREG_ISR,
427 MISCREG_HVBAR,
428 MISCREG_FCSEIDR,
429 MISCREG_CONTEXTIDR,
430 MISCREG_CONTEXTIDR_NS,
431 MISCREG_CONTEXTIDR_S,
432 MISCREG_TPIDRURW,
433 MISCREG_TPIDRURW_NS,
434 MISCREG_TPIDRURW_S,
435 MISCREG_TPIDRURO,
436 MISCREG_TPIDRURO_NS,
437 MISCREG_TPIDRURO_S,
438 MISCREG_TPIDRPRW,
439 MISCREG_TPIDRPRW_NS,
440 MISCREG_TPIDRPRW_S,
441 MISCREG_HTPIDR,
442 // BEGIN Generic Timer (AArch32)
443 MISCREG_CNTFRQ,
444 MISCREG_CNTPCT,
445 MISCREG_CNTVCT,
446 MISCREG_CNTP_CTL,
447 MISCREG_CNTP_CTL_NS,
448 MISCREG_CNTP_CTL_S,
449 MISCREG_CNTP_CVAL,
450 MISCREG_CNTP_CVAL_NS,
451 MISCREG_CNTP_CVAL_S,
452 MISCREG_CNTP_TVAL,
453 MISCREG_CNTP_TVAL_NS,
454 MISCREG_CNTP_TVAL_S,
455 MISCREG_CNTV_CTL,
456 MISCREG_CNTV_CVAL,
457 MISCREG_CNTV_TVAL,
458 MISCREG_CNTKCTL,
459 MISCREG_CNTHCTL,
460 MISCREG_CNTHP_CTL,
461 MISCREG_CNTHP_CVAL,
462 MISCREG_CNTHP_TVAL,
463 MISCREG_CNTVOFF,
464 // END Generic Timer (AArch32)
465 MISCREG_IL1DATA0,
466 MISCREG_IL1DATA1,
467 MISCREG_IL1DATA2,
468 MISCREG_IL1DATA3,
469 MISCREG_DL1DATA0,
470 MISCREG_DL1DATA1,
471 MISCREG_DL1DATA2,
472 MISCREG_DL1DATA3,
473 MISCREG_DL1DATA4,
474 MISCREG_RAMINDEX,
475 MISCREG_L2ACTLR,
476 MISCREG_CBAR,
477 MISCREG_HTTBR,
478 MISCREG_VTTBR,
479 MISCREG_CPUMERRSR,
480 MISCREG_L2MERRSR,
481
482 // AArch64 registers (Op0=2)
483 MISCREG_MDCCINT_EL1,
484 MISCREG_OSDTRRX_EL1,
485 MISCREG_MDSCR_EL1,
486 MISCREG_OSDTRTX_EL1,
487 MISCREG_OSECCR_EL1,
488 MISCREG_DBGBVR0_EL1,
489 MISCREG_DBGBVR1_EL1,
490 MISCREG_DBGBVR2_EL1,
491 MISCREG_DBGBVR3_EL1,
492 MISCREG_DBGBVR4_EL1,
493 MISCREG_DBGBVR5_EL1,
494 MISCREG_DBGBVR6_EL1,
495 MISCREG_DBGBVR7_EL1,
496 MISCREG_DBGBVR8_EL1,
497 MISCREG_DBGBVR9_EL1,
498 MISCREG_DBGBVR10_EL1,
499 MISCREG_DBGBVR11_EL1,
500 MISCREG_DBGBVR12_EL1,
501 MISCREG_DBGBVR13_EL1,
502 MISCREG_DBGBVR14_EL1,
503 MISCREG_DBGBVR15_EL1,
504 MISCREG_DBGBCR0_EL1,
505 MISCREG_DBGBCR1_EL1,
506 MISCREG_DBGBCR2_EL1,
507 MISCREG_DBGBCR3_EL1,
508 MISCREG_DBGBCR4_EL1,
509 MISCREG_DBGBCR5_EL1,
510 MISCREG_DBGBCR6_EL1,
511 MISCREG_DBGBCR7_EL1,
512 MISCREG_DBGBCR8_EL1,
513 MISCREG_DBGBCR9_EL1,
514 MISCREG_DBGBCR10_EL1,
515 MISCREG_DBGBCR11_EL1,
516 MISCREG_DBGBCR12_EL1,
517 MISCREG_DBGBCR13_EL1,
518 MISCREG_DBGBCR14_EL1,
519 MISCREG_DBGBCR15_EL1,
520 MISCREG_DBGWVR0_EL1,
521 MISCREG_DBGWVR1_EL1,
522 MISCREG_DBGWVR2_EL1,
523 MISCREG_DBGWVR3_EL1,
524 MISCREG_DBGWVR4_EL1,
525 MISCREG_DBGWVR5_EL1,
526 MISCREG_DBGWVR6_EL1,
527 MISCREG_DBGWVR7_EL1,
528 MISCREG_DBGWVR8_EL1,
529 MISCREG_DBGWVR9_EL1,
530 MISCREG_DBGWVR10_EL1,
531 MISCREG_DBGWVR11_EL1,
532 MISCREG_DBGWVR12_EL1,
533 MISCREG_DBGWVR13_EL1,
534 MISCREG_DBGWVR14_EL1,
535 MISCREG_DBGWVR15_EL1,
536 MISCREG_DBGWCR0_EL1,
537 MISCREG_DBGWCR1_EL1,
538 MISCREG_DBGWCR2_EL1,
539 MISCREG_DBGWCR3_EL1,
540 MISCREG_DBGWCR4_EL1,
541 MISCREG_DBGWCR5_EL1,
542 MISCREG_DBGWCR6_EL1,
543 MISCREG_DBGWCR7_EL1,
544 MISCREG_DBGWCR8_EL1,
545 MISCREG_DBGWCR9_EL1,
546 MISCREG_DBGWCR10_EL1,
547 MISCREG_DBGWCR11_EL1,
548 MISCREG_DBGWCR12_EL1,
549 MISCREG_DBGWCR13_EL1,
550 MISCREG_DBGWCR14_EL1,
551 MISCREG_DBGWCR15_EL1,
552 MISCREG_MDCCSR_EL0,
553 MISCREG_MDDTR_EL0,
554 MISCREG_MDDTRTX_EL0,
555 MISCREG_MDDTRRX_EL0,
556 MISCREG_DBGVCR32_EL2,
557 MISCREG_MDRAR_EL1,
558 MISCREG_OSLAR_EL1,
559 MISCREG_OSLSR_EL1,
560 MISCREG_OSDLR_EL1,
561 MISCREG_DBGPRCR_EL1,
562 MISCREG_DBGCLAIMSET_EL1,
563 MISCREG_DBGCLAIMCLR_EL1,
564 MISCREG_DBGAUTHSTATUS_EL1,
565 MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
566 MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
567
568 // AArch64 registers (Op0=1,3)
569 MISCREG_MIDR_EL1,
570 MISCREG_MPIDR_EL1,
571 MISCREG_REVIDR_EL1,
572 MISCREG_ID_PFR0_EL1,
573 MISCREG_ID_PFR1_EL1,
574 MISCREG_ID_DFR0_EL1,
575 MISCREG_ID_AFR0_EL1,
576 MISCREG_ID_MMFR0_EL1,
577 MISCREG_ID_MMFR1_EL1,
578 MISCREG_ID_MMFR2_EL1,
579 MISCREG_ID_MMFR3_EL1,
580 MISCREG_ID_MMFR4_EL1,
581 MISCREG_ID_ISAR0_EL1,
582 MISCREG_ID_ISAR1_EL1,
583 MISCREG_ID_ISAR2_EL1,
584 MISCREG_ID_ISAR3_EL1,
585 MISCREG_ID_ISAR4_EL1,
586 MISCREG_ID_ISAR5_EL1,
587 MISCREG_ID_ISAR6_EL1,
588 MISCREG_MVFR0_EL1,
589 MISCREG_MVFR1_EL1,
590 MISCREG_MVFR2_EL1,
591 MISCREG_ID_AA64PFR0_EL1,
592 MISCREG_ID_AA64PFR1_EL1,
593 MISCREG_ID_AA64DFR0_EL1,
594 MISCREG_ID_AA64DFR1_EL1,
595 MISCREG_ID_AA64AFR0_EL1,
596 MISCREG_ID_AA64AFR1_EL1,
597 MISCREG_ID_AA64ISAR0_EL1,
598 MISCREG_ID_AA64ISAR1_EL1,
599 MISCREG_ID_AA64MMFR0_EL1,
600 MISCREG_ID_AA64MMFR1_EL1,
601 MISCREG_CCSIDR_EL1,
602 MISCREG_CLIDR_EL1,
603 MISCREG_AIDR_EL1,
604 MISCREG_CSSELR_EL1,
605 MISCREG_CTR_EL0,
606 MISCREG_DCZID_EL0,
607 MISCREG_VPIDR_EL2,
608 MISCREG_VMPIDR_EL2,
609 MISCREG_SCTLR_EL1,
610 MISCREG_SCTLR_EL12,
611 MISCREG_SCTLR2_EL1,
612 MISCREG_SCTLR2_EL12,
613 MISCREG_ACTLR_EL1,
614 MISCREG_CPACR_EL1,
615 MISCREG_CPACR_EL12,
616 MISCREG_SCTLR_EL2,
617 MISCREG_SCTLR2_EL2,
618 MISCREG_ACTLR_EL2,
619 MISCREG_HCR_EL2,
620 MISCREG_HCRX_EL2,
621 MISCREG_MDCR_EL2,
622 MISCREG_CPTR_EL2,
623 MISCREG_HSTR_EL2,
624 MISCREG_HACR_EL2,
625 MISCREG_SCTLR_EL3,
626 MISCREG_SCTLR2_EL3,
627 MISCREG_ACTLR_EL3,
628 MISCREG_SCR_EL3,
629 MISCREG_SDER32_EL3,
630 MISCREG_CPTR_EL3,
631 MISCREG_MDCR_EL3,
632 MISCREG_TTBR0_EL1,
633 MISCREG_TTBR0_EL12,
634 MISCREG_TTBR1_EL1,
635 MISCREG_TTBR1_EL12,
636 MISCREG_TCR_EL1,
637 MISCREG_TCR_EL12,
638 MISCREG_TCR2_EL1,
639 MISCREG_TCR2_EL12,
640 MISCREG_TTBR0_EL2,
641 MISCREG_TCR_EL2,
642 MISCREG_TCR2_EL2,
643 MISCREG_VTTBR_EL2,
644 MISCREG_VTCR_EL2,
645 MISCREG_VSTTBR_EL2,
646 MISCREG_VSTCR_EL2,
647 MISCREG_TTBR0_EL3,
648 MISCREG_TCR_EL3,
649 MISCREG_DACR32_EL2,
650 MISCREG_SPSR_EL1,
651 MISCREG_SPSR_EL12,
652 MISCREG_ELR_EL1,
653 MISCREG_ELR_EL12,
654 MISCREG_SP_EL0,
655 MISCREG_SPSEL,
656 MISCREG_CURRENTEL,
657 MISCREG_NZCV,
658 MISCREG_DAIF,
659 MISCREG_FPCR,
660 MISCREG_FPSR,
661 MISCREG_DSPSR_EL0,
662 MISCREG_DLR_EL0,
663 MISCREG_SPSR_EL2,
664 MISCREG_ELR_EL2,
665 MISCREG_SP_EL1,
666 MISCREG_SPSR_IRQ_AA64,
667 MISCREG_SPSR_ABT_AA64,
668 MISCREG_SPSR_UND_AA64,
669 MISCREG_SPSR_FIQ_AA64,
670 MISCREG_SPSR_EL3,
671 MISCREG_ELR_EL3,
672 MISCREG_SP_EL2,
673 MISCREG_AFSR0_EL1,
674 MISCREG_AFSR0_EL12,
675 MISCREG_AFSR1_EL1,
676 MISCREG_AFSR1_EL12,
677 MISCREG_ESR_EL1,
678 MISCREG_ESR_EL12,
679 MISCREG_IFSR32_EL2,
680 MISCREG_AFSR0_EL2,
681 MISCREG_AFSR1_EL2,
682 MISCREG_ESR_EL2,
683 MISCREG_FPEXC32_EL2,
684 MISCREG_AFSR0_EL3,
685 MISCREG_AFSR1_EL3,
686 MISCREG_ESR_EL3,
687 MISCREG_FAR_EL1,
688 MISCREG_FAR_EL12,
689 MISCREG_FAR_EL2,
690 MISCREG_HPFAR_EL2,
691 MISCREG_FAR_EL3,
692 MISCREG_IC_IALLUIS,
693 MISCREG_PAR_EL1,
694 MISCREG_IC_IALLU,
695 MISCREG_DC_IVAC_Xt,
696 MISCREG_DC_ISW_Xt,
697 MISCREG_AT_S1E1R_Xt,
698 MISCREG_AT_S1E1W_Xt,
699 MISCREG_AT_S1E0R_Xt,
700 MISCREG_AT_S1E0W_Xt,
701 MISCREG_DC_CSW_Xt,
702 MISCREG_DC_CISW_Xt,
703 MISCREG_DC_ZVA_Xt,
704 MISCREG_IC_IVAU_Xt,
705 MISCREG_DC_CVAC_Xt,
706 MISCREG_DC_CVAU_Xt,
707 MISCREG_DC_CIVAC_Xt,
708 MISCREG_AT_S1E2R_Xt,
709 MISCREG_AT_S1E2W_Xt,
710 MISCREG_AT_S12E1R_Xt,
711 MISCREG_AT_S12E1W_Xt,
712 MISCREG_AT_S12E0R_Xt,
713 MISCREG_AT_S12E0W_Xt,
714 MISCREG_AT_S1E3R_Xt,
715 MISCREG_AT_S1E3W_Xt,
716 TLBI_VARIANTS(MISCREG_TLBI_VMALLE1IS),
717 TLBI_VARIANTS(MISCREG_TLBI_VMALLE1OS),
718 TLBI_VARIANTS(MISCREG_TLBI_VAE1IS),
719 TLBI_VARIANTS(MISCREG_TLBI_VAE1OS),
720 TLBI_VARIANTS(MISCREG_TLBI_ASIDE1IS),
721 TLBI_VARIANTS(MISCREG_TLBI_ASIDE1OS),
722 TLBI_VARIANTS(MISCREG_TLBI_VAAE1IS),
723 TLBI_VARIANTS(MISCREG_TLBI_VAAE1OS),
724 TLBI_VARIANTS(MISCREG_TLBI_VALE1IS),
725 TLBI_VARIANTS(MISCREG_TLBI_VALE1OS),
726 TLBI_VARIANTS(MISCREG_TLBI_VAALE1IS),
727 TLBI_VARIANTS(MISCREG_TLBI_VAALE1OS),
728 TLBI_VARIANTS(MISCREG_TLBI_VMALLE1),
729 TLBI_VARIANTS(MISCREG_TLBI_VAE1),
730 TLBI_VARIANTS(MISCREG_TLBI_ASIDE1),
731 TLBI_VARIANTS(MISCREG_TLBI_VAAE1),
732 TLBI_VARIANTS(MISCREG_TLBI_VALE1),
733 TLBI_VARIANTS(MISCREG_TLBI_VAALE1),
734 TLBI_VARIANTS(MISCREG_TLBI_IPAS2E1IS),
735 TLBI_VARIANTS(MISCREG_TLBI_IPAS2E1OS),
736 TLBI_VARIANTS(MISCREG_TLBI_IPAS2LE1IS),
737 TLBI_VARIANTS(MISCREG_TLBI_IPAS2LE1OS),
738 TLBI_VARIANTS(MISCREG_TLBI_ALLE2IS),
739 TLBI_VARIANTS(MISCREG_TLBI_ALLE2OS),
740 TLBI_VARIANTS(MISCREG_TLBI_VAE2IS),
741 TLBI_VARIANTS(MISCREG_TLBI_VAE2OS),
742 TLBI_VARIANTS(MISCREG_TLBI_ALLE1IS),
743 TLBI_VARIANTS(MISCREG_TLBI_ALLE1OS),
744 TLBI_VARIANTS(MISCREG_TLBI_VALE2IS),
745 TLBI_VARIANTS(MISCREG_TLBI_VALE2OS),
746 TLBI_VARIANTS(MISCREG_TLBI_VMALLS12E1IS),
747 TLBI_VARIANTS(MISCREG_TLBI_VMALLS12E1OS),
748 TLBI_VARIANTS(MISCREG_TLBI_IPAS2E1),
749 TLBI_VARIANTS(MISCREG_TLBI_IPAS2LE1),
750 TLBI_VARIANTS(MISCREG_TLBI_ALLE2),
751 TLBI_VARIANTS(MISCREG_TLBI_VAE2),
752 TLBI_VARIANTS(MISCREG_TLBI_ALLE1),
753 TLBI_VARIANTS(MISCREG_TLBI_VALE2),
754 TLBI_VARIANTS(MISCREG_TLBI_VMALLS12E1),
755 TLBI_VARIANTS(MISCREG_TLBI_ALLE3IS),
756 TLBI_VARIANTS(MISCREG_TLBI_ALLE3OS),
757 TLBI_VARIANTS(MISCREG_TLBI_VAE3IS),
758 TLBI_VARIANTS(MISCREG_TLBI_VAE3OS),
759 TLBI_VARIANTS(MISCREG_TLBI_VALE3IS),
760 TLBI_VARIANTS(MISCREG_TLBI_VALE3OS),
761 TLBI_VARIANTS(MISCREG_TLBI_ALLE3),
762 TLBI_VARIANTS(MISCREG_TLBI_VAE3),
763 TLBI_VARIANTS(MISCREG_TLBI_VALE3),
764 TLBI_VARIANTS(MISCREG_TLBI_RVAE1),
765 TLBI_VARIANTS(MISCREG_TLBI_RVAAE1),
766 TLBI_VARIANTS(MISCREG_TLBI_RVALE1),
767 TLBI_VARIANTS(MISCREG_TLBI_RVAALE1),
768 TLBI_VARIANTS(MISCREG_TLBI_RIPAS2E1),
769 TLBI_VARIANTS(MISCREG_TLBI_RIPAS2LE1),
770 TLBI_VARIANTS(MISCREG_TLBI_RVAE2),
771 TLBI_VARIANTS(MISCREG_TLBI_RVALE2),
772 TLBI_VARIANTS(MISCREG_TLBI_RVAE3),
773 TLBI_VARIANTS(MISCREG_TLBI_RVALE3),
774 TLBI_VARIANTS(MISCREG_TLBI_RVAE1IS),
775 TLBI_VARIANTS(MISCREG_TLBI_RVAAE1IS),
776 TLBI_VARIANTS(MISCREG_TLBI_RVALE1IS),
777 TLBI_VARIANTS(MISCREG_TLBI_RVAALE1IS),
778 TLBI_VARIANTS(MISCREG_TLBI_RIPAS2E1IS),
779 TLBI_VARIANTS(MISCREG_TLBI_RIPAS2LE1IS),
780 TLBI_VARIANTS(MISCREG_TLBI_RVAE2IS),
781 TLBI_VARIANTS(MISCREG_TLBI_RVALE2IS),
782 TLBI_VARIANTS(MISCREG_TLBI_RVAE3IS),
783 TLBI_VARIANTS(MISCREG_TLBI_RVALE3IS),
784 TLBI_VARIANTS(MISCREG_TLBI_RVAE1OS),
785 TLBI_VARIANTS(MISCREG_TLBI_RVAAE1OS),
786 TLBI_VARIANTS(MISCREG_TLBI_RVALE1OS),
787 TLBI_VARIANTS(MISCREG_TLBI_RVAALE1OS),
788 TLBI_VARIANTS(MISCREG_TLBI_RIPAS2E1OS),
789 TLBI_VARIANTS(MISCREG_TLBI_RIPAS2LE1OS),
790 TLBI_VARIANTS(MISCREG_TLBI_RVAE2OS),
791 TLBI_VARIANTS(MISCREG_TLBI_RVALE2OS),
792 TLBI_VARIANTS(MISCREG_TLBI_RVAE3OS),
793 TLBI_VARIANTS(MISCREG_TLBI_RVALE3OS),
794 MISCREG_PMINTENSET_EL1,
795 MISCREG_PMINTENCLR_EL1,
796 MISCREG_PMCR_EL0,
797 MISCREG_PMCNTENSET_EL0,
798 MISCREG_PMCNTENCLR_EL0,
799 MISCREG_PMOVSCLR_EL0,
800 MISCREG_PMSWINC_EL0,
801 MISCREG_PMSELR_EL0,
802 MISCREG_PMCEID0_EL0,
803 MISCREG_PMCEID1_EL0,
804 MISCREG_PMCCNTR_EL0,
805 MISCREG_PMXEVTYPER_EL0,
806 MISCREG_PMCCFILTR_EL0,
807 MISCREG_PMXEVCNTR_EL0,
808 MISCREG_PMUSERENR_EL0,
809 MISCREG_PMOVSSET_EL0,
810 MISCREG_MAIR_EL1,
811 MISCREG_MAIR_EL12,
812 MISCREG_AMAIR_EL1,
813 MISCREG_AMAIR_EL12,
814 MISCREG_MAIR_EL2,
815 MISCREG_AMAIR_EL2,
816 MISCREG_MAIR_EL3,
817 MISCREG_AMAIR_EL3,
818 MISCREG_L2CTLR_EL1,
819 MISCREG_L2ECTLR_EL1,
820 MISCREG_VBAR_EL1,
821 MISCREG_VBAR_EL12,
822 MISCREG_RVBAR_EL1,
823 MISCREG_ISR_EL1,
824 MISCREG_VBAR_EL2,
825 MISCREG_RVBAR_EL2,
826 MISCREG_VBAR_EL3,
827 MISCREG_RVBAR_EL3,
828 MISCREG_RMR_EL3,
829 MISCREG_CONTEXTIDR_EL1,
830 MISCREG_CONTEXTIDR_EL12,
831 MISCREG_TPIDR_EL1,
832 MISCREG_TPIDR_EL0,
833 MISCREG_TPIDRRO_EL0,
834 MISCREG_TPIDR_EL2,
835 MISCREG_TPIDR_EL3,
836 // BEGIN Generic Timer (AArch64)
837 MISCREG_CNTFRQ_EL0,
838 MISCREG_CNTPCT_EL0,
839 MISCREG_CNTVCT_EL0,
840 MISCREG_CNTP_CTL_EL0,
841 MISCREG_CNTP_CVAL_EL0,
842 MISCREG_CNTP_TVAL_EL0,
843 MISCREG_CNTV_CTL_EL0,
844 MISCREG_CNTV_CVAL_EL0,
845 MISCREG_CNTV_TVAL_EL0,
846 MISCREG_CNTP_CTL_EL02,
847 MISCREG_CNTP_CVAL_EL02,
848 MISCREG_CNTP_TVAL_EL02,
849 MISCREG_CNTV_CTL_EL02,
850 MISCREG_CNTV_CVAL_EL02,
851 MISCREG_CNTV_TVAL_EL02,
852 MISCREG_CNTKCTL_EL1,
853 MISCREG_CNTKCTL_EL12,
854 MISCREG_CNTPS_CTL_EL1,
855 MISCREG_CNTPS_CVAL_EL1,
856 MISCREG_CNTPS_TVAL_EL1,
857 MISCREG_CNTHCTL_EL2,
858 MISCREG_CNTHP_CTL_EL2,
859 MISCREG_CNTHP_CVAL_EL2,
860 MISCREG_CNTHP_TVAL_EL2,
861 MISCREG_CNTHPS_CTL_EL2,
862 MISCREG_CNTHPS_CVAL_EL2,
863 MISCREG_CNTHPS_TVAL_EL2,
864 // IF Armv8.1-VHE
865 MISCREG_CNTHV_CTL_EL2,
866 MISCREG_CNTHV_CVAL_EL2,
867 MISCREG_CNTHV_TVAL_EL2,
868 MISCREG_CNTHVS_CTL_EL2,
869 MISCREG_CNTHVS_CVAL_EL2,
870 MISCREG_CNTHVS_TVAL_EL2,
871 // ENDIF Armv8.1-VHE
872 MISCREG_CNTVOFF_EL2,
873 // END Generic Timer (AArch64)
874 MISCREG_PMEVCNTR0_EL0,
875 MISCREG_PMEVCNTR1_EL0,
876 MISCREG_PMEVCNTR2_EL0,
877 MISCREG_PMEVCNTR3_EL0,
878 MISCREG_PMEVCNTR4_EL0,
879 MISCREG_PMEVCNTR5_EL0,
880 MISCREG_PMEVTYPER0_EL0,
881 MISCREG_PMEVTYPER1_EL0,
882 MISCREG_PMEVTYPER2_EL0,
883 MISCREG_PMEVTYPER3_EL0,
884 MISCREG_PMEVTYPER4_EL0,
885 MISCREG_PMEVTYPER5_EL0,
886 MISCREG_IL1DATA0_EL1,
887 MISCREG_IL1DATA1_EL1,
888 MISCREG_IL1DATA2_EL1,
889 MISCREG_IL1DATA3_EL1,
890 MISCREG_DL1DATA0_EL1,
891 MISCREG_DL1DATA1_EL1,
892 MISCREG_DL1DATA2_EL1,
893 MISCREG_DL1DATA3_EL1,
894 MISCREG_DL1DATA4_EL1,
895 MISCREG_L2ACTLR_EL1,
896 MISCREG_CPUACTLR_EL1,
897 MISCREG_CPUECTLR_EL1,
898 MISCREG_CPUMERRSR_EL1,
899 MISCREG_L2MERRSR_EL1,
900 MISCREG_CBAR_EL1,
901 MISCREG_CONTEXTIDR_EL2,
902
903 // Introduced in ARMv8.1
904 MISCREG_TTBR1_EL2,
905
906 MISCREG_ID_AA64MMFR2_EL1,
907 MISCREG_ID_AA64MMFR3_EL1,
908
909 //PAuth Key Regsiters
910 MISCREG_APDAKeyHi_EL1,
911 MISCREG_APDAKeyLo_EL1,
912 MISCREG_APDBKeyHi_EL1,
913 MISCREG_APDBKeyLo_EL1,
914 MISCREG_APGAKeyHi_EL1,
915 MISCREG_APGAKeyLo_EL1,
916 MISCREG_APIAKeyHi_EL1,
917 MISCREG_APIAKeyLo_EL1,
918 MISCREG_APIBKeyHi_EL1,
919 MISCREG_APIBKeyLo_EL1,
920
921 // GICv3, CPU interface
922 MISCREG_ICC_PMR_EL1,
923 MISCREG_ICC_IAR0_EL1,
924 MISCREG_ICC_EOIR0_EL1,
925 MISCREG_ICC_HPPIR0_EL1,
926 MISCREG_ICC_BPR0_EL1,
927 MISCREG_ICC_AP0R0_EL1,
928 MISCREG_ICC_AP0R1_EL1,
929 MISCREG_ICC_AP0R2_EL1,
930 MISCREG_ICC_AP0R3_EL1,
931 MISCREG_ICC_AP1R0_EL1,
932 MISCREG_ICC_AP1R0_EL1_NS,
933 MISCREG_ICC_AP1R0_EL1_S,
934 MISCREG_ICC_AP1R1_EL1,
935 MISCREG_ICC_AP1R1_EL1_NS,
936 MISCREG_ICC_AP1R1_EL1_S,
937 MISCREG_ICC_AP1R2_EL1,
938 MISCREG_ICC_AP1R2_EL1_NS,
939 MISCREG_ICC_AP1R2_EL1_S,
940 MISCREG_ICC_AP1R3_EL1,
941 MISCREG_ICC_AP1R3_EL1_NS,
942 MISCREG_ICC_AP1R3_EL1_S,
943 MISCREG_ICC_DIR_EL1,
944 MISCREG_ICC_RPR_EL1,
945 MISCREG_ICC_SGI1R_EL1,
946 MISCREG_ICC_ASGI1R_EL1,
947 MISCREG_ICC_SGI0R_EL1,
948 MISCREG_ICC_IAR1_EL1,
949 MISCREG_ICC_EOIR1_EL1,
950 MISCREG_ICC_HPPIR1_EL1,
951 MISCREG_ICC_BPR1_EL1,
952 MISCREG_ICC_BPR1_EL1_NS,
953 MISCREG_ICC_BPR1_EL1_S,
954 MISCREG_ICC_CTLR_EL1,
955 MISCREG_ICC_CTLR_EL1_NS,
956 MISCREG_ICC_CTLR_EL1_S,
957 MISCREG_ICC_SRE_EL1,
958 MISCREG_ICC_SRE_EL1_NS,
959 MISCREG_ICC_SRE_EL1_S,
960 MISCREG_ICC_IGRPEN0_EL1,
961 MISCREG_ICC_IGRPEN1_EL1,
962 MISCREG_ICC_IGRPEN1_EL1_NS,
963 MISCREG_ICC_IGRPEN1_EL1_S,
964 MISCREG_ICC_SRE_EL2,
965 MISCREG_ICC_CTLR_EL3,
966 MISCREG_ICC_SRE_EL3,
967 MISCREG_ICC_IGRPEN1_EL3,
968
969 // GICv3, CPU interface, virtualization
970 MISCREG_ICH_AP0R0_EL2,
971 MISCREG_ICH_AP0R1_EL2,
972 MISCREG_ICH_AP0R2_EL2,
973 MISCREG_ICH_AP0R3_EL2,
974 MISCREG_ICH_AP1R0_EL2,
975 MISCREG_ICH_AP1R1_EL2,
976 MISCREG_ICH_AP1R2_EL2,
977 MISCREG_ICH_AP1R3_EL2,
978 MISCREG_ICH_HCR_EL2,
979 MISCREG_ICH_VTR_EL2,
980 MISCREG_ICH_MISR_EL2,
981 MISCREG_ICH_EISR_EL2,
982 MISCREG_ICH_ELRSR_EL2,
983 MISCREG_ICH_VMCR_EL2,
984 MISCREG_ICH_LR0_EL2,
985 MISCREG_ICH_LR1_EL2,
986 MISCREG_ICH_LR2_EL2,
987 MISCREG_ICH_LR3_EL2,
988 MISCREG_ICH_LR4_EL2,
989 MISCREG_ICH_LR5_EL2,
990 MISCREG_ICH_LR6_EL2,
991 MISCREG_ICH_LR7_EL2,
992 MISCREG_ICH_LR8_EL2,
993 MISCREG_ICH_LR9_EL2,
994 MISCREG_ICH_LR10_EL2,
995 MISCREG_ICH_LR11_EL2,
996 MISCREG_ICH_LR12_EL2,
997 MISCREG_ICH_LR13_EL2,
998 MISCREG_ICH_LR14_EL2,
999 MISCREG_ICH_LR15_EL2,
1000
1001 MISCREG_ICV_PMR_EL1,
1002 MISCREG_ICV_IAR0_EL1,
1003 MISCREG_ICV_EOIR0_EL1,
1004 MISCREG_ICV_HPPIR0_EL1,
1005 MISCREG_ICV_BPR0_EL1,
1006 MISCREG_ICV_AP0R0_EL1,
1007 MISCREG_ICV_AP0R1_EL1,
1008 MISCREG_ICV_AP0R2_EL1,
1009 MISCREG_ICV_AP0R3_EL1,
1010 MISCREG_ICV_AP1R0_EL1,
1011 MISCREG_ICV_AP1R0_EL1_NS,
1012 MISCREG_ICV_AP1R0_EL1_S,
1013 MISCREG_ICV_AP1R1_EL1,
1014 MISCREG_ICV_AP1R1_EL1_NS,
1015 MISCREG_ICV_AP1R1_EL1_S,
1016 MISCREG_ICV_AP1R2_EL1,
1017 MISCREG_ICV_AP1R2_EL1_NS,
1018 MISCREG_ICV_AP1R2_EL1_S,
1019 MISCREG_ICV_AP1R3_EL1,
1020 MISCREG_ICV_AP1R3_EL1_NS,
1021 MISCREG_ICV_AP1R3_EL1_S,
1022 MISCREG_ICV_DIR_EL1,
1023 MISCREG_ICV_RPR_EL1,
1024 MISCREG_ICV_SGI1R_EL1,
1025 MISCREG_ICV_ASGI1R_EL1,
1026 MISCREG_ICV_SGI0R_EL1,
1027 MISCREG_ICV_IAR1_EL1,
1028 MISCREG_ICV_EOIR1_EL1,
1029 MISCREG_ICV_HPPIR1_EL1,
1030 MISCREG_ICV_BPR1_EL1,
1031 MISCREG_ICV_BPR1_EL1_NS,
1032 MISCREG_ICV_BPR1_EL1_S,
1033 MISCREG_ICV_CTLR_EL1,
1034 MISCREG_ICV_CTLR_EL1_NS,
1035 MISCREG_ICV_CTLR_EL1_S,
1036 MISCREG_ICV_SRE_EL1,
1037 MISCREG_ICV_SRE_EL1_NS,
1038 MISCREG_ICV_SRE_EL1_S,
1039 MISCREG_ICV_IGRPEN0_EL1,
1040 MISCREG_ICV_IGRPEN1_EL1,
1041 MISCREG_ICV_IGRPEN1_EL1_NS,
1042 MISCREG_ICV_IGRPEN1_EL1_S,
1043
1044 MISCREG_ICC_AP0R0,
1045 MISCREG_ICC_AP0R1,
1046 MISCREG_ICC_AP0R2,
1047 MISCREG_ICC_AP0R3,
1048 MISCREG_ICC_AP1R0,
1049 MISCREG_ICC_AP1R0_NS,
1050 MISCREG_ICC_AP1R0_S,
1051 MISCREG_ICC_AP1R1,
1052 MISCREG_ICC_AP1R1_NS,
1053 MISCREG_ICC_AP1R1_S,
1054 MISCREG_ICC_AP1R2,
1055 MISCREG_ICC_AP1R2_NS,
1056 MISCREG_ICC_AP1R2_S,
1057 MISCREG_ICC_AP1R3,
1058 MISCREG_ICC_AP1R3_NS,
1059 MISCREG_ICC_AP1R3_S,
1060 MISCREG_ICC_ASGI1R,
1061 MISCREG_ICC_BPR0,
1062 MISCREG_ICC_BPR1,
1063 MISCREG_ICC_BPR1_NS,
1064 MISCREG_ICC_BPR1_S,
1065 MISCREG_ICC_CTLR,
1066 MISCREG_ICC_CTLR_NS,
1067 MISCREG_ICC_CTLR_S,
1068 MISCREG_ICC_DIR,
1069 MISCREG_ICC_EOIR0,
1070 MISCREG_ICC_EOIR1,
1071 MISCREG_ICC_HPPIR0,
1072 MISCREG_ICC_HPPIR1,
1073 MISCREG_ICC_HSRE,
1074 MISCREG_ICC_IAR0,
1075 MISCREG_ICC_IAR1,
1076 MISCREG_ICC_IGRPEN0,
1077 MISCREG_ICC_IGRPEN1,
1078 MISCREG_ICC_IGRPEN1_NS,
1079 MISCREG_ICC_IGRPEN1_S,
1080 MISCREG_ICC_MCTLR,
1081 MISCREG_ICC_MGRPEN1,
1082 MISCREG_ICC_MSRE,
1083 MISCREG_ICC_PMR,
1084 MISCREG_ICC_RPR,
1085 MISCREG_ICC_SGI0R,
1086 MISCREG_ICC_SGI1R,
1087 MISCREG_ICC_SRE,
1088 MISCREG_ICC_SRE_NS,
1089 MISCREG_ICC_SRE_S,
1090
1091 MISCREG_ICH_AP0R0,
1092 MISCREG_ICH_AP0R1,
1093 MISCREG_ICH_AP0R2,
1094 MISCREG_ICH_AP0R3,
1095 MISCREG_ICH_AP1R0,
1096 MISCREG_ICH_AP1R1,
1097 MISCREG_ICH_AP1R2,
1098 MISCREG_ICH_AP1R3,
1099 MISCREG_ICH_HCR,
1100 MISCREG_ICH_VTR,
1101 MISCREG_ICH_MISR,
1102 MISCREG_ICH_EISR,
1103 MISCREG_ICH_ELRSR,
1104 MISCREG_ICH_VMCR,
1105 MISCREG_ICH_LR0,
1106 MISCREG_ICH_LR1,
1107 MISCREG_ICH_LR2,
1108 MISCREG_ICH_LR3,
1109 MISCREG_ICH_LR4,
1110 MISCREG_ICH_LR5,
1111 MISCREG_ICH_LR6,
1112 MISCREG_ICH_LR7,
1113 MISCREG_ICH_LR8,
1114 MISCREG_ICH_LR9,
1115 MISCREG_ICH_LR10,
1116 MISCREG_ICH_LR11,
1117 MISCREG_ICH_LR12,
1118 MISCREG_ICH_LR13,
1119 MISCREG_ICH_LR14,
1120 MISCREG_ICH_LR15,
1121 MISCREG_ICH_LRC0,
1122 MISCREG_ICH_LRC1,
1123 MISCREG_ICH_LRC2,
1124 MISCREG_ICH_LRC3,
1125 MISCREG_ICH_LRC4,
1126 MISCREG_ICH_LRC5,
1127 MISCREG_ICH_LRC6,
1128 MISCREG_ICH_LRC7,
1129 MISCREG_ICH_LRC8,
1130 MISCREG_ICH_LRC9,
1131 MISCREG_ICH_LRC10,
1132 MISCREG_ICH_LRC11,
1133 MISCREG_ICH_LRC12,
1134 MISCREG_ICH_LRC13,
1135 MISCREG_ICH_LRC14,
1136 MISCREG_ICH_LRC15,
1137
1138 // SVE
1139 MISCREG_ID_AA64ZFR0_EL1,
1140 MISCREG_ZCR_EL3,
1141 MISCREG_ZCR_EL2,
1142 MISCREG_ZCR_EL12,
1143 MISCREG_ZCR_EL1,
1144
1145 // SME
1146 MISCREG_ID_AA64SMFR0_EL1,
1147 MISCREG_SVCR,
1148 MISCREG_SMIDR_EL1,
1149 MISCREG_SMPRI_EL1,
1150 MISCREG_SMPRIMAP_EL2,
1151 MISCREG_SMCR_EL3,
1152 MISCREG_SMCR_EL2,
1153 MISCREG_SMCR_EL12,
1154 MISCREG_SMCR_EL1,
1155 MISCREG_TPIDR2_EL0,
1156 MISCREG_MPAMSM_EL1,
1157
1158 // FEAT_RNG
1159 MISCREG_RNDR,
1160 MISCREG_RNDRRS,
1161
1162 // FEAT_FGT
1163 MISCREG_HFGITR_EL2,
1164 MISCREG_HFGRTR_EL2,
1165 MISCREG_HFGWTR_EL2,
1166 MISCREG_HDFGRTR_EL2,
1167 MISCREG_HDFGWTR_EL2,
1168 MISCREG_HAFGRTR_EL2,
1169
1170 // FEAT_MPAM
1171 MISCREG_MPAMIDR_EL1,
1172 MISCREG_MPAM0_EL1,
1173 MISCREG_MPAM1_EL1,
1174 MISCREG_MPAM2_EL2,
1175 MISCREG_MPAM3_EL3,
1176 MISCREG_MPAM1_EL12,
1177 MISCREG_MPAMHCR_EL2,
1178 MISCREG_MPAMVPMV_EL2,
1179 MISCREG_MPAMVPM0_EL2,
1180 MISCREG_MPAMVPM1_EL2,
1181 MISCREG_MPAMVPM2_EL2,
1182 MISCREG_MPAMVPM3_EL2,
1183 MISCREG_MPAMVPM4_EL2,
1184 MISCREG_MPAMVPM5_EL2,
1185 MISCREG_MPAMVPM6_EL2,
1186 MISCREG_MPAMVPM7_EL2,
1187
1188 // NUM_PHYS_MISCREGS specifies the number of actual physical
1189 // registers, not considering the following pseudo-registers
1190 // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
1191 // Checkpointing should use this physical index when
1192 // saving/restoring register values.
1193 NUM_PHYS_MISCREGS,
1194
1195 // Dummy registers
1196 MISCREG_NOP,
1197 MISCREG_RAZ,
1198 MISCREG_UNKNOWN,
1199
1200 // Implementation defined register: this represent
1201 // a pool of unimplemented registers whose access can throw
1202 // either UNDEFINED or hypervisor trap exception.
1203 MISCREG_IMPDEF_UNIMPL,
1204
1205 // RAS extension (unimplemented)
1206 MISCREG_ERRIDR_EL1,
1207 MISCREG_ERRSELR_EL1,
1208 MISCREG_ERXFR_EL1,
1209 MISCREG_ERXCTLR_EL1,
1210 MISCREG_ERXSTATUS_EL1,
1211 MISCREG_ERXADDR_EL1,
1212 MISCREG_ERXMISC0_EL1,
1213 MISCREG_ERXMISC1_EL1,
1214 MISCREG_DISR_EL1,
1215 MISCREG_VSESR_EL2,
1216 MISCREG_VDISR_EL2,
1217
1218 // PSTATE
1219 MISCREG_PAN,
1220 MISCREG_UAO,
1221
1222 // Total number of Misc Registers: Physical + Dummy
1223 NUM_MISCREGS
1224 };
1225
1226 enum MiscRegInfo
1227 {
1228 MISCREG_IMPLEMENTED,
1229 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
1230 // arch generic counter)
1231 MISCREG_UNSERIALIZE, // Should the checkpointed value be restored?
1232 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
1233 // tells whether the instruction should raise a
1234 // warning or fail
1235 MISCREG_MUTEX, // True if the register corresponds to a pair of
1236 // mutually exclusive registers
1237 MISCREG_BANKED, // True if the register is banked between the two
1238 // security states, and this is the parent node of the
1239 // two banked registers
1240 MISCREG_BANKED64, // True if the register is banked between the two
1241 // security states, and this is the parent node of
1242 // the two banked registers. Used in AA64 only.
1243 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
1244 // forms a banked set of regs (along with the
1245 // other child regs)
1246
1247 // Access permissions
1248 // User mode
1249 MISCREG_USR_NS_RD,
1250 MISCREG_USR_NS_WR,
1251 MISCREG_USR_S_RD,
1252 MISCREG_USR_S_WR,
1253 // Privileged modes other than hypervisor or monitor
1254 MISCREG_PRI_NS_RD,
1255 MISCREG_PRI_NS_WR,
1256 MISCREG_PRI_S_RD,
1257 MISCREG_PRI_S_WR,
1258 // Hypervisor mode
1259 MISCREG_HYP_NS_RD,
1260 MISCREG_HYP_NS_WR,
1261 MISCREG_HYP_S_RD,
1262 MISCREG_HYP_S_WR,
1263 // Monitor mode, SCR.NS == 0
1264 MISCREG_MON_NS0_RD,
1265 MISCREG_MON_NS0_WR,
1266 // Monitor mode, SCR.NS == 1
1267 MISCREG_MON_NS1_RD,
1268 MISCREG_MON_NS1_WR,
1269
1270 NUM_MISCREG_INFOS
1271 };
1272
1274 struct MiscRegLUTEntry
1275 {
1276 uint32_t lower; // Lower half mapped to this register
1277 uint32_t upper; // Upper half mapped to this register
1278 uint64_t _reset; // value taken on reset (i.e. initialization)
1279 uint64_t _res0; // reserved
1280 uint64_t _res1; // reserved
1281 uint64_t _raz; // read as zero (fixed at 0)
1282 uint64_t _rao; // read as one (fixed at 1)
1283 std::bitset<NUM_MISCREG_INFOS> info;
1284
1285 using FaultCB = std::function<
1286 Fault(const MiscRegLUTEntry &entry, ThreadContext *tc,
1287 const MiscRegOp64 &inst)
1288 >;
1289
1290 std::array<FaultCB, EL3 + 1> faultRead;
1291 std::array<FaultCB, EL3 + 1> faultWrite;
1292
1293 Fault checkFault(ThreadContext *tc, const MiscRegOp64 &inst,
1294 ExceptionLevel el);
1295
1296 protected:
1297 template <MiscRegInfo Sec, MiscRegInfo NonSec>
1298 static Fault defaultFault(const MiscRegLUTEntry &entry,
1299 ThreadContext *tc, const MiscRegOp64 &inst);
1300
1301 public:
1302 MiscRegLUTEntry() :
1303 lower(0), upper(0),
1304 _reset(0), _res0(0), _res1(0), _raz(0), _rao(0), info(0),
1305 faultRead({defaultFault<MISCREG_USR_S_RD, MISCREG_USR_NS_RD>,
1306 defaultFault<MISCREG_PRI_S_RD, MISCREG_PRI_NS_RD>,
1307 defaultFault<MISCREG_HYP_S_RD, MISCREG_HYP_NS_RD>,
1308 defaultFault<MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD>}),
1309 faultWrite({defaultFault<MISCREG_USR_S_WR, MISCREG_USR_NS_WR>,
1310 defaultFault<MISCREG_PRI_S_WR, MISCREG_PRI_NS_WR>,
1311 defaultFault<MISCREG_HYP_S_WR, MISCREG_HYP_NS_WR>,
1312 defaultFault<MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR>})
1313 {}
1314 uint64_t reset() const { return _reset; }
1315 uint64_t res0() const { return _res0; }
1316 uint64_t res1() const { return _res1; }
1317 uint64_t raz() const { return _raz; }
1318 uint64_t rao() const { return _rao; }
1319 // raz/rao implies writes ignored
1320 uint64_t wi() const { return _raz | _rao; }
1321 };
1322
1324 class MiscRegLUTEntryInitializer
1325 {
1326 struct MiscRegLUTEntry &entry;
1327 typedef const MiscRegLUTEntryInitializer& chain;
1328 public:
1329 chain
1330 mapsTo(uint32_t l, uint32_t u = 0) const
1331 {
1332 entry.lower = l;
1333 entry.upper = u;
1334 return *this;
1335 }
1336 chain
1337 reset(uint64_t res_val) const
1338 {
1339 entry._reset = res_val;
1340 return *this;
1341 }
1342 chain
1343 res0(uint64_t mask) const
1344 {
1345 entry._res0 = mask;
1346 return *this;
1347 }
1348 chain
1349 res1(uint64_t mask) const
1350 {
1351 entry._res1 = mask;
1352 return *this;
1353 }
1354 chain
1355 raz(uint64_t mask = (uint64_t)-1) const
1356 {
1357 entry._raz = mask;
1358 return *this;
1359 }
1360 chain
1361 rao(uint64_t mask = (uint64_t)-1) const
1362 {
1363 entry._rao = mask;
1364 return *this;
1365 }
1366 chain
1367 implemented(bool v = true) const
1368 {
1369 entry.info[MISCREG_IMPLEMENTED] = v;
1370 return *this;
1371 }
1372 chain
1373 unimplemented() const
1374 {
1375 return implemented(false);
1376 }
1377 chain
1378 unverifiable(bool v = true) const
1379 {
1380 entry.info[MISCREG_UNVERIFIABLE] = v;
1381 return *this;
1382 }
1383 chain
1384 unserialize(bool v = true) const
1385 {
1386 entry.info[MISCREG_UNSERIALIZE] = v;
1387 return *this;
1388 }
1389 chain
1390 warnNotFail(bool v = true) const
1391 {
1392 entry.info[MISCREG_WARN_NOT_FAIL] = v;
1393 return *this;
1394 }
1395 chain
1396 mutex(bool v = true) const
1397 {
1398 entry.info[MISCREG_MUTEX] = v;
1399 return *this;
1400 }
1401 chain
1402 banked(bool v = true) const
1403 {
1404 entry.info[MISCREG_BANKED] = v;
1405 return *this;
1406 }
1407 chain
1408 banked64(bool v = true) const
1409 {
1410 entry.info[MISCREG_BANKED64] = v;
1411 return *this;
1412 }
1413 chain
1414 bankedChild(bool v = true) const
1415 {
1416 entry.info[MISCREG_BANKED_CHILD] = v;
1417 return *this;
1418 }
1419 chain
1420 userNonSecureRead(bool v = true) const
1421 {
1422 entry.info[MISCREG_USR_NS_RD] = v;
1423 return *this;
1424 }
1425 chain
1426 userNonSecureWrite(bool v = true) const
1427 {
1428 entry.info[MISCREG_USR_NS_WR] = v;
1429 return *this;
1430 }
1431 chain
1432 userSecureRead(bool v = true) const
1433 {
1434 entry.info[MISCREG_USR_S_RD] = v;
1435 return *this;
1436 }
1437 chain
1438 userSecureWrite(bool v = true) const
1439 {
1440 entry.info[MISCREG_USR_S_WR] = v;
1441 return *this;
1442 }
1443 chain
1444 user(bool v = true) const
1445 {
1446 userNonSecureRead(v);
1447 userNonSecureWrite(v);
1448 userSecureRead(v);
1449 userSecureWrite(v);
1450 return *this;
1451 }
1452 chain
1453 privNonSecureRead(bool v = true) const
1454 {
1455 entry.info[MISCREG_PRI_NS_RD] = v;
1456 return *this;
1457 }
1458 chain
1459 privNonSecureWrite(bool v = true) const
1460 {
1461 entry.info[MISCREG_PRI_NS_WR] = v;
1462 return *this;
1463 }
1464 chain
1465 privNonSecure(bool v = true) const
1466 {
1467 privNonSecureRead(v);
1468 privNonSecureWrite(v);
1469 return *this;
1470 }
1471 chain
1472 privSecureRead(bool v = true) const
1473 {
1474 entry.info[MISCREG_PRI_S_RD] = v;
1475 return *this;
1476 }
1477 chain
1478 privSecureWrite(bool v = true) const
1479 {
1480 entry.info[MISCREG_PRI_S_WR] = v;
1481 return *this;
1482 }
1483 chain
1484 privSecure(bool v = true) const
1485 {
1486 privSecureRead(v);
1487 privSecureWrite(v);
1488 return *this;
1489 }
1490 chain
1491 priv(bool v = true) const
1492 {
1493 privSecure(v);
1494 privNonSecure(v);
1495 return *this;
1496 }
1497 chain
1498 privRead(bool v = true) const
1499 {
1500 privSecureRead(v);
1501 privNonSecureRead(v);
1502 return *this;
1503 }
1504 chain
1505 hypSecureRead(bool v = true) const
1506 {
1507 entry.info[MISCREG_HYP_S_RD] = v;
1508 return *this;
1509 }
1510 chain
1511 hypNonSecureRead(bool v = true) const
1512 {
1513 entry.info[MISCREG_HYP_NS_RD] = v;
1514 return *this;
1515 }
1516 chain
1517 hypRead(bool v = true) const
1518 {
1519 hypSecureRead(v);
1520 hypNonSecureRead(v);
1521 return *this;
1522 }
1523 chain
1524 hypSecureWrite(bool v = true) const
1525 {
1526 entry.info[MISCREG_HYP_S_WR] = v;
1527 return *this;
1528 }
1529 chain
1530 hypNonSecureWrite(bool v = true) const
1531 {
1532 entry.info[MISCREG_HYP_NS_WR] = v;
1533 return *this;
1534 }
1535 chain
1536 hypWrite(bool v = true) const
1537 {
1538 hypSecureWrite(v);
1539 hypNonSecureWrite(v);
1540 return *this;
1541 }
1542 chain
1543 hypSecure(bool v = true) const
1544 {
1545 hypSecureRead(v);
1546 hypSecureWrite(v);
1547 return *this;
1548 }
1549 chain
1550 hyp(bool v = true) const
1551 {
1552 hypRead(v);
1553 hypWrite(v);
1554 return *this;
1555 }
1556 chain
1557 monSecureRead(bool v = true) const
1558 {
1559 entry.info[MISCREG_MON_NS0_RD] = v;
1560 return *this;
1561 }
1562 chain
1563 monSecureWrite(bool v = true) const
1564 {
1565 entry.info[MISCREG_MON_NS0_WR] = v;
1566 return *this;
1567 }
1568 chain
1569 monNonSecureRead(bool v = true) const
1570 {
1571 entry.info[MISCREG_MON_NS1_RD] = v;
1572 return *this;
1573 }
1574 chain
1575 monNonSecureWrite(bool v = true) const
1576 {
1577 entry.info[MISCREG_MON_NS1_WR] = v;
1578 return *this;
1579 }
1580 chain
1581 mon(bool v = true) const
1582 {
1583 monSecureRead(v);
1584 monSecureWrite(v);
1585 monNonSecureRead(v);
1586 monNonSecureWrite(v);
1587 return *this;
1588 }
1589 chain
1590 monWrite(bool v = true) const
1591 {
1592 monSecureWrite(v);
1593 monNonSecureWrite(v);
1594 return *this;
1595 }
1596 chain
1597 monSecure(bool v = true) const
1598 {
1599 monSecureRead(v);
1600 monSecureWrite(v);
1601 return *this;
1602 }
1603 chain
1604 monNonSecure(bool v = true) const
1605 {
1606 monNonSecureRead(v);
1607 monNonSecureWrite(v);
1608 return *this;
1609 }
1610 chain
1611 allPrivileges(bool v = true) const
1612 {
1613 userNonSecureRead(v);
1614 userNonSecureWrite(v);
1615 userSecureRead(v);
1616 userSecureWrite(v);
1617 privNonSecureRead(v);
1618 privNonSecureWrite(v);
1619 privSecureRead(v);
1620 privSecureWrite(v);
1621 hypRead(v);
1622 hypWrite(v);
1623 monSecureRead(v);
1624 monSecureWrite(v);
1625 monNonSecureRead(v);
1626 monNonSecureWrite(v);
1627 return *this;
1628 }
1629 chain
1630 nonSecure(bool v = true) const
1631 {
1632 userNonSecureRead(v);
1633 userNonSecureWrite(v);
1634 privNonSecureRead(v);
1635 privNonSecureWrite(v);
1636 hypRead(v);
1637 hypWrite(v);
1638 monNonSecureRead(v);
1639 monNonSecureWrite(v);
1640 return *this;
1641 }
1642 chain
1643 secure(bool v = true) const
1644 {
1645 userSecureRead(v);
1646 userSecureWrite(v);
1647 privSecureRead(v);
1648 privSecureWrite(v);
1649 monSecureRead(v);
1650 monSecureWrite(v);
1651 return *this;
1652 }
1653 chain
1654 reads(bool v) const
1655 {
1656 userNonSecureRead(v);
1657 userSecureRead(v);
1658 privNonSecureRead(v);
1659 privSecureRead(v);
1660 hypRead(v);
1661 monSecureRead(v);
1662 monNonSecureRead(v);
1663 return *this;
1664 }
1665 chain
1666 writes(bool v) const
1667 {
1668 userNonSecureWrite(v);
1669 userSecureWrite(v);
1670 privNonSecureWrite(v);
1671 privSecureWrite(v);
1672 hypWrite(v);
1673 monSecureWrite(v);
1674 monNonSecureWrite(v);
1675 return *this;
1676 }
1677 chain
1678 exceptUserMode() const
1679 {
1680 user(0);
1681 return *this;
1682 }
1683 chain highest(ArmSystem *const sys) const;
1684
1685 chain
1686 faultRead(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
1687 {
1688 entry.faultRead[el] = cb;
1689 return *this;
1690 }
1691
1692 chain
1693 faultWrite(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
1694 {
1695 entry.faultWrite[el] = cb;
1696 return *this;
1697 }
1698
1699 chain
1700 fault(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
1701 {
1702 return faultRead(el, cb).faultWrite(el, cb);
1703 }
1704
1705 chain
1706 fault(MiscRegLUTEntry::FaultCB cb) const
1707 {
1708 return fault(EL0, cb).fault(EL1, cb).fault(EL2, cb).fault(EL3, cb);
1709 }
1710
1711 MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
1712 : entry(e)
1713 {
1714 // force unimplemented registers to be thusly declared
1715 implemented(1).unserialize(1);
1716 }
1717 };
1718
1719 extern std::vector<struct MiscRegLUTEntry> lookUpMiscReg;
1720
1721 struct MiscRegNum32
1722 {
1723 MiscRegNum32(unsigned _coproc, unsigned _opc1,
1724 unsigned _crn, unsigned _crm,
1725 unsigned _opc2)
1726 : reg64(0), coproc(_coproc), opc1(_opc1), crn(_crn),
1727 crm(_crm), opc2(_opc2)
1728 {
1729 // MCR/MRC CP14 or CP15 register
1730 assert(coproc == 0b1110 || coproc == 0b1111);
1731 assert(opc1 < 8 && crn < 16 && crm < 16 && opc2 < 8);
1732 }
1733
1734 MiscRegNum32(unsigned _coproc, unsigned _opc1,
1735 unsigned _crm)
1736 : reg64(1), coproc(_coproc), opc1(_opc1), crn(0),
1737 crm(_crm), opc2(0)
1738 {
1739 // MCRR/MRRC CP14 or CP15 register
1740 assert(coproc == 0b1110 || coproc == 0b1111);
1741 assert(opc1 < 16 && crm < 16);
1742 }
1743
1744 MiscRegNum32(const MiscRegNum32& rhs) = default;
1745
1746 bool
1747 operator==(const MiscRegNum32 &other) const
1748 {
1749 return reg64 == other.reg64 &&
1750 coproc == other.coproc &&
1751 opc1 == other.opc1 &&
1752 crn == other.crn &&
1753 crm == other.crm &&
1754 opc2 == other.opc2;
1755 }
1756
1757 uint32_t
1758 packed() const
1759 {
1760 return reg64 << 19 |
1761 coproc << 15 |
1762 opc1 << 11 |
1763 crn << 7 |
1764 crm << 3 |
1765 opc2;
1766 }
1767
1768 // 1 if the register is 64bit wide (accessed through MCRR/MRCC)
1769 // 0 otherwise. We need this when generating the hash as there
1770 // might be collisions between 32 and 64 bit registers
1771 const unsigned reg64;
1772
1773 unsigned coproc;
1774 unsigned opc1;
1775 unsigned crn;
1776 unsigned crm;
1777 unsigned opc2;
1778 };
1779
1780 struct MiscRegNum64
1781 {
1782 MiscRegNum64(unsigned _op0, unsigned _op1,
1783 unsigned _crn, unsigned _crm,
1784 unsigned _op2)
1785 : op0(_op0), op1(_op1), crn(_crn),
1786 crm(_crm), op2(_op2)
1787 {
1788 assert(op0 < 4 && op1 < 8 && crn < 16 && crm < 16 && op2 < 8);
1789 }
1790
1791 MiscRegNum64(const MiscRegNum64& rhs) = default;
1792
1793 bool
1794 operator==(const MiscRegNum64 &other) const
1795 {
1796 return op0 == other.op0 &&
1797 op1 == other.op1 &&
1798 crn == other.crn &&
1799 crm == other.crm &&
1800 op2 == other.op2;
1801 }
1802
1803 uint32_t
1804 packed() const
1805 {
1806 return op0 << 14 |
1807 op1 << 11 |
1808 crn << 7 |
1809 crm << 3 |
1810 op2;
1811 }
1812
1813 unsigned op0;
1814 unsigned op1;
1815 unsigned crn;
1816 unsigned crm;
1817 unsigned op2;
1818 };
1819
1820 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
1821 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
1822 unsigned crm, unsigned opc2);
1823 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
1824 unsigned crn, unsigned crm,
1825 unsigned op2);
1826 MiscRegIndex decodeAArch64SysReg(const MiscRegNum64 &misc_reg);
1827 std::optional<MiscRegNum64> encodeAArch64SysReg(MiscRegIndex misc_reg);
1828
1829 // Whether a particular AArch64 system register is -always- read only.
1830 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
1831
1832 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
1833 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
1834 unsigned crm, unsigned opc2);
1835
1836 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
1837 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
1838
1839
1840 const char * const miscRegName[] = {
1841 "cpsr",
1842 "spsr",
1843 "spsr_fiq",
1844 "spsr_irq",
1845 "spsr_svc",
1846 "spsr_mon",
1847 "spsr_abt",
1848 "spsr_hyp",
1849 "spsr_und",
1850 "elr_hyp",
1851 "fpsid",
1852 "fpscr",
1853 "mvfr1",
1854 "mvfr0",
1855 "fpexc",
1856
1857 // Helper registers
1858 "cpsr_mode",
1859 "cpsr_q",
1860 "fpscr_exc",
1861 "fpscr_qc",
1862 "lockaddr",
1863 "lockflag",
1864 "prrr_mair0",
1865 "prrr_mair0_ns",
1866 "prrr_mair0_s",
1867 "nmrr_mair1",
1868 "nmrr_mair1_ns",
1869 "nmrr_mair1_s",
1870 "pmxevtyper_pmccfiltr",
1871 "sev_mailbox",
1872 "tlbi_needsync",
1873
1874 // AArch32 CP14 registers
1875 "dbgdidr",
1876 "dbgdscrint",
1877 "dbgdccint",
1878 "dbgdtrtxint",
1879 "dbgdtrrxint",
1880 "dbgwfar",
1881 "dbgvcr",
1882 "dbgdtrrxext",
1883 "dbgdscrext",
1884 "dbgdtrtxext",
1885 "dbgoseccr",
1886 "dbgbvr0",
1887 "dbgbvr1",
1888 "dbgbvr2",
1889 "dbgbvr3",
1890 "dbgbvr4",
1891 "dbgbvr5",
1892 "dbgbvr6",
1893 "dbgbvr7",
1894 "dbgbvr8",
1895 "dbgbvr9",
1896 "dbgbvr10",
1897 "dbgbvr11",
1898 "dbgbvr12",
1899 "dbgbvr13",
1900 "dbgbvr14",
1901 "dbgbvr15",
1902 "dbgbcr0",
1903 "dbgbcr1",
1904 "dbgbcr2",
1905 "dbgbcr3",
1906 "dbgbcr4",
1907 "dbgbcr5",
1908 "dbgbcr6",
1909 "dbgbcr7",
1910 "dbgbcr8",
1911 "dbgbcr9",
1912 "dbgbcr10",
1913 "dbgbcr11",
1914 "dbgbcr12",
1915 "dbgbcr13",
1916 "dbgbcr14",
1917 "dbgbcr15",
1918 "dbgwvr0",
1919 "dbgwvr1",
1920 "dbgwvr2",
1921 "dbgwvr3",
1922 "dbgwvr4",
1923 "dbgwvr5",
1924 "dbgwvr6",
1925 "dbgwvr7",
1926 "dbgwvr8",
1927 "dbgwvr9",
1928 "dbgwvr10",
1929 "dbgwvr11",
1930 "dbgwvr12",
1931 "dbgwvr13",
1932 "dbgwvr14",
1933 "dbgwvr15",
1934 "dbgwcr0",
1935 "dbgwcr1",
1936 "dbgwcr2",
1937 "dbgwcr3",
1938 "dbgwcr4",
1939 "dbgwcr5",
1940 "dbgwcr6",
1941 "dbgwcr7",
1942 "dbgwcr8",
1943 "dbgwcr9",
1944 "dbgwcr10",
1945 "dbgwcr11",
1946 "dbgwcr12",
1947 "dbgwcr13",
1948 "dbgwcr14",
1949 "dbgwcr15",
1950 "dbgdrar",
1951 "dbgbxvr0",
1952 "dbgbxvr1",
1953 "dbgbxvr2",
1954 "dbgbxvr3",
1955 "dbgbxvr4",
1956 "dbgbxvr5",
1957 "dbgbxvr6",
1958 "dbgbxvr7",
1959 "dbgbxvr8",
1960 "dbgbxvr9",
1961 "dbgbxvr10",
1962 "dbgbxvr11",
1963 "dbgbxvr12",
1964 "dbgbxvr13",
1965 "dbgbxvr14",
1966 "dbgbxvr15",
1967 "dbgoslar",
1968 "dbgoslsr",
1969 "dbgosdlr",
1970 "dbgprcr",
1971 "dbgdsar",
1972 "dbgclaimset",
1973 "dbgclaimclr",
1974 "dbgauthstatus",
1975 "dbgdevid2",
1976 "dbgdevid1",
1977 "dbgdevid0",
1978 "teecr",
1979 "jidr",
1980 "teehbr",
1981 "joscr",
1982 "jmcr",
1983
1984 // AArch32 CP15 registers
1985 "midr",
1986 "ctr",
1987 "tcmtr",
1988 "tlbtr",
1989 "mpidr",
1990 "revidr",
1991 "id_pfr0",
1992 "id_pfr1",
1993 "id_dfr0",
1994 "id_afr0",
1995 "id_mmfr0",
1996 "id_mmfr1",
1997 "id_mmfr2",
1998 "id_mmfr3",
1999 "id_mmfr4",
2000 "id_isar0",
2001 "id_isar1",
2002 "id_isar2",
2003 "id_isar3",
2004 "id_isar4",
2005 "id_isar5",
2006 "id_isar6",
2007 "ccsidr",
2008 "clidr",
2009 "aidr",
2010 "csselr",
2011 "csselr_ns",
2012 "csselr_s",
2013 "vpidr",
2014 "vmpidr",
2015 "sctlr",
2016 "sctlr_ns",
2017 "sctlr_s",
2018 "actlr",
2019 "actlr_ns",
2020 "actlr_s",
2021 "cpacr",
2022 "sdcr",
2023 "scr",
2024 "sder",
2025 "nsacr",
2026 "hsctlr",
2027 "hactlr",
2028 "hcr",
2029 "hcr2",
2030 "hdcr",
2031 "hcptr",
2032 "hstr",
2033 "hacr",
2034 "ttbr0",
2035 "ttbr0_ns",
2036 "ttbr0_s",
2037 "ttbr1",
2038 "ttbr1_ns",
2039 "ttbr1_s",
2040 "ttbcr",
2041 "ttbcr_ns",
2042 "ttbcr_s",
2043 "htcr",
2044 "vtcr",
2045 "dacr",
2046 "dacr_ns",
2047 "dacr_s",
2048 "dfsr",
2049 "dfsr_ns",
2050 "dfsr_s",
2051 "ifsr",
2052 "ifsr_ns",
2053 "ifsr_s",
2054 "adfsr",
2055 "adfsr_ns",
2056 "adfsr_s",
2057 "aifsr",
2058 "aifsr_ns",
2059 "aifsr_s",
2060 "hadfsr",
2061 "haifsr",
2062 "hsr",
2063 "dfar",
2064 "dfar_ns",
2065 "dfar_s",
2066 "ifar",
2067 "ifar_ns",
2068 "ifar_s",
2069 "hdfar",
2070 "hifar",
2071 "hpfar",
2072 "icialluis",
2073 "bpiallis",
2074 "par",
2075 "par_ns",
2076 "par_s",
2077 "iciallu",
2078 "icimvau",
2079 "cp15isb",
2080 "bpiall",
2081 "bpimva",
2082 "dcimvac",
2083 "dcisw",
2084 "ats1cpr",
2085 "ats1cpw",
2086 "ats1cur",
2087 "ats1cuw",
2088 "ats12nsopr",
2089 "ats12nsopw",
2090 "ats12nsour",
2091 "ats12nsouw",
2092 "dccmvac",
2093 "dccsw",
2094 "cp15dsb",
2095 "cp15dmb",
2096 "dccmvau",
2097 "dccimvac",
2098 "dccisw",
2099 "ats1hr",
2100 "ats1hw",
2101 "tlbiallis",
2102 "tlbimvais",
2103 "tlbiasidis",
2104 "tlbimvaais",
2105 "tlbimvalis",
2106 "tlbimvaalis",
2107 "itlbiall",
2108 "itlbimva",
2109 "itlbiasid",
2110 "dtlbiall",
2111 "dtlbimva",
2112 "dtlbiasid",
2113 "tlbiall",
2114 "tlbimva",
2115 "tlbiasid",
2116 "tlbimvaa",
2117 "tlbimval",
2118 "tlbimvaal",
2119 "tlbiipas2is",
2120 "tlbiipas2lis",
2121 "tlbiallhis",
2122 "tlbimvahis",
2123 "tlbiallnsnhis",
2124 "tlbimvalhis",
2125 "tlbiipas2",
2126 "tlbiipas2l",
2127 "tlbiallh",
2128 "tlbimvah",
2129 "tlbiallnsnh",
2130 "tlbimvalh",
2131 "pmcr",
2132 "pmcntenset",
2133 "pmcntenclr",
2134 "pmovsr",
2135 "pmswinc",
2136 "pmselr",
2137 "pmceid0",
2138 "pmceid1",
2139 "pmccntr",
2140 "pmxevtyper",
2141 "pmevcntr0",
2142 "pmevcntr1",
2143 "pmevcntr2",
2144 "pmevcntr3",
2145 "pmevcntr4",
2146 "pmevcntr5",
2147 "pmevtyper0",
2148 "pmevtyper1",
2149 "pmevtyper2",
2150 "pmevtyper3",
2151 "pmevtyper4",
2152 "pmevtyper5",
2153 "pmccfiltr",
2154 "pmxevcntr",
2155 "pmuserenr",
2156 "pmintenset",
2157 "pmintenclr",
2158 "pmovsset",
2159 "l2ctlr",
2160 "l2ectlr",
2161 "prrr",
2162 "prrr_ns",
2163 "prrr_s",
2164 "mair0",
2165 "mair0_ns",
2166 "mair0_s",
2167 "nmrr",
2168 "nmrr_ns",
2169 "nmrr_s",
2170 "mair1",
2171 "mair1_ns",
2172 "mair1_s",
2173 "amair0",
2174 "amair0_ns",
2175 "amair0_s",
2176 "amair1",
2177 "amair1_ns",
2178 "amair1_s",
2179 "hmair0",
2180 "hmair1",
2181 "hamair0",
2182 "hamair1",
2183 "vbar",
2184 "vbar_ns",
2185 "vbar_s",
2186 "mvbar",
2187 "rmr",
2188 "isr",
2189 "hvbar",
2190 "fcseidr",
2191 "contextidr",
2192 "contextidr_ns",
2193 "contextidr_s",
2194 "tpidrurw",
2195 "tpidrurw_ns",
2196 "tpidrurw_s",
2197 "tpidruro",
2198 "tpidruro_ns",
2199 "tpidruro_s",
2200 "tpidrprw",
2201 "tpidrprw_ns",
2202 "tpidrprw_s",
2203 "htpidr",
2204 "cntfrq",
2205 "cntpct",
2206 "cntvct",
2207 "cntp_ctl",
2208 "cntp_ctl_ns",
2209 "cntp_ctl_s",
2210 "cntp_cval",
2211 "cntp_cval_ns",
2212 "cntp_cval_s",
2213 "cntp_tval",
2214 "cntp_tval_ns",
2215 "cntp_tval_s",
2216 "cntv_ctl",
2217 "cntv_cval",
2218 "cntv_tval",
2219 "cntkctl",
2220 "cnthctl",
2221 "cnthp_ctl",
2222 "cnthp_cval",
2223 "cnthp_tval",
2224 "cntvoff",
2225 "il1data0",
2226 "il1data1",
2227 "il1data2",
2228 "il1data3",
2229 "dl1data0",
2230 "dl1data1",
2231 "dl1data2",
2232 "dl1data3",
2233 "dl1data4",
2234 "ramindex",
2235 "l2actlr",
2236 "cbar",
2237 "httbr",
2238 "vttbr",
2239 "cpumerrsr",
2240 "l2merrsr",
2241
2242 // AArch64 registers (Op0=2)
2243 "mdccint_el1",
2244 "osdtrrx_el1",
2245 "mdscr_el1",
2246 "osdtrtx_el1",
2247 "oseccr_el1",
2248 "dbgbvr0_el1",
2249 "dbgbvr1_el1",
2250 "dbgbvr2_el1",
2251 "dbgbvr3_el1",
2252 "dbgbvr4_el1",
2253 "dbgbvr5_el1",
2254 "dbgbvr6_el1",
2255 "dbgbvr7_el1",
2256 "dbgbvr8_el1",
2257 "dbgbvr9_el1",
2258 "dbgbvr10_el1",
2259 "dbgbvr11_el1",
2260 "dbgbvr12_el1",
2261 "dbgbvr13_el1",
2262 "dbgbvr14_el1",
2263 "dbgbvr15_el1",
2264 "dbgbcr0_el1",
2265 "dbgbcr1_el1",
2266 "dbgbcr2_el1",
2267 "dbgbcr3_el1",
2268 "dbgbcr4_el1",
2269 "dbgbcr5_el1",
2270 "dbgbcr6_el1",
2271 "dbgbcr7_el1",
2272 "dbgbcr8_el1",
2273 "dbgbcr9_el1",
2274 "dbgbcr10_el1",
2275 "dbgbcr11_el1",
2276 "dbgbcr12_el1",
2277 "dbgbcr13_el1",
2278 "dbgbcr14_el1",
2279 "dbgbcr15_el1",
2280 "dbgwvr0_el1",
2281 "dbgwvr1_el1",
2282 "dbgwvr2_el1",
2283 "dbgwvr3_el1",
2284 "dbgwvr4_el1",
2285 "dbgwvr5_el1",
2286 "dbgwvr6_el1",
2287 "dbgwvr7_el1",
2288 "dbgwvr8_el1",
2289 "dbgwvr9_el1",
2290 "dbgwvr10_el1",
2291 "dbgwvr11_el1",
2292 "dbgwvr12_el1",
2293 "dbgwvr13_el1",
2294 "dbgwvr14_el1",
2295 "dbgwvr15_el1",
2296 "dbgwcr0_el1",
2297 "dbgwcr1_el1",
2298 "dbgwcr2_el1",
2299 "dbgwcr3_el1",
2300 "dbgwcr4_el1",
2301 "dbgwcr5_el1",
2302 "dbgwcr6_el1",
2303 "dbgwcr7_el1",
2304 "dbgwcr8_el1",
2305 "dbgwcr9_el1",
2306 "dbgwcr10_el1",
2307 "dbgwcr11_el1",
2308 "dbgwcr12_el1",
2309 "dbgwcr13_el1",
2310 "dbgwcr14_el1",
2311 "dbgwcr15_el1",
2312 "mdccsr_el0",
2313 "mddtr_el0",
2314 "mddtrtx_el0",
2315 "mddtrrx_el0",
2316 "dbgvcr32_el2",
2317 "mdrar_el1",
2318 "oslar_el1",
2319 "oslsr_el1",
2320 "osdlr_el1",
2321 "dbgprcr_el1",
2322 "dbgclaimset_el1",
2323 "dbgclaimclr_el1",
2324 "dbgauthstatus_el1",
2325 "teecr32_el1",
2326 "teehbr32_el1",
2327
2328 // AArch64 registers (Op0=1,3)
2329 "midr_el1",
2330 "mpidr_el1",
2331 "revidr_el1",
2332 "id_pfr0_el1",
2333 "id_pfr1_el1",
2334 "id_dfr0_el1",
2335 "id_afr0_el1",
2336 "id_mmfr0_el1",
2337 "id_mmfr1_el1",
2338 "id_mmfr2_el1",
2339 "id_mmfr3_el1",
2340 "id_mmfr4_el1",
2341 "id_isar0_el1",
2342 "id_isar1_el1",
2343 "id_isar2_el1",
2344 "id_isar3_el1",
2345 "id_isar4_el1",
2346 "id_isar5_el1",
2347 "id_isar6_el1",
2348 "mvfr0_el1",
2349 "mvfr1_el1",
2350 "mvfr2_el1",
2351 "id_aa64pfr0_el1",
2352 "id_aa64pfr1_el1",
2353 "id_aa64dfr0_el1",
2354 "id_aa64dfr1_el1",
2355 "id_aa64afr0_el1",
2356 "id_aa64afr1_el1",
2357 "id_aa64isar0_el1",
2358 "id_aa64isar1_el1",
2359 "id_aa64mmfr0_el1",
2360 "id_aa64mmfr1_el1",
2361 "ccsidr_el1",
2362 "clidr_el1",
2363 "aidr_el1",
2364 "csselr_el1",
2365 "ctr_el0",
2366 "dczid_el0",
2367 "vpidr_el2",
2368 "vmpidr_el2",
2369 "sctlr_el1",
2370 "sctlr_el12",
2371 "sctlr2_el1",
2372 "sctlr2_el12",
2373 "actlr_el1",
2374 "cpacr_el1",
2375 "cpacr_el12",
2376 "sctlr_el2",
2377 "sctlr2_el2",
2378 "actlr_el2",
2379 "hcr_el2",
2380 "hcrx_el2",
2381 "mdcr_el2",
2382 "cptr_el2",
2383 "hstr_el2",
2384 "hacr_el2",
2385 "sctlr_el3",
2386 "sctlr2_el3",
2387 "actlr_el3",
2388 "scr_el3",
2389 "sder32_el3",
2390 "cptr_el3",
2391 "mdcr_el3",
2392 "ttbr0_el1",
2393 "ttbr0_el12",
2394 "ttbr1_el1",
2395 "ttbr1_el12",
2396 "tcr_el1",
2397 "tcr_el12",
2398 "tcr2_el1",
2399 "tcr2_el12",
2400 "ttbr0_el2",
2401 "tcr_el2",
2402 "tcr2_el2",
2403 "vttbr_el2",
2404 "vtcr_el2",
2405 "vsttbr_el2",
2406 "vstcr_el2",
2407 "ttbr0_el3",
2408 "tcr_el3",
2409 "dacr32_el2",
2410 "spsr_el1",
2411 "spsr_el12",
2412 "elr_el1",
2413 "elr_el12",
2414 "sp_el0",
2415 "spsel",
2416 "currentel",
2417 "nzcv",
2418 "daif",
2419 "fpcr",
2420 "fpsr",
2421 "dspsr_el0",
2422 "dlr_el0",
2423 "spsr_el2",
2424 "elr_el2",
2425 "sp_el1",
2426 "spsr_irq_aa64",
2427 "spsr_abt_aa64",
2428 "spsr_und_aa64",
2429 "spsr_fiq_aa64",
2430 "spsr_el3",
2431 "elr_el3",
2432 "sp_el2",
2433 "afsr0_el1",
2434 "afsr0_el12",
2435 "afsr1_el1",
2436 "afsr1_el12",
2437 "esr_el1",
2438 "esr_el12",
2439 "ifsr32_el2",
2440 "afsr0_el2",
2441 "afsr1_el2",
2442 "esr_el2",
2443 "fpexc32_el2",
2444 "afsr0_el3",
2445 "afsr1_el3",
2446 "esr_el3",
2447 "far_el1",
2448 "far_el12",
2449 "far_el2",
2450 "hpfar_el2",
2451 "far_el3",
2452 "ic_ialluis",
2453 "par_el1",
2454 "ic_iallu",
2455 "dc_ivac_xt",
2456 "dc_isw_xt",
2457 "at_s1e1r_xt",
2458 "at_s1e1w_xt",
2459 "at_s1e0r_xt",
2460 "at_s1e0w_xt",
2461 "dc_csw_xt",
2462 "dc_cisw_xt",
2463 "dc_zva_xt",
2464 "ic_ivau_xt",
2465 "dc_cvac_xt",
2466 "dc_cvau_xt",
2467 "dc_civac_xt",
2468 "at_s1e2r_xt",
2469 "at_s1e2w_xt",
2470 "at_s12e1r_xt",
2471 "at_s12e1w_xt",
2472 "at_s12e0r_xt",
2473 "at_s12e0w_xt",
2474 "at_s1e3r_xt",
2475 "at_s1e3w_xt",
2476 TLBI_STR_VARIANTS(tlbi_vmalle1is),
2477 TLBI_STR_VARIANTS(tlbi_vmalle1os),
2478 TLBI_STR_VARIANTS(tlbi_vae1is),
2479 TLBI_STR_VARIANTS(tlbi_vae1os),
2480 TLBI_STR_VARIANTS(lbi_aside1is_xt),
2481 TLBI_STR_VARIANTS(tlbi_aside1os),
2482 TLBI_STR_VARIANTS(tlbi_vaae1is),
2483 TLBI_STR_VARIANTS(tlbi_vaae1os),
2484 TLBI_STR_VARIANTS(tlbi_vale1is),
2485 TLBI_STR_VARIANTS(tlbi_vale1os),
2486 TLBI_STR_VARIANTS(tlbi_vaale1is),
2487 TLBI_STR_VARIANTS(tlbi_vaale1os),
2488 TLBI_STR_VARIANTS(tlbi_vmalle1),
2489 TLBI_STR_VARIANTS(tlbi_vae1),
2490 TLBI_STR_VARIANTS(tlbi_aside1),
2491 TLBI_STR_VARIANTS(tlbi_vaae1),
2492 TLBI_STR_VARIANTS(tlbi_vale1),
2493 TLBI_STR_VARIANTS(tlbi_vaale1),
2494 TLBI_STR_VARIANTS(tlbi_ipas2e1is),
2495 TLBI_STR_VARIANTS(tlbi_ipas2e1os),
2496 TLBI_STR_VARIANTS(tlbi_ipas2le1is),
2497 TLBI_STR_VARIANTS(tlbi_ipas2le1os),
2498 TLBI_STR_VARIANTS(tlbi_alle2is),
2499 TLBI_STR_VARIANTS(tlbi_alle2os),
2500 TLBI_STR_VARIANTS(tlbi_vae2is),
2501 TLBI_STR_VARIANTS(tlbi_vae2os),
2502 TLBI_STR_VARIANTS(tlbi_alle1is),
2503 TLBI_STR_VARIANTS(tlbi_alle1os),
2504 TLBI_STR_VARIANTS(tlbi_vale2is),
2505 TLBI_STR_VARIANTS(tlbi_vale2os),
2506 TLBI_STR_VARIANTS(tlbi_vmalls12e1is),
2507 TLBI_STR_VARIANTS(tlbi_vmalls12e1os),
2508 TLBI_STR_VARIANTS(tlbi_ipas2e1),
2509 TLBI_STR_VARIANTS(tlbi_ipas2le1),
2510 TLBI_STR_VARIANTS(tlbi_alle2),
2511 TLBI_STR_VARIANTS(tlbi_vae2),
2512 TLBI_STR_VARIANTS(tlbi_alle1),
2513 TLBI_STR_VARIANTS(tlbi_vale2),
2514 TLBI_STR_VARIANTS(tlbi_vmalls12e1),
2515 TLBI_STR_VARIANTS(tlbi_alle3is),
2516 TLBI_STR_VARIANTS(tlbi_alle3os),
2517 TLBI_STR_VARIANTS(tlbi_vae3is),
2518 TLBI_STR_VARIANTS(tlbi_vae3os),
2519 TLBI_STR_VARIANTS(tlbi_vale3is),
2520 TLBI_STR_VARIANTS(tlbi_vale3os),
2521 TLBI_STR_VARIANTS(tlbi_alle3),
2522 TLBI_STR_VARIANTS(tlbi_vae3),
2523 TLBI_STR_VARIANTS(tlbi_vale3),
2524 TLBI_STR_VARIANTS(tlbi_rvae1),
2525 TLBI_STR_VARIANTS(tlbi_rvaae1),
2526 TLBI_STR_VARIANTS(tlbi_rvale1),
2527 TLBI_STR_VARIANTS(tlbi_rvaale1),
2528 TLBI_STR_VARIANTS(tlbi_ripas2e1),
2529 TLBI_STR_VARIANTS(tlbi_ripas2le1),
2530 TLBI_STR_VARIANTS(tlbi_rvae2),
2531 TLBI_STR_VARIANTS(tlbi_rvale2),
2532 TLBI_STR_VARIANTS(tlbi_rvae3),
2533 TLBI_STR_VARIANTS(tlbi_rvale3),
2534 TLBI_STR_VARIANTS(tlbi_rvae1is),
2535 TLBI_STR_VARIANTS(tlbi_rvaae1is),
2536 TLBI_STR_VARIANTS(tlbi_rvale1is),
2537 TLBI_STR_VARIANTS(tlbi_rvaale1is),
2538 TLBI_STR_VARIANTS(tlbi_ripas2e1is),
2539 TLBI_STR_VARIANTS(tlbi_ripas2le1is),
2540 TLBI_STR_VARIANTS(tlbi_rvae2is),
2541 TLBI_STR_VARIANTS(tlbi_rvale2is),
2542 TLBI_STR_VARIANTS(tlbi_rvae3is),
2543 TLBI_STR_VARIANTS(tlbi_rvale3is),
2544 TLBI_STR_VARIANTS(tlbi_rvae1os),
2545 TLBI_STR_VARIANTS(tlbi_rvaae1os),
2546 TLBI_STR_VARIANTS(tlbi_rvale1os),
2547 TLBI_STR_VARIANTS(tlbi_rvaale1os),
2548 TLBI_STR_VARIANTS(tlbi_ripas2e1os),
2549 TLBI_STR_VARIANTS(tlbi_ripas2le1os),
2550 TLBI_STR_VARIANTS(tlbi_rvae2os),
2551 TLBI_STR_VARIANTS(tlbi_rvale2os),
2552 TLBI_STR_VARIANTS(tlbi_rvae3os),
2553 TLBI_STR_VARIANTS(tlbi_rvale3os),
2554 "pmintenset_el1",
2555 "pmintenclr_el1",
2556 "pmcr_el0",
2557 "pmcntenset_el0",
2558 "pmcntenclr_el0",
2559 "pmovsclr_el0",
2560 "pmswinc_el0",
2561 "pmselr_el0",
2562 "pmceid0_el0",
2563 "pmceid1_el0",
2564 "pmccntr_el0",
2565 "pmxevtyper_el0",
2566 "pmccfiltr_el0",
2567 "pmxevcntr_el0",
2568 "pmuserenr_el0",
2569 "pmovsset_el0",
2570 "mair_el1",
2571 "mair_el12",
2572 "amair_el1",
2573 "amair_el12",
2574 "mair_el2",
2575 "amair_el2",
2576 "mair_el3",
2577 "amair_el3",
2578 "l2ctlr_el1",
2579 "l2ectlr_el1",
2580 "vbar_el1",
2581 "vbar_el12",
2582 "rvbar_el1",
2583 "isr_el1",
2584 "vbar_el2",
2585 "rvbar_el2",
2586 "vbar_el3",
2587 "rvbar_el3",
2588 "rmr_el3",
2589 "contextidr_el1",
2590 "contextidr_el12",
2591 "tpidr_el1",
2592 "tpidr_el0",
2593 "tpidrro_el0",
2594 "tpidr_el2",
2595 "tpidr_el3",
2596 "cntfrq_el0",
2597 "cntpct_el0",
2598 "cntvct_el0",
2599 "cntp_ctl_el0",
2600 "cntp_cval_el0",
2601 "cntp_tval_el0",
2602 "cntv_ctl_el0",
2603 "cntv_cval_el0",
2604 "cntv_tval_el0",
2605 "cntp_ctl_el02",
2606 "cntp_cval_el02",
2607 "cntp_tval_el02",
2608 "cntv_ctl_el02",
2609 "cntv_cval_el02",
2610 "cntv_tval_el02",
2611 "cntkctl_el1",
2612 "cntkctl_el12",
2613 "cntps_ctl_el1",
2614 "cntps_cval_el1",
2615 "cntps_tval_el1",
2616 "cnthctl_el2",
2617 "cnthp_ctl_el2",
2618 "cnthp_cval_el2",
2619 "cnthp_tval_el2",
2620 "cnthps_ctl_el2",
2621 "cnthps_cval_el2",
2622 "cnthps_tval_el2",
2623 "cnthv_ctl_el2",
2624 "cnthv_cval_el2",
2625 "cnthv_tval_el2",
2626 "cnthvs_ctl_el2",
2627 "cnthvs_cval_el2",
2628 "cnthvs_tval_el2",
2629 "cntvoff_el2",
2630 "pmevcntr0_el0",
2631 "pmevcntr1_el0",
2632 "pmevcntr2_el0",
2633 "pmevcntr3_el0",
2634 "pmevcntr4_el0",
2635 "pmevcntr5_el0",
2636 "pmevtyper0_el0",
2637 "pmevtyper1_el0",
2638 "pmevtyper2_el0",
2639 "pmevtyper3_el0",
2640 "pmevtyper4_el0",
2641 "pmevtyper5_el0",
2642 "il1data0_el1",
2643 "il1data1_el1",
2644 "il1data2_el1",
2645 "il1data3_el1",
2646 "dl1data0_el1",
2647 "dl1data1_el1",
2648 "dl1data2_el1",
2649 "dl1data3_el1",
2650 "dl1data4_el1",
2651 "l2actlr_el1",
2652 "cpuactlr_el1",
2653 "cpuectlr_el1",
2654 "cpumerrsr_el1",
2655 "l2merrsr_el1",
2656 "cbar_el1",
2657 "contextidr_el2",
2658
2659 "ttbr1_el2",
2660 "id_aa64mmfr2_el1",
2661 "id_aa64mmfr3_el1",
2662
2663 "apdakeyhi_el1",
2664 "apdakeylo_el1",
2665 "apdbkeyhi_el1",
2666 "apdbkeylo_el1",
2667 "apgakeyhi_el1",
2668 "apgakeylo_el1",
2669 "apiakeyhi_el1",
2670 "apiakeylo_el1",
2671 "apibkeyhi_el1",
2672 "apibkeylo_el1",
2673 // GICv3, CPU interface
2674 "icc_pmr_el1",
2675 "icc_iar0_el1",
2676 "icc_eoir0_el1",
2677 "icc_hppir0_el1",
2678 "icc_bpr0_el1",
2679 "icc_ap0r0_el1",
2680 "icc_ap0r1_el1",
2681 "icc_ap0r2_el1",
2682 "icc_ap0r3_el1",
2683 "icc_ap1r0_el1",
2684 "icc_ap1r0_el1_ns",
2685 "icc_ap1r0_el1_s",
2686 "icc_ap1r1_el1",
2687 "icc_ap1r1_el1_ns",
2688 "icc_ap1r1_el1_s",
2689 "icc_ap1r2_el1",
2690 "icc_ap1r2_el1_ns",
2691 "icc_ap1r2_el1_s",
2692 "icc_ap1r3_el1",
2693 "icc_ap1r3_el1_ns",
2694 "icc_ap1r3_el1_s",
2695 "icc_dir_el1",
2696 "icc_rpr_el1",
2697 "icc_sgi1r_el1",
2698 "icc_asgi1r_el1",
2699 "icc_sgi0r_el1",
2700 "icc_iar1_el1",
2701 "icc_eoir1_el1",
2702 "icc_hppir1_el1",
2703 "icc_bpr1_el1",
2704 "icc_bpr1_el1_ns",
2705 "icc_bpr1_el1_s",
2706 "icc_ctlr_el1",
2707 "icc_ctlr_el1_ns",
2708 "icc_ctlr_el1_s",
2709 "icc_sre_el1",
2710 "icc_sre_el1_ns",
2711 "icc_sre_el1_s",
2712 "icc_igrpen0_el1",
2713 "icc_igrpen1_el1",
2714 "icc_igrpen1_el1_ns",
2715 "icc_igrpen1_el1_s",
2716 "icc_sre_el2",
2717 "icc_ctlr_el3",
2718 "icc_sre_el3",
2719 "icc_igrpen1_el3",
2720
2721 // GICv3, CPU interface, virtualization
2722 "ich_ap0r0_el2",
2723 "ich_ap0r1_el2",
2724 "ich_ap0r2_el2",
2725 "ich_ap0r3_el2",
2726 "ich_ap1r0_el2",
2727 "ich_ap1r1_el2",
2728 "ich_ap1r2_el2",
2729 "ich_ap1r3_el2",
2730 "ich_hcr_el2",
2731 "ich_vtr_el2",
2732 "ich_misr_el2",
2733 "ich_eisr_el2",
2734 "ich_elrsr_el2",
2735 "ich_vmcr_el2",
2736 "ich_lr0_el2",
2737 "ich_lr1_el2",
2738 "ich_lr2_el2",
2739 "ich_lr3_el2",
2740 "ich_lr4_el2",
2741 "ich_lr5_el2",
2742 "ich_lr6_el2",
2743 "ich_lr7_el2",
2744 "ich_lr8_el2",
2745 "ich_lr9_el2",
2746 "ich_lr10_el2",
2747 "ich_lr11_el2",
2748 "ich_lr12_el2",
2749 "ich_lr13_el2",
2750 "ich_lr14_el2",
2751 "ich_lr15_el2",
2752
2753 "icv_pmr_el1",
2754 "icv_iar0_el1",
2755 "icv_eoir0_el1",
2756 "icv_hppir0_el1",
2757 "icv_bpr0_el1",
2758 "icv_ap0r0_el1",
2759 "icv_ap0r1_el1",
2760 "icv_ap0r2_el1",
2761 "icv_ap0r3_el1",
2762 "icv_ap1r0_el1",
2763 "icv_ap1r0_el1_ns",
2764 "icv_ap1r0_el1_s",
2765 "icv_ap1r1_el1",
2766 "icv_ap1r1_el1_ns",
2767 "icv_ap1r1_el1_s",
2768 "icv_ap1r2_el1",
2769 "icv_ap1r2_el1_ns",
2770 "icv_ap1r2_el1_s",
2771 "icv_ap1r3_el1",
2772 "icv_ap1r3_el1_ns",
2773 "icv_ap1r3_el1_s",
2774 "icv_dir_el1",
2775 "icv_rpr_el1",
2776 "icv_sgi1r_el1",
2777 "icv_asgi1r_el1",
2778 "icv_sgi0r_el1",
2779 "icv_iar1_el1",
2780 "icv_eoir1_el1",
2781 "icv_hppir1_el1",
2782 "icv_bpr1_el1",
2783 "icv_bpr1_el1_ns",
2784 "icv_bpr1_el1_s",
2785 "icv_ctlr_el1",
2786 "icv_ctlr_el1_ns",
2787 "icv_ctlr_el1_s",
2788 "icv_sre_el1",
2789 "icv_sre_el1_ns",
2790 "icv_sre_el1_s",
2791 "icv_igrpen0_el1",
2792 "icv_igrpen1_el1",
2793 "icv_igrpen1_el1_ns",
2794 "icv_igrpen1_el1_s",
2795
2796 "icc_ap0r0",
2797 "icc_ap0r1",
2798 "icc_ap0r2",
2799 "icc_ap0r3",
2800 "icc_ap1r0",
2801 "icc_ap1r0_ns",
2802 "icc_ap1r0_s",
2803 "icc_ap1r1",
2804 "icc_ap1r1_ns",
2805 "icc_ap1r1_s",
2806 "icc_ap1r2",
2807 "icc_ap1r2_ns",
2808 "icc_ap1r2_s",
2809 "icc_ap1r3",
2810 "icc_ap1r3_ns",
2811 "icc_ap1r3_s",
2812 "icc_asgi1r",
2813 "icc_bpr0",
2814 "icc_bpr1",
2815 "icc_bpr1_ns",
2816 "icc_bpr1_s",
2817 "icc_ctlr",
2818 "icc_ctlr_ns",
2819 "icc_ctlr_s",
2820 "icc_dir",
2821 "icc_eoir0",
2822 "icc_eoir1",
2823 "icc_hppir0",
2824 "icc_hppir1",
2825 "icc_hsre",
2826 "icc_iar0",
2827 "icc_iar1",
2828 "icc_igrpen0",
2829 "icc_igrpen1",
2830 "icc_igrpen1_ns",
2831 "icc_igrpen1_s",
2832 "icc_mctlr",
2833 "icc_mgrpen1",
2834 "icc_msre",
2835 "icc_pmr",
2836 "icc_rpr",
2837 "icc_sgi0r",
2838 "icc_sgi1r",
2839 "icc_sre",
2840 "icc_sre_ns",
2841 "icc_sre_s",
2842
2843 "ich_ap0r0",
2844 "ich_ap0r1",
2845 "ich_ap0r2",
2846 "ich_ap0r3",
2847 "ich_ap1r0",
2848 "ich_ap1r1",
2849 "ich_ap1r2",
2850 "ich_ap1r3",
2851 "ich_hcr",
2852 "ich_vtr",
2853 "ich_misr",
2854 "ich_eisr",
2855 "ich_elrsr",
2856 "ich_vmcr",
2857 "ich_lr0",
2858 "ich_lr1",
2859 "ich_lr2",
2860 "ich_lr3",
2861 "ich_lr4",
2862 "ich_lr5",
2863 "ich_lr6",
2864 "ich_lr7",
2865 "ich_lr8",
2866 "ich_lr9",
2867 "ich_lr10",
2868 "ich_lr11",
2869 "ich_lr12",
2870 "ich_lr13",
2871 "ich_lr14",
2872 "ich_lr15",
2873 "ich_lrc0",
2874 "ich_lrc1",
2875 "ich_lrc2",
2876 "ich_lrc3",
2877 "ich_lrc4",
2878 "ich_lrc5",
2879 "ich_lrc6",
2880 "ich_lrc7",
2881 "ich_lrc8",
2882 "ich_lrc9",
2883 "ich_lrc10",
2884 "ich_lrc11",
2885 "ich_lrc12",
2886 "ich_lrc13",
2887 "ich_lrc14",
2888 "ich_lrc15",
2889
2890 "id_aa64zfr0_el1",
2891 "zcr_el3",
2892 "zcr_el2",
2893 "zcr_el12",
2894 "zcr_el1",
2895
2896 "id_aa64smfr0_el1",
2897 "svcr",
2898 "smidr_el1",
2899 "smpri_el1",
2900 "smprimap_el2",
2901 "smcr_el3",
2902 "smcr_el2",
2903 "smcr_el12",
2904 "smcr_el1",
2905 "tpidr2_el0",
2906 "mpamsm_el1",
2907
2908 "rndr",
2909 "rndrrs",
2910
2911 "hfgitr_el2",
2912 "hfgrtr_el2",
2913 "hfgwtr_el2",
2914 "hdfgrtr_el2",
2915 "hdfgwtr_el2",
2916 "hafgrtr_el2",
2917
2918 // FEAT_MPAM
2919 "mpamidr_el1",
2920 "mpam0_el1",
2921 "mpam1_el1",
2922 "mpam2_el2",
2923 "mpam3_el3",
2924 "mpam1_el12",
2925 "mpamhcr_el2",
2926 "mpamvpmv_el2",
2927 "mpamvpm0_el2",
2928 "mpamvpm1_el2",
2929 "mpamvpm2_el2",
2930 "mpamvpm3_el2",
2931 "mpamvpm4_el2",
2932 "mpamvpm5_el2",
2933 "mpamvpm6_el2",
2934 "mpamvpm7_el2",
2935
2936 "num_phys_regs",
2937
2938 // Dummy registers
2939 "nop",
2940 "raz",
2941 "unknown",
2942 "impl_defined",
2943 "erridr_el1",
2944 "errselr_el1",
2945 "erxfr_el1",
2946 "erxctlr_el1",
2947 "erxstatus_el1",
2948 "erxaddr_el1",
2949 "erxmisc0_el1",
2950 "erxmisc1_el1",
2951 "disr_el1",
2952 "vsesr_el2",
2953 "vdisr_el2",
2954
2955 // PSTATE
2956 "pan",
2957 "uao",
2958 };
2959
2960 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
2961 "The miscRegName array and NUM_MISCREGS are inconsistent.");
2962
2963 class MiscRegClassOps : public RegClassOps
2964 {
2965 public:
2966 std::string
2967 regName(const RegId &id) const override
2968 {
2969 return miscRegName[id.index()];
2970 }
2971 };
2972
2973 static inline MiscRegClassOps miscRegClassOps;
2974
2975 inline constexpr RegClass miscRegClass =
2976 RegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS,
2977 debug::MiscRegs).
2978 ops(miscRegClassOps);
2979
2980 // This mask selects bits of the CPSR that actually go in the CondCodes
2981 // integer register to allow renaming.
2982 static const uint32_t CondCodesMask = 0xF00F0000;
2983 static const uint32_t CpsrMaskQ = 0x08000000;
2984
2985 // APSR (Application Program Status Register Mask). It is the user level
2986 // alias for the CPSR. The APSR is a subset of the CPSR. Although
2987 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
2988 // APSR:
2989 // Bit[9] returns the value of CPSR.E.
2990 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
2991 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
2992
2993 // CPSR (Current Program Status Register Mask).
2994 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
2995
2996 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
2997 // integer register to allow renaming.
2998 static const uint32_t FpCondCodesMask = 0xF0000000;
2999 // This mask selects the cumulative saturation flag of the FPSCR.
3000 static const uint32_t FpscrQcMask = 0x08000000;
3001 // This mask selects the AHP bit of the FPSCR.
3002 static const uint32_t FpscrAhpMask = 0x04000000;
3003 // This mask selects the cumulative FP exception flags of the FPSCR.
3004 static const uint32_t FpscrExcMask = 0x0000009F;
3005
3020 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
3021 CPSR cpsr, ThreadContext *tc);
3022
3037 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
3038 CPSR cpsr, ThreadContext *tc);
3039
3040 // Checks for UNDEFINED behaviours when accessing AArch32
3041 // Generic Timer system registers
3042 bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc);
3043
3044 // Checks access permissions to AArch64 system registers
3045 Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr,
3046 ThreadContext *tc, const MiscRegOp64 &inst);
3047
3048 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
3049 // for MCR/MRC instructions
3050 int
3051 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
3052
3053 // Flattens a misc reg index using the specified security state. This is
3054 // used for opperations (eg address translations) where the security
3055 // state of the register access may differ from the current state of the
3056 // processor
3057 int
3058 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
3059
3060 int
3061 snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc);
3062
3063 // Takes a misc reg index and returns the root reg if its one of a set of
3064 // banked registers
3065 void
3066 preUnflattenMiscReg();
3067
3068 int
3069 unflattenMiscReg(int reg);
3070
3071} // namespace ArmISA
3072} // namespace gem5
3073
3074namespace std
3075{
3076template<>
3077struct hash<gem5::ArmISA::MiscRegNum32>
3078{
3079 size_t
3080 operator()(const gem5::ArmISA::MiscRegNum32& reg) const
3081 {
3082 return reg.packed();
3083 }
3084};
3085
3086template<>
3087struct hash<gem5::ArmISA::MiscRegNum64>
3088{
3089 size_t
3090 operator()(const gem5::ArmISA::MiscRegNum64& reg) const
3091 {
3092 return reg.packed();
3093 }
3094};
3095} // namespace std
3096
3097#endif // __ARCH_ARM_REGS_MISC_HH__
TLBI_STR_VARIANTS
#define TLBI_STR_VARIANTS(TLBI)
Definition misc.hh:64
gem5::ArmISA::MiscRegClassOps::regName
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Definition misc.hh:2967
gem5::ArmISA::MiscRegLUTEntryInitializer
Metadata table accessible via the value of the register.
Definition misc.hh:1325
gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureWrite
chain userNonSecureWrite(bool v=true) const
Definition misc.hh:1426
gem5::ArmISA::MiscRegLUTEntryInitializer::chain
const MiscRegLUTEntryInitializer & chain
Definition misc.hh:1327
gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureWrite
chain userSecureWrite(bool v=true) const
Definition misc.hh:1438
gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition misc.hh:1390
gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition misc.hh:1330
gem5::ArmISA::MiscRegLUTEntryInitializer::fault
chain fault(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1700
gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureRead
chain userSecureRead(bool v=true) const
Definition misc.hh:1432
gem5::ArmISA::MiscRegLUTEntryInitializer::implemented
chain implemented(bool v=true) const
Definition misc.hh:1367
gem5::ArmISA::MiscRegLUTEntryInitializer::MiscRegLUTEntryInitializer
MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e)
Definition misc.hh:1711
gem5::ArmISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition misc.cc:3012
gem5::ArmISA::MiscRegLUTEntryInitializer::secure
chain secure(bool v=true) const
Definition misc.hh:1643
gem5::ArmISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition misc.hh:1396
gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureWrite
chain hypNonSecureWrite(bool v=true) const
Definition misc.hh:1530
gem5::ArmISA::MiscRegLUTEntryInitializer::priv
chain priv(bool v=true) const
Definition misc.hh:1491
gem5::ArmISA::MiscRegLUTEntryInitializer::raz
chain raz(uint64_t mask=(uint64_t) -1) const
Definition misc.hh:1355
gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureRead
chain hypSecureRead(bool v=true) const
Definition misc.hh:1505
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecure
chain monSecure(bool v=true) const
Definition misc.hh:1597
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecure
chain privSecure(bool v=true) const
Definition misc.hh:1484
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureRead
chain privSecureRead(bool v=true) const
Definition misc.hh:1472
gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecure
chain privNonSecure(bool v=true) const
Definition misc.hh:1465
gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureWrite
chain hypSecureWrite(bool v=true) const
Definition misc.hh:1524
gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureRead
chain userNonSecureRead(bool v=true) const
Definition misc.hh:1420
gem5::ArmISA::MiscRegLUTEntryInitializer::nonSecure
chain nonSecure(bool v=true) const
Definition misc.hh:1630
gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureRead
chain privNonSecureRead(bool v=true) const
Definition misc.hh:1453
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition misc.hh:1575
gem5::ArmISA::MiscRegLUTEntryInitializer::reset
chain reset(uint64_t res_val) const
Definition misc.hh:1337
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead
chain monNonSecureRead(bool v=true) const
Definition misc.hh:1569
gem5::ArmISA::MiscRegLUTEntryInitializer::monWrite
chain monWrite(bool v=true) const
Definition misc.hh:1590
gem5::ArmISA::MiscRegLUTEntryInitializer::user
chain user(bool v=true) const
Definition misc.hh:1444
gem5::ArmISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition misc.hh:1378
gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecure
chain hypSecure(bool v=true) const
Definition misc.hh:1543
gem5::ArmISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition misc.hh:1402
gem5::ArmISA::MiscRegLUTEntryInitializer::privRead
chain privRead(bool v=true) const
Definition misc.hh:1498
gem5::ArmISA::MiscRegLUTEntryInitializer::hypRead
chain hypRead(bool v=true) const
Definition misc.hh:1517
gem5::ArmISA::MiscRegLUTEntryInitializer::entry
struct MiscRegLUTEntry & entry
Definition misc.hh:1326
gem5::ArmISA::MiscRegLUTEntryInitializer::banked64
chain banked64(bool v=true) const
Definition misc.hh:1408
gem5::ArmISA::MiscRegLUTEntryInitializer::fault
chain fault(MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1706
gem5::ArmISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition misc.hh:1343
gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition misc.hh:1414
gem5::ArmISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition misc.hh:1536
gem5::ArmISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition misc.hh:1611
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead
chain monSecureRead(bool v=true) const
Definition misc.hh:1557
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition misc.hh:1478
gem5::ArmISA::MiscRegLUTEntryInitializer::res1
chain res1(uint64_t mask) const
Definition misc.hh:1349
gem5::ArmISA::MiscRegLUTEntryInitializer::faultRead
chain faultRead(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1686
gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureRead
chain hypNonSecureRead(bool v=true) const
Definition misc.hh:1511
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition misc.hh:1604
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition misc.hh:1563
gem5::ArmISA::MiscRegLUTEntryInitializer::rao
chain rao(uint64_t mask=(uint64_t) -1) const
Definition misc.hh:1361
gem5::ArmISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition misc.hh:1581
gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureWrite
chain privNonSecureWrite(bool v=true) const
Definition misc.hh:1459
gem5::ArmISA::MiscRegLUTEntryInitializer::unserialize
chain unserialize(bool v=true) const
Definition misc.hh:1384
gem5::ArmISA::MiscRegLUTEntryInitializer::faultWrite
chain faultWrite(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1693
gem5::ArmISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition misc.hh:1550
gem5::MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition misc64.hh:160
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition thread_context.hh:89
std::vector
STL vector class.
Definition stl.hh:37
generic_timer_miscregs_types.hh
misc_types.hh
gem5::ArmISA::v
Bitfield< 28 > v
Definition misc_types.hh:54
gem5::ArmISA::AArch32isUndefinedGenericTimer
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:674
gem5::ArmISA::FpscrQcMask
static const uint32_t FpscrQcMask
Definition misc.hh:3000
gem5::ArmISA::miscRegClassOps
static MiscRegClassOps miscRegClassOps
Definition misc.hh:2973
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
gem5::ArmISA::aarch64SysRegReadOnly
bool aarch64SysRegReadOnly(MiscRegIndex miscReg)
gem5::ArmISA::CpsrMask
static const uint32_t CpsrMask
Definition misc.hh:2994
gem5::ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition misc.hh:3004
gem5::ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition misc.cc:2930
gem5::ArmISA::decodeCP15Reg
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition misc.cc:549
gem5::ArmISA::checkFaultAccessAArch64SysReg
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:744
gem5::ArmISA::ApsrMask
static const uint32_t ApsrMask
Definition misc.hh:2991
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition types.hh:106
gem5::ArmISA::CpsrMaskQ
static const uint32_t CpsrMaskQ
Definition misc.hh:2983
gem5::ArmISA::FpCondCodesMask
static const uint32_t FpCondCodesMask
Definition misc.hh:2998
gem5::ArmISA::e
Bitfield< 9 > e
Definition misc_types.hh:65
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition misc_types.hh:418
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition misc.cc:722
gem5::ArmISA::u
Bitfield< 22 > u
Definition misc_types.hh:439
gem5::ArmISA::FpscrAhpMask
static const uint32_t FpscrAhpMask
Definition misc.hh:3002
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition misc.hh:805
gem5::ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition misc.hh:1210
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition misc.hh:817
gem5::ArmISA::MISCREG_PMEVTYPER0
@ MISCREG_PMEVTYPER0
Definition misc.hh:385
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition misc.hh:521
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition misc.hh:188
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition misc.hh:263
gem5::ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition misc.hh:470
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition misc.hh:591
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition misc.hh:177
gem5::ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition misc.hh:1104
gem5::ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition misc.hh:249
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition misc.hh:623
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition misc.hh:533
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition misc.hh:393
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition misc.hh:155
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition misc.hh:206
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition misc.hh:120
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition misc.hh:578
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition misc.hh:635
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition misc.hh:336
gem5::ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition misc.hh:1206
gem5::ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition misc.hh:285
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition misc.hh:843
gem5::ArmISA::MISCREG_ICH_LR7
@ MISCREG_ICH_LR7
Definition misc.hh:1112
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition misc.hh:180
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition misc.hh:266
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition misc.hh:952
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition misc.hh:406
gem5::ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition misc.hh:96
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition misc.hh:102
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition misc.hh:962
gem5::ArmISA::MISCREG_ICV_BPR0_EL1
@ MISCREG_ICV_BPR0_EL1
Definition misc.hh:1005
gem5::ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition misc.hh:972
gem5::ArmISA::MISCREG_VSTCR_EL2
@ MISCREG_VSTCR_EL2
Definition misc.hh:646
gem5::ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition misc.hh:170
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition misc.hh:307
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition misc.hh:570
gem5::ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition misc.hh:1077
gem5::ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition misc.hh:288
gem5::ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition misc.hh:466
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition misc.hh:530
gem5::ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition misc.hh:469
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition misc.hh:897
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition misc.hh:337
gem5::ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition misc.hh:1209
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition misc.hh:616
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition misc.hh:801
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition misc.hh:574
gem5::ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition misc.hh:850
gem5::ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition misc.hh:317
gem5::ArmISA::MISCREG_PMEVTYPER5
@ MISCREG_PMEVTYPER5
Definition misc.hh:390
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition misc.hh:840
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition misc.hh:302
gem5::ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition misc.hh:197
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition misc.hh:343
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition misc.hh:396
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition misc.hh:93
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition misc.hh:173
gem5::ArmISA::MISCREG_MPAMVPM2_EL2
@ MISCREG_MPAMVPM2_EL2
Definition misc.hh:1181
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition misc.hh:107
gem5::ArmISA::MISCREG_ICH_LR7_EL2
@ MISCREG_ICH_LR7_EL2
Definition misc.hh:991
gem5::ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition misc.hh:846
gem5::ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition misc.hh:948
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition misc.hh:655
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition misc.hh:641
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition misc.hh:698
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition misc.hh:581
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition misc.hh:541
gem5::ArmISA::MISCREG_RNDRRS
@ MISCREG_RNDRRS
Definition misc.hh:1160
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition misc.hh:158
gem5::ArmISA::MISCREG_ICH_LR6_EL2
@ MISCREG_ICH_LR6_EL2
Definition misc.hh:990
gem5::ArmISA::MISCREG_PMEVCNTR5
@ MISCREG_PMEVCNTR5
Definition misc.hh:384
gem5::ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition misc.hh:1096
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition misc.hh:114
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition misc.hh:91
gem5::ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition misc.hh:886
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition misc.hh:569
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition misc.hh:262
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition misc.hh:548
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition misc.hh:560
gem5::ArmISA::MISCREG_ICV_RPR_EL1
@ MISCREG_ICV_RPR_EL1
Definition misc.hh:1023
gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1_S
@ MISCREG_ICV_IGRPEN1_EL1_S
Definition misc.hh:1042
gem5::ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition misc.hh:472
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition misc.hh:441
gem5::ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition misc.hh:204
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition misc.hh:344
gem5::ArmISA::MISCREG_ICV_AP1R2_EL1
@ MISCREG_ICV_AP1R2_EL1
Definition misc.hh:1016
gem5::ArmISA::MISCREG_ICV_AP0R3_EL1
@ MISCREG_ICV_AP0R3_EL1
Definition misc.hh:1009
gem5::ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition misc.hh:1081
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition misc.hh:1141
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition misc.hh:967
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition misc.hh:86
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition misc.hh:1139
gem5::ArmISA::MISCREG_MPAMVPM7_EL2
@ MISCREG_MPAMVPM7_EL2
Definition misc.hh:1186
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition misc.hh:215
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition misc.hh:443
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition misc.hh:209
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition misc.hh:676
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition misc.hh:479
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition misc.hh:97
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition misc.hh:493
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition misc.hh:810
gem5::ArmISA::MISCREG_ICV_AP1R1_EL1_NS
@ MISCREG_ICV_AP1R1_EL1_NS
Definition misc.hh:1014
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition misc.hh:506
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition misc.hh:583
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition misc.hh:356
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition misc.hh:489
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition misc.hh:313
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition misc.hh:963
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition misc.hh:420
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition misc.hh:807
gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS
@ MISCREG_ICC_IGRPEN1_NS
Definition misc.hh:1078
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition misc.hh:922
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition misc.hh:829
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition misc.hh:457
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition misc.hh:826
gem5::ArmISA::MISCREG_ICV_CTLR_EL1
@ MISCREG_ICV_CTLR_EL1
Definition misc.hh:1033
gem5::ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition misc.hh:296
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition misc.hh:182
gem5::ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition misc.hh:198
gem5::ArmISA::MISCREG_ICC_CTLR_NS
@ MISCREG_ICC_CTLR_NS
Definition misc.hh:1066
gem5::ArmISA::MISCREG_PMEVTYPER1
@ MISCREG_PMEVTYPER1
Definition misc.hh:386
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition misc.hh:856
gem5::ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition misc.hh:1057
gem5::ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition misc.hh:1080
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition misc.hh:269
gem5::ArmISA::MISCREG_ICV_AP1R2_EL1_S
@ MISCREG_ICV_AP1R2_EL1_S
Definition misc.hh:1018
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition misc.hh:663
gem5::ArmISA::MISCREG_ICH_LR8
@ MISCREG_ICH_LR8
Definition misc.hh:1113
gem5::ArmISA::MISCREG_ICV_AP0R0_EL1
@ MISCREG_ICV_AP0R0_EL1
Definition misc.hh:1006
gem5::ArmISA::MISCREG_MPAMVPM4_EL2
@ MISCREG_MPAMVPM4_EL2
Definition misc.hh:1183
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition misc.hh:931
gem5::ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition misc.hh:926
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition misc.hh:118
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition misc.hh:304
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition misc.hh:428
gem5::ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition misc.hh:163
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition misc.hh:234
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition misc.hh:709
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition misc.hh:881
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition misc.hh:101
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition misc.hh:999
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition misc.hh:89
gem5::ArmISA::MISCREG_MPAM3_EL3
@ MISCREG_MPAM3_EL3
Definition misc.hh:1175
gem5::ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition misc.hh:201
gem5::ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition misc.hh:1101
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition misc.hh:542
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition misc.hh:575
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition misc.hh:126
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition misc.hh:811
gem5::ArmISA::MISCREG_ICV_IGRPEN1_EL1_NS
@ MISCREG_ICV_IGRPEN1_EL1_NS
Definition misc.hh:1041
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition misc.hh:495
gem5::ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition misc.hh:1121
gem5::ArmISA::MISCREG_SMIDR_EL1
@ MISCREG_SMIDR_EL1
Definition misc.hh:1148
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition misc.hh:253
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition misc.hh:693
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition misc.hh:278
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition misc.hh:523
gem5::ArmISA::MISCREG_ICH_LR5
@ MISCREG_ICH_LR5
Definition misc.hh:1110
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition misc.hh:711
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition misc.hh:363
gem5::ArmISA::MISCREG_ICV_EOIR1_EL1
@ MISCREG_ICV_EOIR1_EL1
Definition misc.hh:1028
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition misc.hh:329
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition misc.hh:814
gem5::ArmISA::MISCREG_ICV_IGRPEN0_EL1
@ MISCREG_ICV_IGRPEN0_EL1
Definition misc.hh:1039
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition misc.hh:456
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition misc.hh:913
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition misc.hh:557
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition misc.hh:248
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition misc.hh:259
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition misc.hh:419
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition misc.hh:364
gem5::ArmISA::MISCREG_ICC_BPR1_S
@ MISCREG_ICC_BPR1_S
Definition misc.hh:1064
gem5::ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition misc.hh:132
gem5::ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition misc.hh:294
gem5::ArmISA::MISCREG_ICH_LRC11
@ MISCREG_ICH_LRC11
Definition misc.hh:1132
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition misc.hh:628
gem5::ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition misc.hh:274
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition misc.hh:359
gem5::ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition misc.hh:887
gem5::ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition misc.hh:853
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition misc.hh:910
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition misc.hh:358
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition misc.hh:341
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition misc.hh:593
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition misc.hh:244
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition misc.hh:211
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition misc.hh:833
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition misc.hh:127
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition misc.hh:525
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition misc.hh:205
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition misc.hh:883
gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS
@ MISCREG_ICC_SRE_EL1_NS
Definition misc.hh:958
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition misc.hh:150
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition misc.hh:83
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition misc.hh:571
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition misc.hh:121
gem5::ArmISA::MISCREG_SCTLR2_EL12
@ MISCREG_SCTLR2_EL12
Definition misc.hh:612
gem5::ArmISA::MISCREG_SCTLR2_EL1
@ MISCREG_SCTLR2_EL1
Definition misc.hh:611
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition misc.hh:648
gem5::ArmISA::MISCREG_SCTLR2_EL3
@ MISCREG_SCTLR2_EL3
Definition misc.hh:626
gem5::ArmISA::MISCREG_SMCR_EL1
@ MISCREG_SMCR_EL1
Definition misc.hh:1154
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition misc.hh:660
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition misc.hh:113
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition misc.hh:497
gem5::ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition misc.hh:978
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition misc.hh:615
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition misc.hh:268
gem5::ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition misc.hh:297
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition misc.hh:677
gem5::ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition misc.hh:1214
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition misc.hh:292
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICC_AP1R3_EL1_NS
Definition misc.hh:941
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition misc.hh:804
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition misc.hh:452
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition misc.hh:552
gem5::ArmISA::MISCREG_ICV_AP1R3_EL1_S
@ MISCREG_ICV_AP1R3_EL1_S
Definition misc.hh:1021
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition misc.hh:349
gem5::ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition misc.hh:668
gem5::ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition misc.hh:169
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition misc.hh:713
gem5::ArmISA::MISCREG_PMEVTYPER2
@ MISCREG_PMEVTYPER2
Definition misc.hh:387
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition misc.hh:193
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition misc.hh:636
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition misc.hh:394
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition misc.hh:279
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition misc.hh:378
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition misc.hh:517
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition misc.hh:835
gem5::ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition misc.hh:135
gem5::ArmISA::MISCREG_HFGRTR_EL2
@ MISCREG_HFGRTR_EL2
Definition misc.hh:1164
gem5::ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition misc.hh:1047
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition misc.hh:252
gem5::ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition misc.hh:434
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition misc.hh:601
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition misc.hh:194
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition misc.hh:445
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition misc.hh:678
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition misc.hh:368
gem5::ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition misc.hh:891
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition misc.hh:933
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition misc.hh:544
gem5::ArmISA::MISCREG_ICC_IGRPEN1_S
@ MISCREG_ICC_IGRPEN1_S
Definition misc.hh:1079
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition misc.hh:673
gem5::ArmISA::MISCREG_ICC_AP1R0_S
@ MISCREG_ICC_AP1R0_S
Definition misc.hh:1050
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition misc.hh:87
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition misc.hh:225
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition misc.hh:549
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition misc.hh:207
gem5::ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition misc.hh:192
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition misc.hh:547
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition misc.hh:531
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition misc.hh:82
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition misc.hh:243
gem5::ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition misc.hh:318
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition misc.hh:498
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition misc.hh:584
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition misc.hh:884
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition misc.hh:324
gem5::ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition misc.hh:982
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition misc.hh:705
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition misc.hh:607
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition misc.hh:174
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition misc.hh:558
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition misc.hh:838
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition misc.hh:540
gem5::ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition misc.hh:1211
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition misc.hh:412
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition misc.hh:518
gem5::ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition misc.hh:1098
gem5::ArmISA::MISCREG_MPAM1_EL1
@ MISCREG_MPAM1_EL1
Definition misc.hh:1173
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition misc.hh:85
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition misc.hh:520
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition misc.hh:681
gem5::ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition misc.hh:849
gem5::ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition misc.hh:333
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition misc.hh:504
gem5::ArmISA::MISCREG_SCTLR2_EL2
@ MISCREG_SCTLR2_EL2
Definition misc.hh:617
gem5::ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition misc.hh:171
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition misc.hh:352
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition misc.hh:878
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition misc.hh:430
gem5::ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition misc.hh:977
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition misc.hh:510
gem5::ArmISA::MISCREG_HFGITR_EL2
@ MISCREG_HFGITR_EL2
Definition misc.hh:1163
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition misc.hh:242
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition misc.hh:507
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
Definition misc.hh:936
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition misc.hh:609
gem5::ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition misc.hh:848
gem5::ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition misc.hh:1094
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition misc.hh:524
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition misc.hh:439
gem5::ArmISA::MISCREG_PMEVCNTR3
@ MISCREG_PMEVCNTR3
Definition misc.hh:382
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition misc.hh:603
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition misc.hh:707
gem5::ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition misc.hh:214
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition misc.hh:399
gem5::ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition misc.hh:1076
gem5::ArmISA::MISCREG_ICH_LRC7
@ MISCREG_ICH_LRC7
Definition misc.hh:1128
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition misc.hh:216
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition misc.hh:706
gem5::ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition misc.hh:196
gem5::ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition misc.hh:416
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition misc.hh:527
gem5::ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition misc.hh:133
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition misc.hh:880
gem5::ArmISA::MISCREG_ICH_LRC8
@ MISCREG_ICH_LRC8
Definition misc.hh:1129
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition misc.hh:622
gem5::ArmISA::MISCREG_ICH_LR9_EL2
@ MISCREG_ICH_LR9_EL2
Definition misc.hh:993
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition misc.hh:512
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition misc.hh:245
gem5::ArmISA::MISCREG_ICV_SRE_EL1_NS
@ MISCREG_ICV_SRE_EL1_NS
Definition misc.hh:1037
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition misc.hh:687
gem5::ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition misc.hh:1212
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition misc.hh:831
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition misc.hh:808
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition misc.hh:917
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition misc.hh:172
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition misc.hh:708
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition misc.hh:369
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition misc.hh:865
gem5::ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition misc.hh:1068
gem5::ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition misc.hh:453
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition misc.hh:455
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition misc.hh:685
gem5::ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition misc.hh:293
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition misc.hh:919
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition misc.hh:301
gem5::ArmISA::MISCREG_ICV_CTLR_EL1_NS
@ MISCREG_ICV_CTLR_EL1_NS
Definition misc.hh:1034
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition misc.hh:594
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition misc.hh:701
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition misc.hh:220
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition misc.hh:828
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition misc.hh:598
gem5::ArmISA::MISCREG_PMEVCNTR2
@ MISCREG_PMEVCNTR2
Definition misc.hh:381
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition misc.hh:355
gem5::ArmISA::MISCREG_SMCR_EL3
@ MISCREG_SMCR_EL3
Definition misc.hh:1151
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition misc.hh:653
gem5::ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition misc.hh:892
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition misc.hh:124
gem5::ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition misc.hh:1073
gem5::ArmISA::MISCREG_ICH_LR1
@ MISCREG_ICH_LR1
Definition misc.hh:1106
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition misc.hh:874
gem5::ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition misc.hh:565
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition misc.hh:684
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition misc.hh:604
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition misc.hh:821
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition misc.hh:816
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition misc.hh:345
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition misc.hh:480
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition misc.hh:600
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition misc.hh:561
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition misc.hh:105
gem5::ArmISA::MISCREG_ICH_LR4_EL2
@ MISCREG_ICH_LR4_EL2
Definition misc.hh:988
gem5::ArmISA::MISCREG_UNKNOWN
@ MISCREG_UNKNOWN
Definition misc.hh:1198
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition misc.hh:372
gem5::ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition misc.hh:1103
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition misc.hh:367
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition misc.hh:633
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition misc.hh:462
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition misc.hh:328
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition misc.hh:88
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition misc.hh:546
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition misc.hh:839
gem5::ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition misc.hh:138
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition misc.hh:496
gem5::ArmISA::MISCREG_ICH_LR11_EL2
@ MISCREG_ICH_LR11_EL2
Definition misc.hh:995
gem5::ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition misc.hh:900
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition misc.hh:934
gem5::ArmISA::MISCREG_ICV_AP1R1_EL1_S
@ MISCREG_ICV_AP1R1_EL1_S
Definition misc.hh:1015
gem5::ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition misc.hh:893
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition misc.hh:825
gem5::ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition misc.hh:213
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition misc.hh:654
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition misc.hh:371
gem5::ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition misc.hh:1207
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition misc.hh:303
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition misc.hh:488
gem5::ArmISA::MISCREG_ICC_AP1R2_NS
@ MISCREG_ICC_AP1R2_NS
Definition misc.hh:1055
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition misc.hh:508
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition misc.hh:79
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition misc.hh:659
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition misc.hh:260
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition misc.hh:176
gem5::ArmISA::MISCREG_ICH_LR14_EL2
@ MISCREG_ICH_LR14_EL2
Definition misc.hh:998
gem5::ArmISA::MISCREG_ICV_SRE_EL1_S
@ MISCREG_ICV_SRE_EL1_S
Definition misc.hh:1038
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition misc.hh:425
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition misc.hh:614
gem5::ArmISA::MISCREG_PMEVTYPER3
@ MISCREG_PMEVTYPER3
Definition misc.hh:388
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition misc.hh:271
gem5::ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition misc.hh:944
gem5::ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition misc.hh:202
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition misc.hh:290
gem5::ArmISA::MISCREG_SMPRI_EL1
@ MISCREG_SMPRI_EL1
Definition misc.hh:1149
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition misc.hh:233
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition misc.hh:885
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition misc.hh:449
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition misc.hh:238
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition misc.hh:490
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_ICC_AP1R3_EL1_S
Definition misc.hh:942
gem5::ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition misc.hh:473
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition misc.hh:852
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition misc.hh:417
gem5::ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition misc.hh:167
gem5::ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition misc.hh:930
gem5::ArmISA::MISCREG_MPAMHCR_EL2
@ MISCREG_MPAMHCR_EL2
Definition misc.hh:1177
gem5::ArmISA::MISCREG_ICC_BPR1_NS
@ MISCREG_ICC_BPR1_NS
Definition misc.hh:1063
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition misc.hh:444
gem5::ArmISA::MISCREG_ICH_LR10_EL2
@ MISCREG_ICH_LR10_EL2
Definition misc.hh:994
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition misc.hh:672
gem5::ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition misc.hh:1045
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition misc.hh:806
gem5::ArmISA::MISCREG_ICH_LR10
@ MISCREG_ICH_LR10
Definition misc.hh:1115
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition misc.hh:854
gem5::ArmISA::MISCREG_ID_AA64MMFR3_EL1
@ MISCREG_ID_AA64MMFR3_EL1
Definition misc.hh:907
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition misc.hh:405
gem5::ArmISA::MISCREG_MPAMVPMV_EL2
@ MISCREG_MPAMVPMV_EL2
Definition misc.hh:1178
gem5::ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition misc.hh:957
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition misc.hh:500
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition misc.hh:800
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition misc.hh:610
gem5::ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition misc.hh:134
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