gem5  v22.0.0.2
system.cc
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41 
42 #include "sim/system.hh"
43 
44 #include <algorithm>
45 
46 #include "base/compiler.hh"
47 #include "base/cprintf.hh"
49 #include "base/loader/symtab.hh"
50 #include "base/str.hh"
51 #include "base/trace.hh"
52 #include "config/the_isa.hh"
53 #if !IS_NULL_ISA
54 #include "cpu/base.hh"
55 #endif
56 #include "cpu/thread_context.hh"
57 #include "debug/Loader.hh"
58 #include "debug/Quiesce.hh"
59 #include "debug/WorkItems.hh"
60 #include "mem/abstract_mem.hh"
61 #include "mem/physical.hh"
62 #include "params/System.hh"
63 #include "sim/byteswap.hh"
64 #include "sim/debug.hh"
65 #include "sim/redirect_path.hh"
67 
68 namespace gem5
69 {
70 
72 
73 void
75 {
76 # if !IS_NULL_ISA
77  DPRINTFS(Quiesce, context->getCpuPtr(), "activating\n");
78  context->activate();
79 # endif
80 }
81 
82 std::string
84 {
85  assert(context);
86  return csprintf("%s.threads[%d]", context->getSystemPtr()->name(),
87  context->contextId());
88 }
89 
90 void
92 {
93  context->suspend();
94  context->getSystemPtr()->workload->recordQuiesce();
95 }
96 
97 void
99 {
100  ContextID id = size();
101  tc->setContextId(id);
102 
103  auto &t = threads.emplace_back();
104  t.context = tc;
105  // Look up this thread again on resume, in case the threads vector has
106  // been reallocated.
107  t.resumeEvent = new EventFunctionWrapper(
108  [this, id](){ thread(id).resume(); },
109  tc->getSystemPtr()->name());
110 }
111 
112 void
114 {
115  auto &t = thread(id);
116  panic_if(!t.context, "Can't replace a context which doesn't exist.");
117 # if !IS_NULL_ISA
118  if (t.resumeEvent->scheduled()) {
119  Tick when = t.resumeEvent->when();
120  t.context->getCpuPtr()->deschedule(t.resumeEvent);
121  tc->getCpuPtr()->schedule(t.resumeEvent, when);
122  }
123 # endif
124  t.context = tc;
125 }
126 
129 {
130  for (auto &thread: threads) {
132  return thread.context;
133  }
134  return nullptr;
135 }
136 
137 int
139 {
140  int count = 0;
141  for (auto &thread: threads) {
142  auto status = thread.context->status();
143  if (status != ThreadContext::Halted &&
145  count++;
146  }
147  }
148  return count;
149 }
150 
151 void
153 {
154  auto &t = thread(id);
155 # if !IS_NULL_ISA
156  [[maybe_unused]] BaseCPU *cpu = t.context->getCpuPtr();
157  DPRINTFS(Quiesce, cpu, "quiesce()\n");
158 # endif
159  t.quiesce();
160 }
161 
162 void
164 {
165 # if !IS_NULL_ISA
166  auto &t = thread(id);
167  BaseCPU *cpu = t.context->getCpuPtr();
168 
169  DPRINTFS(Quiesce, cpu, "quiesceTick until %u\n", when);
170  t.quiesce();
171 
172  cpu->reschedule(t.resumeEvent, when, true);
173 # endif
174 }
175 
177 
179  : SimObject(p), _systemPort("system_port", this),
180  multiThread(p.multi_thread),
182  physProxy(_systemPort, p.cache_line_size),
184  physmem(name() + ".physmem", p.memories, p.mmap_using_noreserve,
185  p.shared_backstore, p.auto_unlink_shared_backstore),
186  ShadowRomRanges(p.shadow_rom_ranges.begin(),
187  p.shadow_rom_ranges.end()),
188  memoryMode(p.mem_mode),
189  _cacheLineSize(p.cache_line_size),
190  numWorkIds(p.num_work_ids),
191  thermalModel(p.thermal_model),
192  _m5opRange(p.m5ops_base ?
193  RangeSize(p.m5ops_base, 0x10000) :
194  AddrRange(1, 0)), // Create an empty range if disabled
195  redirectPaths(p.redirect_paths)
196 {
197  panic_if(!workload, "No workload set for system %s "
198  "(could use StubWorkload?).", name());
199  workload->setSystem(this);
200 
201  // add self to global system list
202  systemList.push_back(this);
203 
204  // check if the cache line size is a value known to work
205  if (_cacheLineSize != 16 && _cacheLineSize != 32 &&
206  _cacheLineSize != 64 && _cacheLineSize != 128) {
207  warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
208  }
209 
210  // Get the generic system requestor IDs
211  [[maybe_unused]] RequestorID tmp_id;
212  tmp_id = getRequestorId(this, "writebacks");
213  assert(tmp_id == Request::wbRequestorId);
214  tmp_id = getRequestorId(this, "functional");
215  assert(tmp_id == Request::funcRequestorId);
216  tmp_id = getRequestorId(this, "interrupt");
217  assert(tmp_id == Request::intRequestorId);
218 
219  // increment the number of running systems
221 
222  // Set back pointers to the system in all memories
223  for (int x = 0; x < params().memories.size(); x++)
224  params().memories[x]->system(this);
225 }
226 
228 {
229  for (uint32_t j = 0; j < numWorkIds; j++)
230  delete workItemStats[j];
231 }
232 
233 Port &
234 System::getPort(const std::string &if_name, PortID idx)
235 {
236  // no need to distinguish at the moment (besides checking)
237  return _systemPort;
238 }
239 
240 void
241 System::setMemoryMode(enums::MemoryMode mode)
242 {
243  assert(drainState() == DrainState::Drained);
244  memoryMode = mode;
245 }
246 
247 void
249 {
250  threads.insert(tc);
251 
253 
254  for (auto *e: liveEvents)
255  tc->schedule(e);
256 }
257 
258 bool
260 {
261  bool all = true;
262  liveEvents.push_back(event);
263  for (auto *tc: threads)
264  all = tc->schedule(event) && all;
265  return all;
266 }
267 
268 bool
270 {
271  bool all = true;
272  liveEvents.remove(event);
273  for (auto *tc: threads)
274  all = tc->remove(event) && all;
275  return all;
276 }
277 
278 void
280 {
281  auto *otc = threads[context_id];
282  threads.replace(tc, context_id);
283 
285 
286  for (auto *e: liveEvents) {
287  otc->remove(e);
288  tc->schedule(e);
289  }
290 }
291 
292 Addr
294 {
295  return physmem.totalSize();
296 }
297 
298 bool
300 {
301  return physmem.isMemAddr(addr);
302 }
303 
304 void
306  memory::AbstractMemory *deviceMemory)
307 {
308  deviceMemMap[requestor_id].push_back(deviceMemory);
309 }
310 
311 bool
313 {
314  if (!deviceMemMap.count(pkt->requestorId())) {
315  return false;
316  }
317 
318  return (getDeviceMemory(pkt) != nullptr);
319 }
320 
323 {
324  const RequestorID& rid = pkt->requestorId();
325 
326  panic_if(!deviceMemMap.count(rid),
327  "No device memory found for Requestor %d\n", rid);
328 
329  for (auto& mem : deviceMemMap.at(rid)) {
330  if (pkt->getAddrRange().isSubset(mem->getAddrRange())) {
331  return mem;
332  }
333  }
334 
335  return nullptr;
336 }
337 
338 void
340 {
341  for (auto &t: threads.threads) {
342  Tick when = 0;
343  if (t.resumeEvent && t.resumeEvent->scheduled())
344  when = t.resumeEvent->when();
345  ContextID id = t.context->contextId();
346  paramOut(cp, csprintf("quiesceEndTick_%d", id), when);
347  }
348 
349  // also serialize the memories in the system
350  physmem.serializeSection(cp, "physmem");
351 }
352 
353 
354 void
356 {
357  for (auto &t: threads.threads) {
358  Tick when = 0;
359  ContextID id = t.context->contextId();
360  if (!optParamIn(cp, csprintf("quiesceEndTick_%d", id), when) ||
361  !when || !t.resumeEvent) {
362  continue;
363  }
364 # if !IS_NULL_ISA
365  t.context->getCpuPtr()->schedule(t.resumeEvent, when);
366 # endif
367  }
368 
369  // also unserialize the memories in the system
370  physmem.unserializeSection(cp, "physmem");
371 }
372 
373 void
375 {
377 
378  for (uint32_t j = 0; j < numWorkIds ; j++) {
380  std::stringstream namestr;
381  ccprintf(namestr, "work_item_type%d", j);
382  workItemStats[j]->init(20)
383  .name(namestr.str())
384  .desc("Run time stat for" + namestr.str())
385  .prereq(*workItemStats[j]);
386  }
387 }
388 
389 void
390 System::workItemEnd(uint32_t tid, uint32_t workid)
391 {
392  std::pair<uint32_t,uint32_t> p(tid, workid);
393  if (!lastWorkItemStarted.count(p))
394  return;
395 
396  Tick samp = curTick() - lastWorkItemStarted[p];
397  DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
398 
399  if (workid >= numWorkIds)
400  fatal("Got workid greater than specified in system configuration\n");
401 
402  workItemStats[workid]->sample(samp);
403  lastWorkItemStarted.erase(p);
404 }
405 
406 bool
407 System::trapToGdb(int signal, ContextID ctx_id) const
408 {
409  return workload->trapToGdb(signal, ctx_id);
410 }
411 
412 void
414 {
415  std::ios::fmtflags flags(std::cerr.flags());
416 
419  for (; i != end; ++i) {
420  System *sys = *i;
421  std::cerr << "System " << sys->name() << ": " << std::hex << sys
422  << std::endl;
423  }
424 
425  std::cerr.flags(flags);
426 }
427 
428 void
430 {
432 }
433 
434 std::string
435 System::stripSystemName(const std::string& requestor_name) const
436 {
437  if (startswith(requestor_name, name())) {
438  return requestor_name.substr(name().size() + 1);
439  } else {
440  return requestor_name;
441  }
442 }
443 
446 {
448 
449  // number of occurrences of the SimObject pointer
450  // in the requestor list.
451  auto obj_number = 0;
452 
453  for (int i = 0; i < requestors.size(); i++) {
454  if (requestors[i].obj == obj) {
455  id = i;
456  obj_number++;
457  }
458  }
459 
460  fatal_if(obj_number > 1,
461  "Cannot lookup RequestorID by SimObject pointer: "
462  "More than one requestor is sharing the same SimObject\n");
463 
464  return id;
465 }
466 
468 System::lookupRequestorId(const std::string& requestor_name) const
469 {
470  std::string name = stripSystemName(requestor_name);
471 
472  for (int i = 0; i < requestors.size(); i++) {
473  if (requestors[i].req_name == name) {
474  return i;
475  }
476  }
477 
479 }
480 
482 System::getGlobalRequestorId(const std::string& requestor_name)
483 {
484  return _getRequestorId(nullptr, requestor_name);
485 }
486 
488 System::getRequestorId(const SimObject* requestor, std::string subrequestor)
489 {
490  auto requestor_name = leafRequestorName(requestor, subrequestor);
491  return _getRequestorId(requestor, requestor_name);
492 }
493 
496  const std::string& requestor_name)
497 {
498  std::string name = stripSystemName(requestor_name);
499 
500  // CPUs in switch_cpus ask for ids again after switching
501  for (int i = 0; i < requestors.size(); i++) {
502  if (requestors[i].req_name == name) {
503  return i;
504  }
505  }
506 
507  // Verify that the statistics haven't been enabled yet
508  // Otherwise objects will have sized their stat buckets and
509  // they will be too small
510 
511  if (statistics::enabled()) {
512  fatal("Can't request a requestorId after regStats(). "
513  "You must do so in init().\n");
514  }
515 
516  // Generate a new RequestorID incrementally
517  RequestorID requestor_id = requestors.size();
518 
519  // Append the new Requestor metadata to the group of system Requestors.
520  requestors.emplace_back(requestor, name, requestor_id);
521 
522  return requestors.back().id;
523 }
524 
525 std::string
527  const std::string& subrequestor)
528 {
529  if (subrequestor.empty()) {
530  return requestor->name();
531  } else {
532  // Get the full requestor name by appending the subrequestor name to
533  // the root SimObject requestor name
534  return requestor->name() + "." + subrequestor;
535  }
536 }
537 
538 std::string
540 {
541  if (requestor_id >= requestors.size())
542  fatal("Invalid requestor_id passed to getRequestorName()\n");
543 
544  const auto& requestor_info = requestors[requestor_id];
545  return requestor_info.req_name;
546 }
547 
548 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::System::addDeviceMemory
void addDeviceMemory(RequestorID requestorId, memory::AbstractMemory *deviceMemory)
Add a physical memory range for a device.
Definition: system.cc:305
gem5::System::lastWorkItemStarted
std::map< std::pair< uint32_t, uint32_t >, Tick > lastWorkItemStarted
Definition: system.hh:588
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::System::Threads::size
int size() const
Definition: system.hh:214
gem5::System::workItemEnd
void workItemEnd(uint32_t tid, uint32_t workid)
Definition: system.cc:390
system.hh
gem5::System::lookupRequestorId
RequestorID lookupRequestorId(const SimObject *obj) const
Looks up the RequestorID for a given SimObject returns an invalid RequestorID (invldRequestorId) if n...
Definition: system.cc:445
gem5::System::numWorkIds
uint32_t numWorkIds
Definition: system.hh:416
gem5::System::Threads::Thread::resume
void resume()
Definition: system.cc:74
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::System::liveEvents
std::list< PCEvent * > liveEvents
Definition: system.hh:108
gem5::System::Threads::Thread::context
ThreadContext * context
Definition: system.hh:122
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:815
abstract_mem.hh
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:327
gem5::System::schedule
bool schedule(PCEvent *event) override
Definition: system.cc:259
gem5::System::Threads::quiesce
void quiesce(ContextID id)
Definition: system.cc:152
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::System::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Additional function to return the Port of a memory object.
Definition: system.cc:234
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Serializable::serializeSection
void serializeSection(CheckpointOut &cp, const char *name) const
Serialize an object into a new section.
Definition: serialize.cc:74
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
redirect_path.hh
gem5::System::workItemStats
std::map< uint32_t, statistics::Histogram * > workItemStats
Definition: system.hh:589
gem5::startswith
bool startswith(const char *s, const char *prefix)
Return true if 's' starts with the prefix string 'prefix'.
Definition: str.hh:229
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::System::Threads::replace
void replace(ThreadContext *tc, ContextID id)
Definition: system.cc:113
gem5::System::Threads::end
const_iterator end() const
Definition: system.hh:232
gem5::System::setMemoryMode
void setMemoryMode(enums::MemoryMode mode)
Change the memory mode of the system.
Definition: system.cc:241
gem5::ThreadContext::activate
virtual void activate()=0
Set the status to Active.
gem5::System::numSystemsRunning
static int numSystemsRunning
Definition: system.hh:598
std::vector
STL vector class.
Definition: stl.hh:37
gem5::System::registerThreadContext
void registerThreadContext(ThreadContext *tc)
Definition: system.cc:248
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::System::System
System(const Params &p)
Definition: system.cc:178
gem5::System::regStats
void regStats() override
Callback to set stat parameters.
Definition: system.cc:374
gem5::System::getDeviceMemory
memory::AbstractMemory * getDeviceMemory(const PacketPtr &pkt) const
Return a pointer to the device memory.
Definition: system.cc:322
gem5::AddrRange::isSubset
bool isSubset(const AddrRange &r) const
Determine if this range is a subset of another range, i.e.
Definition: addr_range.hh:445
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ThreadContext::status
virtual Status status() const =0
gem5::System::_getRequestorId
RequestorID _getRequestorId(const SimObject *requestor, const std::string &requestor_name)
helper function for getRequestorId
Definition: system.cc:495
gem5::System::stripSystemName
std::string stripSystemName(const std::string &requestor_name) const
Strips off the system name from a requestor name.
Definition: system.cc:435
gem5::System::Threads::quiesceTick
void quiesceTick(ContextID id, Tick when)
Definition: system.cc:163
gem5::Request::intRequestorId
@ intRequestorId
This requestor id is used for message signaled interrupts.
Definition: request.hh:281
gem5::System::requestors
std::vector< RequestorInfo > requestors
This array is a per-system list of all devices capable of issuing a memory system request and an asso...
Definition: system.hh:423
str.hh
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::System::redirectPaths
std::vector< RedirectPath * > redirectPaths
Definition: system.hh:616
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::System::Threads::threads
std::vector< Thread > threads
Definition: system.hh:131
gem5::System::_systemPort
SystemPort _systemPort
Definition: system.hh:109
gem5::System::deviceMemMap
std::unordered_map< RequestorID, std::vector< memory::AbstractMemory * > > deviceMemMap
Definition: system.hh:113
gem5::System
Definition: system.hh:75
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
gem5::System::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: system.cc:299
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Packet::requestorId
RequestorID requestorId() const
Definition: packet.hh:776
gem5::Serializable::unserializeSection
void unserializeSection(CheckpointIn &cp, const char *name)
Unserialize an a child object.
Definition: serialize.cc:81
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::System::physmem
memory::PhysicalMemory physmem
Definition: system.hh:406
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::System::systemList
static std::vector< System * > systemList
Definition: system.hh:597
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Request::wbRequestorId
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
Definition: request.hh:274
debug.hh
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::VegaISA::x
Bitfield< 4 > x
Definition: pagetable.hh:61
gem5::PCEvent
Definition: pc_event.hh:45
gem5::System::getRequestorName
std::string getRequestorName(RequestorID requestor_id)
Get the name of an object for a given request id.
Definition: system.cc:539
gem5::System::getGlobalRequestorId
RequestorID getGlobalRequestorId(const std::string &requestor_name)
Registers a GLOBAL RequestorID, which is a RequestorID not related to any particular SimObject; since...
Definition: system.cc:482
gem5::System::getRequestorId
RequestorID getRequestorId(const SimObject *requestor, std::string subrequestor={})
Request an id used to create a request object in the system.
Definition: system.cc:488
cprintf.hh
compiler.hh
flags
uint8_t flags
Definition: helpers.cc:66
gem5::System::memSize
Addr memSize() const
Amount of physical memory that exists.
Definition: system.cc:293
gem5::System::memoryMode
enums::MemoryMode memoryMode
Definition: system.hh:410
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::Threads::Thread::quiesce
void quiesce() const
Definition: system.cc:91
std::pair
STL pair class.
Definition: stl.hh:58
gem5::System::Threads::begin
const_iterator begin() const
Definition: system.hh:231
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::System::remove
bool remove(PCEvent *event) override
Definition: system.cc:269
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
DPRINTFS
#define DPRINTFS(x, s,...)
Definition: trace.hh:193
gem5::Workload::trapToGdb
bool trapToGdb(int signal, ContextID ctx_id)
Definition: workload.cc:80
gem5::System::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: system.cc:355
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:279
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:286
gem5::System::leafRequestorName
std::string leafRequestorName(const SimObject *requestor, const std::string &subrequestor)
Helper function for constructing the full (sub)requestor name by providing the root requestor and the...
Definition: system.cc:526
gem5::System::trapToGdb
bool trapToGdb(int signal, ContextID ctx_id) const
Definition: system.cc:407
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::System::multiThread
const bool multiThread
Definition: system.hh:316
gem5::System::isDeviceMemAddr
bool isDeviceMemAddr(const PacketPtr &pkt) const
Similar to isMemAddr but for devices.
Definition: system.cc:312
gem5::System::Threads::insert
void insert(ThreadContext *tc)
Definition: system.cc:98
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::optParamIn
bool optParamIn(CheckpointIn &cp, const std::string &name, T &param, bool do_warn=true)
This function is used for restoring optional parameters from the checkpoint.
Definition: serialize.hh:357
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
serialize_handlers.hh
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::System::ShadowRomRanges
AddrRangeList ShadowRomRanges
Definition: system.hh:408
gem5::System::init_param
uint64_t init_param
Definition: system.hh:323
gem5::Workload::replaceThreadContext
virtual void replaceThreadContext(ThreadContext *tc)
Definition: workload.cc:54
gem5::Request::invldRequestorId
@ invldRequestorId
Invalid requestor id for assertion checking only.
Definition: request.hh:286
gem5::System::Threads::thread
Thread & thread(ContextID id)
Definition: system.hh:134
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:117
physical.hh
gem5::System::Threads::Thread::name
std::string name() const
Definition: system.cc:83
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::System::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: system.cc:339
gem5::System::_m5opRange
const AddrRange _m5opRange
Range for memory-mapped m5 pseudo ops.
Definition: system.hh:565
gem5::System::printSystems
static void printSystems()
Definition: system.cc:413
gem5::memory::PhysicalMemory::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: physical.cc:273
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Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
mem
bool_vector8 mem[]
Definition: reset_stim.h:43
gem5::System::replaceThreadContext
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Definition: system.cc:279
gem5::printSystems
void printSystems()
Definition: system.cc:429
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::memory::PhysicalMemory::totalSize
uint64_t totalSize() const
Get the total physical memory size.
Definition: physical.hh:231
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
trace.hh
symtab.hh
gem5::PCEventScope::schedule
virtual bool schedule(PCEvent *event)=0
gem5::Workload::setSystem
virtual void setSystem(System *sys)
Definition: workload.hh:87
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5::System::~System
~System()
Definition: system.cc:227
gem5::Workload::registerThreadContext
virtual void registerThreadContext(ThreadContext *tc)
Definition: workload.cc:39
gem5::System::Threads::findFree
ThreadContext * findFree()
Definition: system.cc:128
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Packet::getAddrRange
AddrRange getAddrRange() const
Get address range to which this packet belongs.
Definition: packet.cc:239
object_file.hh
gem5::System::Threads::numRunning
int numRunning() const
Definition: system.cc:138
thread_context.hh
gem5::System::_cacheLineSize
const unsigned int _cacheLineSize
Definition: system.hh:412
byteswap.hh
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::System::thermalModel
ThermalModel * thermalModel
Definition: system.hh:425

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