gem5  v21.2.1.1
system.cc
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41 
42 #include "sim/system.hh"
43 
44 #include <algorithm>
45 
46 #include "base/compiler.hh"
47 #include "base/cprintf.hh"
49 #include "base/loader/symtab.hh"
50 #include "base/str.hh"
51 #include "base/trace.hh"
52 #include "config/the_isa.hh"
53 #include "config/use_kvm.hh"
54 #if USE_KVM
55 #include "cpu/kvm/base.hh"
56 #include "cpu/kvm/vm.hh"
57 #endif
58 #if !IS_NULL_ISA
59 #include "cpu/base.hh"
60 #endif
61 #include "cpu/thread_context.hh"
62 #include "debug/Loader.hh"
63 #include "debug/Quiesce.hh"
64 #include "debug/WorkItems.hh"
65 #include "mem/abstract_mem.hh"
66 #include "mem/physical.hh"
67 #include "params/System.hh"
68 #include "sim/byteswap.hh"
69 #include "sim/debug.hh"
70 #include "sim/redirect_path.hh"
72 
73 namespace gem5
74 {
75 
77 
78 void
80 {
81 # if !IS_NULL_ISA
82  DPRINTFS(Quiesce, context->getCpuPtr(), "activating\n");
83  context->activate();
84 # endif
85 }
86 
87 std::string
89 {
90  assert(context);
91  return csprintf("%s.threads[%d]", context->getSystemPtr()->name(),
92  context->contextId());
93 }
94 
95 void
97 {
98  context->suspend();
99  context->getSystemPtr()->workload->recordQuiesce();
100 }
101 
102 void
104 {
105  if (id == InvalidContextID) {
106  for (id = 0; id < size(); id++) {
107  if (!threads[id].context)
108  break;
109  }
110  }
111 
112  tc->setContextId(id);
113 
114  if (id >= size())
115  threads.resize(id + 1);
116 
117  fatal_if(threads[id].context,
118  "Cannot have two thread contexts with the same id (%d).", id);
119 
120  auto *sys = tc->getSystemPtr();
121 
122  auto &t = thread(id);
123  t.context = tc;
124  // Look up this thread again on resume, in case the threads vector has
125  // been reallocated.
126  t.resumeEvent = new EventFunctionWrapper(
127  [this, id](){ thread(id).resume(); }, sys->name());
128 }
129 
130 void
132 {
133  auto &t = thread(id);
134  panic_if(!t.context, "Can't replace a context which doesn't exist.");
135 # if !IS_NULL_ISA
136  if (t.resumeEvent->scheduled()) {
137  Tick when = t.resumeEvent->when();
138  t.context->getCpuPtr()->deschedule(t.resumeEvent);
139  tc->getCpuPtr()->schedule(t.resumeEvent, when);
140  }
141 # endif
142  t.context = tc;
143 }
144 
147 {
148  for (auto &thread: threads) {
150  return thread.context;
151  }
152  return nullptr;
153 }
154 
155 int
157 {
158  int count = 0;
159  for (auto &thread: threads) {
160  auto status = thread.context->status();
161  if (status != ThreadContext::Halted &&
163  count++;
164  }
165  }
166  return count;
167 }
168 
169 void
171 {
172  auto &t = thread(id);
173 # if !IS_NULL_ISA
174  [[maybe_unused]] BaseCPU *cpu = t.context->getCpuPtr();
175  DPRINTFS(Quiesce, cpu, "quiesce()\n");
176 # endif
177  t.quiesce();
178 }
179 
180 void
182 {
183 # if !IS_NULL_ISA
184  auto &t = thread(id);
185  BaseCPU *cpu = t.context->getCpuPtr();
186 
187  DPRINTFS(Quiesce, cpu, "quiesceTick until %u\n", when);
188  t.quiesce();
189 
190  cpu->reschedule(t.resumeEvent, when, true);
191 # endif
192 }
193 
195 
197  : SimObject(p), _systemPort("system_port", this),
198  multiThread(p.multi_thread),
200  physProxy(_systemPort, p.cache_line_size),
202 #if USE_KVM
203  kvmVM(p.kvm_vm),
204 #endif
205  physmem(name() + ".physmem", p.memories, p.mmap_using_noreserve,
206  p.shared_backstore),
207  ShadowRomRanges(p.shadow_rom_ranges.begin(),
208  p.shadow_rom_ranges.end()),
209  memoryMode(p.mem_mode),
210  _cacheLineSize(p.cache_line_size),
211  numWorkIds(p.num_work_ids),
212  thermalModel(p.thermal_model),
213  _m5opRange(p.m5ops_base ?
214  RangeSize(p.m5ops_base, 0x10000) :
215  AddrRange(1, 0)), // Create an empty range if disabled
216  redirectPaths(p.redirect_paths)
217 {
218  panic_if(!workload, "No workload set for system %s "
219  "(could use StubWorkload?).", name());
220  workload->setSystem(this);
221 
222  // add self to global system list
223  systemList.push_back(this);
224 
225 #if USE_KVM
226  if (kvmVM) {
227  kvmVM->setSystem(this);
228  }
229 #endif
230 
231  // check if the cache line size is a value known to work
232  if (_cacheLineSize != 16 && _cacheLineSize != 32 &&
233  _cacheLineSize != 64 && _cacheLineSize != 128) {
234  warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
235  }
236 
237  // Get the generic system requestor IDs
238  [[maybe_unused]] RequestorID tmp_id;
239  tmp_id = getRequestorId(this, "writebacks");
240  assert(tmp_id == Request::wbRequestorId);
241  tmp_id = getRequestorId(this, "functional");
242  assert(tmp_id == Request::funcRequestorId);
243  tmp_id = getRequestorId(this, "interrupt");
244  assert(tmp_id == Request::intRequestorId);
245 
246  // increment the number of running systems
248 
249  // Set back pointers to the system in all memories
250  for (int x = 0; x < params().memories.size(); x++)
251  params().memories[x]->system(this);
252 }
253 
255 {
256  for (uint32_t j = 0; j < numWorkIds; j++)
257  delete workItemStats[j];
258 }
259 
260 Port &
261 System::getPort(const std::string &if_name, PortID idx)
262 {
263  // no need to distinguish at the moment (besides checking)
264  return _systemPort;
265 }
266 
267 void
268 System::setMemoryMode(enums::MemoryMode mode)
269 {
270  assert(drainState() == DrainState::Drained);
271  memoryMode = mode;
272 }
273 
274 void
276 {
277  threads.insert(tc, assigned);
278 
280 
281  for (auto *e: liveEvents)
282  tc->schedule(e);
283 }
284 
285 bool
287 {
288  bool all = true;
289  liveEvents.push_back(event);
290  for (auto *tc: threads)
291  all = tc->schedule(event) && all;
292  return all;
293 }
294 
295 bool
297 {
298  bool all = true;
299  liveEvents.remove(event);
300  for (auto *tc: threads)
301  all = tc->remove(event) && all;
302  return all;
303 }
304 
305 void
307 {
308  auto *otc = threads[context_id];
309  threads.replace(tc, context_id);
310 
312 
313  for (auto *e: liveEvents) {
314  otc->remove(e);
315  tc->schedule(e);
316  }
317 }
318 
319 bool
321 {
322 #if USE_KVM
323  if (threads.empty())
324  return false;
325 
326  for (auto *tc: threads) {
327  if (!dynamic_cast<BaseKvmCPU *>(tc->getCpuPtr()))
328  return false;
329  }
330 
331  return true;
332 #else
333  return false;
334 #endif
335 }
336 
337 Addr
339 {
340  return physmem.totalSize();
341 }
342 
343 bool
345 {
346  return physmem.isMemAddr(addr);
347 }
348 
349 void
351  memory::AbstractMemory *deviceMemory)
352 {
353  deviceMemMap[requestor_id].push_back(deviceMemory);
354 }
355 
356 bool
358 {
359  if (!deviceMemMap.count(pkt->requestorId())) {
360  return false;
361  }
362 
363  return (getDeviceMemory(pkt) != nullptr);
364 }
365 
368 {
369  const RequestorID& rid = pkt->requestorId();
370 
371  panic_if(!deviceMemMap.count(rid),
372  "No device memory found for Requestor %d\n", rid);
373 
374  for (auto& mem : deviceMemMap.at(rid)) {
375  if (pkt->getAddrRange().isSubset(mem->getAddrRange())) {
376  return mem;
377  }
378  }
379 
380  return nullptr;
381 }
382 
383 void
385 {
386  for (auto &t: threads.threads) {
387  Tick when = 0;
388  if (t.resumeEvent && t.resumeEvent->scheduled())
389  when = t.resumeEvent->when();
390  ContextID id = t.context->contextId();
391  paramOut(cp, csprintf("quiesceEndTick_%d", id), when);
392  }
393 
394  // also serialize the memories in the system
395  physmem.serializeSection(cp, "physmem");
396 }
397 
398 
399 void
401 {
402  for (auto &t: threads.threads) {
403  Tick when = 0;
404  ContextID id = t.context->contextId();
405  if (!optParamIn(cp, csprintf("quiesceEndTick_%d", id), when) ||
406  !when || !t.resumeEvent) {
407  continue;
408  }
409 # if !IS_NULL_ISA
410  t.context->getCpuPtr()->schedule(t.resumeEvent, when);
411 # endif
412  }
413 
414  // also unserialize the memories in the system
415  physmem.unserializeSection(cp, "physmem");
416 }
417 
418 void
420 {
422 
423  for (uint32_t j = 0; j < numWorkIds ; j++) {
425  std::stringstream namestr;
426  ccprintf(namestr, "work_item_type%d", j);
427  workItemStats[j]->init(20)
428  .name(namestr.str())
429  .desc("Run time stat for" + namestr.str())
430  .prereq(*workItemStats[j]);
431  }
432 }
433 
434 void
435 System::workItemEnd(uint32_t tid, uint32_t workid)
436 {
437  std::pair<uint32_t,uint32_t> p(tid, workid);
438  if (!lastWorkItemStarted.count(p))
439  return;
440 
441  Tick samp = curTick() - lastWorkItemStarted[p];
442  DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
443 
444  if (workid >= numWorkIds)
445  fatal("Got workid greater than specified in system configuration\n");
446 
447  workItemStats[workid]->sample(samp);
448  lastWorkItemStarted.erase(p);
449 }
450 
451 bool
452 System::trapToGdb(int signal, ContextID ctx_id) const
453 {
454  return workload->trapToGdb(signal, ctx_id);
455 }
456 
457 void
459 {
460  std::ios::fmtflags flags(std::cerr.flags());
461 
464  for (; i != end; ++i) {
465  System *sys = *i;
466  std::cerr << "System " << sys->name() << ": " << std::hex << sys
467  << std::endl;
468  }
469 
470  std::cerr.flags(flags);
471 }
472 
473 void
475 {
477 }
478 
479 std::string
480 System::stripSystemName(const std::string& requestor_name) const
481 {
482  if (startswith(requestor_name, name())) {
483  return requestor_name.substr(name().size() + 1);
484  } else {
485  return requestor_name;
486  }
487 }
488 
491 {
493 
494  // number of occurrences of the SimObject pointer
495  // in the requestor list.
496  auto obj_number = 0;
497 
498  for (int i = 0; i < requestors.size(); i++) {
499  if (requestors[i].obj == obj) {
500  id = i;
501  obj_number++;
502  }
503  }
504 
505  fatal_if(obj_number > 1,
506  "Cannot lookup RequestorID by SimObject pointer: "
507  "More than one requestor is sharing the same SimObject\n");
508 
509  return id;
510 }
511 
513 System::lookupRequestorId(const std::string& requestor_name) const
514 {
515  std::string name = stripSystemName(requestor_name);
516 
517  for (int i = 0; i < requestors.size(); i++) {
518  if (requestors[i].req_name == name) {
519  return i;
520  }
521  }
522 
524 }
525 
527 System::getGlobalRequestorId(const std::string& requestor_name)
528 {
529  return _getRequestorId(nullptr, requestor_name);
530 }
531 
533 System::getRequestorId(const SimObject* requestor, std::string subrequestor)
534 {
535  auto requestor_name = leafRequestorName(requestor, subrequestor);
536  return _getRequestorId(requestor, requestor_name);
537 }
538 
541  const std::string& requestor_name)
542 {
543  std::string name = stripSystemName(requestor_name);
544 
545  // CPUs in switch_cpus ask for ids again after switching
546  for (int i = 0; i < requestors.size(); i++) {
547  if (requestors[i].req_name == name) {
548  return i;
549  }
550  }
551 
552  // Verify that the statistics haven't been enabled yet
553  // Otherwise objects will have sized their stat buckets and
554  // they will be too small
555 
556  if (statistics::enabled()) {
557  fatal("Can't request a requestorId after regStats(). "
558  "You must do so in init().\n");
559  }
560 
561  // Generate a new RequestorID incrementally
562  RequestorID requestor_id = requestors.size();
563 
564  // Append the new Requestor metadata to the group of system Requestors.
565  requestors.emplace_back(requestor, name, requestor_id);
566 
567  return requestors.back().id;
568 }
569 
570 std::string
572  const std::string& subrequestor)
573 {
574  if (subrequestor.empty()) {
575  return requestor->name();
576  } else {
577  // Get the full requestor name by appending the subrequestor name to
578  // the root SimObject requestor name
579  return requestor->name() + "." + subrequestor;
580  }
581 }
582 
583 std::string
585 {
586  if (requestor_id >= requestors.size())
587  fatal("Invalid requestor_id passed to getRequestorName()\n");
588 
589  const auto& requestor_info = requestors[requestor_id];
590  return requestor_info.req_name;
591 }
592 
593 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::System::addDeviceMemory
void addDeviceMemory(RequestorID requestorId, memory::AbstractMemory *deviceMemory)
Add a physical memory range for a device.
Definition: system.cc:350
gem5::System::lastWorkItemStarted
std::map< std::pair< uint32_t, uint32_t >, Tick > lastWorkItemStarted
Definition: system.hh:586
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::System::Threads::size
int size() const
Definition: system.hh:214
gem5::System::workItemEnd
void workItemEnd(uint32_t tid, uint32_t workid)
Definition: system.cc:435
system.hh
gem5::System::lookupRequestorId
RequestorID lookupRequestorId(const SimObject *obj) const
Looks up the RequestorID for a given SimObject returns an invalid RequestorID (invldRequestorId) if n...
Definition: system.cc:490
gem5::System::numWorkIds
uint32_t numWorkIds
Definition: system.hh:413
gem5::System::Threads::Thread::resume
void resume()
Definition: system.cc:79
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::System::liveEvents
std::list< PCEvent * > liveEvents
Definition: system.hh:108
gem5::System::Threads::Thread::context
ThreadContext * context
Definition: system.hh:122
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:815
abstract_mem.hh
warn_once
#define warn_once(...)
Definition: logging.hh:250
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:327
gem5::System::schedule
bool schedule(PCEvent *event) override
Definition: system.cc:286
gem5::InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:247
gem5::System::Threads::quiesce
void quiesce(ContextID id)
Definition: system.cc:170
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::System::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Additional function to return the Port of a memory object.
Definition: system.cc:261
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Serializable::serializeSection
void serializeSection(CheckpointOut &cp, const char *name) const
Serialize an object into a new section.
Definition: serialize.cc:74
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::KvmVM::setSystem
void setSystem(System *s)
Initialize system pointer.
Definition: vm.cc:546
redirect_path.hh
gem5::System::workItemStats
std::map< uint32_t, statistics::Histogram * > workItemStats
Definition: system.hh:587
gem5::startswith
bool startswith(const char *s, const char *prefix)
Return true if 's' starts with the prefix string 'prefix'.
Definition: str.hh:229
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:330
gem5::System::Threads::replace
void replace(ThreadContext *tc, ContextID id)
Definition: system.cc:131
gem5::System::Threads::end
const_iterator end() const
Definition: system.hh:232
gem5::System::setMemoryMode
void setMemoryMode(enums::MemoryMode mode)
Change the memory mode of the system.
Definition: system.cc:268
gem5::ThreadContext::activate
virtual void activate()=0
Set the status to Active.
gem5::System::numSystemsRunning
static int numSystemsRunning
Definition: system.hh:596
std::vector
STL vector class.
Definition: stl.hh:37
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::System::System
System(const Params &p)
Definition: system.cc:196
gem5::System::regStats
void regStats() override
Callback to set stat parameters.
Definition: system.cc:419
gem5::System::getDeviceMemory
memory::AbstractMemory * getDeviceMemory(const PacketPtr &pkt) const
Return a pointer to the device memory.
Definition: system.cc:367
gem5::AddrRange::isSubset
bool isSubset(const AddrRange &r) const
Determine if this range is a subset of another range, i.e.
Definition: addr_range.hh:445
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:262
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ThreadContext::status
virtual Status status() const =0
gem5::System::_getRequestorId
RequestorID _getRequestorId(const SimObject *requestor, const std::string &requestor_name)
helper function for getRequestorId
Definition: system.cc:540
gem5::System::stripSystemName
std::string stripSystemName(const std::string &requestor_name) const
Strips off the system name from a requestor name.
Definition: system.cc:480
gem5::System::Threads::quiesceTick
void quiesceTick(ContextID id, Tick when)
Definition: system.cc:181
gem5::System::requestors
std::vector< RequestorInfo > requestors
This array is a per-system list of all devices capable of issuing a memory system request and an asso...
Definition: system.hh:420
str.hh
gem5::System::Threads::empty
bool empty() const
Definition: system.hh:215
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::System::redirectPaths
std::vector< RedirectPath * > redirectPaths
Definition: system.hh:614
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2126
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::System::Threads::threads
std::vector< Thread > threads
Definition: system.hh:131
gem5::System::_systemPort
SystemPort _systemPort
Definition: system.hh:109
gem5::System::deviceMemMap
std::unordered_map< RequestorID, std::vector< memory::AbstractMemory * > > deviceMemMap
Definition: system.hh:113
gem5::System
Definition: system.hh:75
gem5::System::kvmVM
KvmVM *const kvmVM
Definition: system.hh:401
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::System::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: system.cc:344
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Packet::requestorId
RequestorID requestorId() const
Definition: packet.hh:767
gem5::Serializable::unserializeSection
void unserializeSection(CheckpointIn &cp, const char *name)
Unserialize an a child object.
Definition: serialize.cc:81
gem5::System::physmem
memory::PhysicalMemory physmem
Definition: system.hh:403
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::System::systemList
static std::vector< System * > systemList
Definition: system.hh:595
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::BaseKvmCPU
Base class for KVM based CPU models.
Definition: base.hh:87
debug.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::System::getRequestorName
std::string getRequestorName(RequestorID requestor_id)
Get the name of an object for a given request id.
Definition: system.cc:584
gem5::System::getGlobalRequestorId
RequestorID getGlobalRequestorId(const std::string &requestor_name)
Registers a GLOBAL RequestorID, which is a RequestorID not related to any particular SimObject; since...
Definition: system.cc:527
gem5::Request::intRequestorId
@ intRequestorId
This requestor id is used for message signaled interrupts.
Definition: request.hh:264
gem5::Request::wbRequestorId
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
Definition: request.hh:257
gem5::System::getRequestorId
RequestorID getRequestorId(const SimObject *requestor, std::string subrequestor={})
Request an id used to create a request object in the system.
Definition: system.cc:533
cprintf.hh
compiler.hh
gem5::System::memSize
Addr memSize() const
Amount of physical memory that exists.
Definition: system.cc:338
gem5::System::memoryMode
enums::MemoryMode memoryMode
Definition: system.hh:407
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::Threads::Thread::quiesce
void quiesce() const
Definition: system.cc:96
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:71
std::pair
STL pair class.
Definition: stl.hh:58
gem5::System::Threads::begin
const_iterator begin() const
Definition: system.hh:231
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::System::remove
bool remove(PCEvent *event) override
Definition: system.cc:296
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
DPRINTFS
#define DPRINTFS(x, s,...)
Definition: trace.hh:193
gem5::Workload::trapToGdb
bool trapToGdb(int signal, ContextID ctx_id)
Definition: workload.cc:80
base.hh
gem5::System::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: system.cc:400
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
vm.hh
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:286
gem5::System::leafRequestorName
std::string leafRequestorName(const SimObject *requestor, const std::string &subrequestor)
Helper function for constructing the full (sub)requestor name by providing the root requestor and the...
Definition: system.cc:571
gem5::System::trapToGdb
bool trapToGdb(int signal, ContextID ctx_id) const
Definition: system.cc:452
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::System::multiThread
const bool multiThread
Definition: system.hh:316
gem5::System::isDeviceMemAddr
bool isDeviceMemAddr(const PacketPtr &pkt) const
Similar to isMemAddr but for devices.
Definition: system.cc:357
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::optParamIn
bool optParamIn(CheckpointIn &cp, const std::string &name, T &param, bool do_warn=true)
This function is used for restoring optional parameters from the checkpoint.
Definition: serialize.hh:357
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
serialize_handlers.hh
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::System::ShadowRomRanges
AddrRangeList ShadowRomRanges
Definition: system.hh:405
gem5::System::init_param
uint64_t init_param
Definition: system.hh:323
gem5::Workload::replaceThreadContext
virtual void replaceThreadContext(ThreadContext *tc)
Definition: workload.cc:54
gem5::System::Threads::thread
Thread & thread(ContextID id)
Definition: system.hh:134
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:117
physical.hh
gem5::System::Threads::Thread::name
std::string name() const
Definition: system.cc:88
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::System::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: system.cc:384
gem5::System::_m5opRange
const AddrRange _m5opRange
Range for memory-mapped m5 pseudo ops.
Definition: system.hh:562
gem5::System::printSystems
static void printSystems()
Definition: system.cc:458
gem5::memory::PhysicalMemory::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: physical.cc:256
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::System::validKvmEnvironment
bool validKvmEnvironment() const
Verify gem5 configuration will support KVM emulation.
Definition: system.cc:320
gem5::System::registerThreadContext
void registerThreadContext(ThreadContext *tc, ContextID assigned=InvalidContextID)
Definition: system.cc:275
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
mem
bool_vector8 mem[]
Definition: reset_stim.h:43
gem5::System::replaceThreadContext
void replaceThreadContext(ThreadContext *tc, ContextID context_id)
Definition: system.cc:306
gem5::printSystems
void printSystems()
Definition: system.cc:474
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::memory::PhysicalMemory::totalSize
uint64_t totalSize() const
Get the total physical memory size.
Definition: physical.hh:213
gem5::Request::invldRequestorId
@ invldRequestorId
Invalid requestor id for assertion checking only.
Definition: request.hh:269
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
trace.hh
gem5::System::Threads::insert
void insert(ThreadContext *tc, ContextID id=InvalidContextID)
Definition: system.cc:103
symtab.hh
gem5::PCEventScope::schedule
virtual bool schedule(PCEvent *event)=0
gem5::Workload::setSystem
virtual void setSystem(System *sys)
Definition: workload.hh:87
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5::System::~System
~System()
Definition: system.cc:254
gem5::Workload::registerThreadContext
virtual void registerThreadContext(ThreadContext *tc)
Definition: workload.cc:39
gem5::System::Threads::findFree
ThreadContext * findFree()
Definition: system.cc:146
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::Packet::getAddrRange
AddrRange getAddrRange() const
Get address range to which this packet belongs.
Definition: packet.cc:225
object_file.hh
gem5::System::Threads::numRunning
int numRunning() const
Definition: system.cc:156
thread_context.hh
gem5::System::_cacheLineSize
const unsigned int _cacheLineSize
Definition: system.hh:409
byteswap.hh
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:423
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::System::thermalModel
ThermalModel * thermalModel
Definition: system.hh:422

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