gem5  v21.1.0.2
system.cc
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41 
42 #include "sim/system.hh"
43 
44 #include <algorithm>
45 
46 #include "base/compiler.hh"
48 #include "base/loader/symtab.hh"
49 #include "base/str.hh"
50 #include "base/trace.hh"
51 #include "config/the_isa.hh"
52 #include "config/use_kvm.hh"
53 #if USE_KVM
54 #include "cpu/kvm/base.hh"
55 #include "cpu/kvm/vm.hh"
56 #endif
57 #if THE_ISA != NULL_ISA
58 #include "cpu/base.hh"
59 #endif
60 #include "cpu/thread_context.hh"
61 #include "debug/Loader.hh"
62 #include "debug/Quiesce.hh"
63 #include "debug/WorkItems.hh"
64 #include "mem/abstract_mem.hh"
65 #include "mem/physical.hh"
66 #include "params/System.hh"
67 #include "sim/byteswap.hh"
68 #include "sim/debug.hh"
69 #include "sim/full_system.hh"
70 #include "sim/redirect_path.hh"
71 
72 namespace gem5
73 {
74 
76 
77 void
79 {
80 # if THE_ISA != NULL_ISA
81  DPRINTFS(Quiesce, context->getCpuPtr(), "activating\n");
82  context->activate();
83 # endif
84 }
85 
86 std::string
88 {
89  assert(context);
90  return csprintf("%s.threads[%d]", context->getSystemPtr()->name(),
91  context->contextId());
92 }
93 
94 void
96 {
97  context->suspend();
98  auto *workload = context->getSystemPtr()->workload;
99  if (workload)
101 }
102 
103 void
105 {
106  if (id == InvalidContextID) {
107  for (id = 0; id < size(); id++) {
108  if (!threads[id].context)
109  break;
110  }
111  }
112 
113  tc->setContextId(id);
114 
115  if (id >= size())
116  threads.resize(id + 1);
117 
118  fatal_if(threads[id].context,
119  "Cannot have two thread contexts with the same id (%d).", id);
120 
121  auto *sys = tc->getSystemPtr();
122 
123  auto &t = thread(id);
124  t.context = tc;
125  // Look up this thread again on resume, in case the threads vector has
126  // been reallocated.
127  t.resumeEvent = new EventFunctionWrapper(
128  [this, id](){ thread(id).resume(); }, sys->name());
129 }
130 
131 void
133 {
134  auto &t = thread(id);
135  panic_if(!t.context, "Can't replace a context which doesn't exist.");
136 # if THE_ISA != NULL_ISA
137  if (t.resumeEvent->scheduled()) {
138  Tick when = t.resumeEvent->when();
139  t.context->getCpuPtr()->deschedule(t.resumeEvent);
140  tc->getCpuPtr()->schedule(t.resumeEvent, when);
141  }
142 # endif
143  t.context = tc;
144 }
145 
148 {
149  for (auto &thread: threads) {
151  return thread.context;
152  }
153  return nullptr;
154 }
155 
156 int
158 {
159  int count = 0;
160  for (auto &thread: threads) {
161  auto status = thread.context->status();
162  if (status != ThreadContext::Halted &&
164  count++;
165  }
166  }
167  return count;
168 }
169 
170 void
172 {
173  auto &t = thread(id);
174 # if THE_ISA != NULL_ISA
175  GEM5_VAR_USED BaseCPU *cpu = t.context->getCpuPtr();
176  DPRINTFS(Quiesce, cpu, "quiesce()\n");
177 # endif
178  t.quiesce();
179 }
180 
181 void
183 {
184 # if THE_ISA != NULL_ISA
185  auto &t = thread(id);
186  BaseCPU *cpu = t.context->getCpuPtr();
187 
188  DPRINTFS(Quiesce, cpu, "quiesceTick until %u\n", when);
189  t.quiesce();
190 
191  cpu->reschedule(t.resumeEvent, when, true);
192 # endif
193 }
194 
196 
198  : SimObject(p), _systemPort("system_port", this),
199  multiThread(p.multi_thread),
201  physProxy(_systemPort, p.cache_line_size),
203 #if USE_KVM
204  kvmVM(p.kvm_vm),
205 #endif
206  physmem(name() + ".physmem", p.memories, p.mmap_using_noreserve,
207  p.shared_backstore),
208  ShadowRomRanges(p.shadow_rom_ranges.begin(),
209  p.shadow_rom_ranges.end()),
210  memoryMode(p.mem_mode),
211  _cacheLineSize(p.cache_line_size),
212  numWorkIds(p.num_work_ids),
213  thermalModel(p.thermal_model),
214  _m5opRange(p.m5ops_base ?
215  RangeSize(p.m5ops_base, 0x10000) :
216  AddrRange(1, 0)), // Create an empty range if disabled
217  redirectPaths(p.redirect_paths)
218 {
219  if (workload)
220  workload->setSystem(this);
221 
222  // add self to global system list
223  systemList.push_back(this);
224 
225 #if USE_KVM
226  if (kvmVM) {
227  kvmVM->setSystem(this);
228  }
229 #endif
230 
231  if (!FullSystem) {
233  assert(!memories.empty());
234  for (const auto &mem : memories) {
235  assert(!mem.interleaved());
236  memPools.emplace_back(this, mem.start(), mem.end());
237  }
238 
239  /*
240  * Set freePage to what it was before Gabe Black's page table changes
241  * so allocations don't trample the page table entries.
242  */
243  memPools[0].setFreePage(memPools[0].freePage() + 70);
244  }
245 
246  // check if the cache line size is a value known to work
247  if (_cacheLineSize != 16 && _cacheLineSize != 32 &&
248  _cacheLineSize != 64 && _cacheLineSize != 128) {
249  warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
250  }
251 
252  // Get the generic system requestor IDs
253  GEM5_VAR_USED RequestorID tmp_id;
254  tmp_id = getRequestorId(this, "writebacks");
255  assert(tmp_id == Request::wbRequestorId);
256  tmp_id = getRequestorId(this, "functional");
257  assert(tmp_id == Request::funcRequestorId);
258  tmp_id = getRequestorId(this, "interrupt");
259  assert(tmp_id == Request::intRequestorId);
260 
261  // increment the number of running systems
263 
264  // Set back pointers to the system in all memories
265  for (int x = 0; x < params().memories.size(); x++)
266  params().memories[x]->system(this);
267 }
268 
270 {
271  for (uint32_t j = 0; j < numWorkIds; j++)
272  delete workItemStats[j];
273 }
274 
275 Port &
276 System::getPort(const std::string &if_name, PortID idx)
277 {
278  // no need to distinguish at the moment (besides checking)
279  return _systemPort;
280 }
281 
282 void
283 System::setMemoryMode(enums::MemoryMode mode)
284 {
285  assert(drainState() == DrainState::Drained);
286  memoryMode = mode;
287 }
288 
289 void
291 {
292  threads.insert(tc, assigned);
293 
294  if (workload)
296 
297  for (auto *e: liveEvents)
298  tc->schedule(e);
299 }
300 
301 bool
303 {
304  bool all = true;
305  liveEvents.push_back(event);
306  for (auto *tc: threads)
307  all = tc->schedule(event) && all;
308  return all;
309 }
310 
311 bool
313 {
314  bool all = true;
315  liveEvents.remove(event);
316  for (auto *tc: threads)
317  all = tc->remove(event) && all;
318  return all;
319 }
320 
321 void
323 {
324  auto *otc = threads[context_id];
325  threads.replace(tc, context_id);
326 
327  if (workload)
329 
330  for (auto *e: liveEvents) {
331  otc->remove(e);
332  tc->schedule(e);
333  }
334 }
335 
336 bool
338 {
339 #if USE_KVM
340  if (threads.empty())
341  return false;
342 
343  for (auto *tc: threads) {
344  if (!dynamic_cast<BaseKvmCPU *>(tc->getCpuPtr()))
345  return false;
346  }
347 
348  return true;
349 #else
350  return false;
351 #endif
352 }
353 
354 Addr
355 System::allocPhysPages(int npages, int poolID)
356 {
357  assert(!FullSystem);
358  return memPools[poolID].allocate(npages);
359 }
360 
361 Addr
362 System::memSize(int poolID) const
363 {
364  assert(!FullSystem);
365  return memPools[poolID].totalBytes();
366 }
367 
368 Addr
369 System::freeMemSize(int poolID) const
370 {
371  assert(!FullSystem);
372  return memPools[poolID].freeBytes();
373 }
374 
375 bool
377 {
378  return physmem.isMemAddr(addr);
379 }
380 
381 void
383  memory::AbstractMemory *deviceMemory)
384 {
385  deviceMemMap[requestor_id].push_back(deviceMemory);
386 }
387 
388 bool
390 {
391  if (!deviceMemMap.count(pkt->requestorId())) {
392  return false;
393  }
394 
395  return (getDeviceMemory(pkt) != nullptr);
396 }
397 
400 {
401  const RequestorID& rid = pkt->requestorId();
402 
403  panic_if(!deviceMemMap.count(rid),
404  "No device memory found for Requestor %d\n", rid);
405 
406  for (auto& mem : deviceMemMap.at(rid)) {
407  if (pkt->getAddrRange().isSubset(mem->getAddrRange())) {
408  return mem;
409  }
410  }
411 
412  return nullptr;
413 }
414 
415 void
417 {
418  for (auto &t: threads.threads) {
419  Tick when = 0;
420  if (t.resumeEvent && t.resumeEvent->scheduled())
421  when = t.resumeEvent->when();
422  ContextID id = t.context->contextId();
423  paramOut(cp, csprintf("quiesceEndTick_%d", id), when);
424  }
425 
426  std::vector<Addr> ptrs;
427  std::vector<Addr> limits;
428 
429  for (const auto& memPool : memPools) {
430  ptrs.push_back(memPool.freePageAddr());
431  limits.push_back(memPool.totalBytes());
432  }
433 
434  SERIALIZE_CONTAINER(ptrs);
435  SERIALIZE_CONTAINER(limits);
436 
437  // also serialize the memories in the system
438  physmem.serializeSection(cp, "physmem");
439 }
440 
441 
442 void
444 {
445  for (auto &t: threads.threads) {
446  Tick when = 0;
447  ContextID id = t.context->contextId();
448  if (!optParamIn(cp, csprintf("quiesceEndTick_%d", id), when) ||
449  !when || !t.resumeEvent) {
450  continue;
451  }
452 # if THE_ISA != NULL_ISA
453  t.context->getCpuPtr()->schedule(t.resumeEvent, when);
454 # endif
455  }
456 
457  std::vector<Addr> ptrs;
458  std::vector<Addr> limits;
459 
460  UNSERIALIZE_CONTAINER(ptrs);
461  UNSERIALIZE_CONTAINER(limits);
462 
463  assert(ptrs.size() == limits.size());
464  for (size_t i = 0; i < ptrs.size(); i++)
465  memPools.emplace_back(this, ptrs[i], limits[i]);
466 
467  // also unserialize the memories in the system
468  physmem.unserializeSection(cp, "physmem");
469 }
470 
471 void
473 {
475 
476  for (uint32_t j = 0; j < numWorkIds ; j++) {
478  std::stringstream namestr;
479  ccprintf(namestr, "work_item_type%d", j);
480  workItemStats[j]->init(20)
481  .name(namestr.str())
482  .desc("Run time stat for" + namestr.str())
483  .prereq(*workItemStats[j]);
484  }
485 }
486 
487 void
488 System::workItemEnd(uint32_t tid, uint32_t workid)
489 {
490  std::pair<uint32_t,uint32_t> p(tid, workid);
491  if (!lastWorkItemStarted.count(p))
492  return;
493 
494  Tick samp = curTick() - lastWorkItemStarted[p];
495  DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
496 
497  if (workid >= numWorkIds)
498  fatal("Got workid greater than specified in system configuration\n");
499 
500  workItemStats[workid]->sample(samp);
501  lastWorkItemStarted.erase(p);
502 }
503 
504 bool
505 System::trapToGdb(int signal, ContextID ctx_id) const
506 {
507  return workload && workload->trapToGdb(signal, ctx_id);
508 }
509 
510 void
512 {
513  std::ios::fmtflags flags(std::cerr.flags());
514 
517  for (; i != end; ++i) {
518  System *sys = *i;
519  std::cerr << "System " << sys->name() << ": " << std::hex << sys
520  << std::endl;
521  }
522 
523  std::cerr.flags(flags);
524 }
525 
526 void
528 {
530 }
531 
532 std::string
533 System::stripSystemName(const std::string& requestor_name) const
534 {
535  if (startswith(requestor_name, name())) {
536  return requestor_name.substr(name().size() + 1);
537  } else {
538  return requestor_name;
539  }
540 }
541 
544 {
546 
547  // number of occurrences of the SimObject pointer
548  // in the requestor list.
549  auto obj_number = 0;
550 
551  for (int i = 0; i < requestors.size(); i++) {
552  if (requestors[i].obj == obj) {
553  id = i;
554  obj_number++;
555  }
556  }
557 
558  fatal_if(obj_number > 1,
559  "Cannot lookup RequestorID by SimObject pointer: "
560  "More than one requestor is sharing the same SimObject\n");
561 
562  return id;
563 }
564 
566 System::lookupRequestorId(const std::string& requestor_name) const
567 {
568  std::string name = stripSystemName(requestor_name);
569 
570  for (int i = 0; i < requestors.size(); i++) {
571  if (requestors[i].req_name == name) {
572  return i;
573  }
574  }
575 
577 }
578 
580 System::getGlobalRequestorId(const std::string& requestor_name)
581 {
582  return _getRequestorId(nullptr, requestor_name);
583 }
584 
586 System::getRequestorId(const SimObject* requestor, std::string subrequestor)
587 {
588  auto requestor_name = leafRequestorName(requestor, subrequestor);
589  return _getRequestorId(requestor, requestor_name);
590 }
591 
594  const std::string& requestor_name)
595 {
596  std::string name = stripSystemName(requestor_name);
597 
598  // CPUs in switch_cpus ask for ids again after switching
599  for (int i = 0; i < requestors.size(); i++) {
600  if (requestors[i].req_name == name) {
601  return i;
602  }
603  }
604 
605  // Verify that the statistics haven't been enabled yet
606  // Otherwise objects will have sized their stat buckets and
607  // they will be too small
608 
609  if (statistics::enabled()) {
610  fatal("Can't request a requestorId after regStats(). "
611  "You must do so in init().\n");
612  }
613 
614  // Generate a new RequestorID incrementally
615  RequestorID requestor_id = requestors.size();
616 
617  // Append the new Requestor metadata to the group of system Requestors.
618  requestors.emplace_back(requestor, name, requestor_id);
619 
620  return requestors.back().id;
621 }
622 
623 std::string
625  const std::string& subrequestor)
626 {
627  if (subrequestor.empty()) {
628  return requestor->name();
629  } else {
630  // Get the full requestor name by appending the subrequestor name to
631  // the root SimObject requestor name
632  return requestor->name() + "." + subrequestor;
633  }
634 }
635 
636 std::string
638 {
639  if (requestor_id >= requestors.size())
640  fatal("Invalid requestor_id passed to getRequestorName()\n");
641 
642  const auto& requestor_info = requestors[requestor_id];
643  return requestor_info.req_name;
644 }
645 
646 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::System::addDeviceMemory
void addDeviceMemory(RequestorID requestorId, memory::AbstractMemory *deviceMemory)
Add a physical memory range for a device.
Definition: system.cc:382
gem5::System::lastWorkItemStarted
std::map< std::pair< uint32_t, uint32_t >, Tick > lastWorkItemStarted
Definition: system.hh:612
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::System::Threads::size
int size() const
Definition: system.hh:216
gem5::System::workItemEnd
void workItemEnd(uint32_t tid, uint32_t workid)
Definition: system.cc:488
system.hh
gem5::System::lookupRequestorId
RequestorID lookupRequestorId(const SimObject *obj) const
Looks up the RequestorID for a given SimObject returns an invalid RequestorID (invldRequestorId) if n...
Definition: system.cc:543
gem5::System::numWorkIds
uint32_t numWorkIds
Definition: system.hh:435
gem5::System::Threads::Thread::resume
void resume()
Definition: system.cc:78
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:121
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::System::liveEvents
std::list< PCEvent * > liveEvents
Definition: system.hh:110
gem5::System::Threads::Thread::context
ThreadContext * context
Definition: system.hh:124
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:661
abstract_mem.hh
warn_once
#define warn_once(...)
Definition: logging.hh:249
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::System::physProxy
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition: system.hh:332
gem5::System::memPools
std::vector< MemPool > memPools
Memory allocation objects for all physical memories in the system.
Definition: system.hh:326
gem5::System::schedule
bool schedule(PCEvent *event) override
Definition: system.cc:302
gem5::InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:247
gem5::System::Threads::quiesce
void quiesce(ContextID id)
Definition: system.cc:171
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::System::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Additional function to return the Port of a memory object.
Definition: system.cc:276
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Serializable::serializeSection
void serializeSection(CheckpointOut &cp, const char *name) const
Serialize an object into a new section.
Definition: serialize.cc:74
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::KvmVM::setSystem
void setSystem(System *s)
Initialize system pointer.
Definition: vm.cc:544
redirect_path.hh
gem5::System::workItemStats
std::map< uint32_t, statistics::Histogram * > workItemStats
Definition: system.hh:613
gem5::startswith
bool startswith(const char *s, const char *prefix)
Return true if 's' starts with the prefix string 'prefix'.
Definition: str.hh:242
gem5::System::workload
Workload * workload
OS kernel.
Definition: system.hh:335
gem5::System::Threads::replace
void replace(ThreadContext *tc, ContextID id)
Definition: system.cc:132
gem5::System::Threads::end
const_iterator end() const
Definition: system.hh:234
gem5::System::setMemoryMode
void setMemoryMode(enums::MemoryMode mode)
Change the memory mode of the system.
Definition: system.cc:283
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
gem5::ThreadContext::activate
virtual void activate()=0
Set the status to Active.
gem5::System::numSystemsRunning
static int numSystemsRunning
Definition: system.hh:622
std::vector
STL vector class.
Definition: stl.hh:37
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::System::System
System(const Params &p)
Definition: system.cc:197
gem5::System::regStats
void regStats() override
Callback to set stat parameters.
Definition: system.cc:472
gem5::System::getDeviceMemory
memory::AbstractMemory * getDeviceMemory(const PacketPtr &pkt) const
Return a pointer to the device memory.
Definition: system.cc:399
gem5::AddrRange::isSubset
bool isSubset(const AddrRange &r) const
Determine if this range is a subset of another range, i.e.
Definition: addr_range.hh:413
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ThreadContext::status
virtual Status status() const =0
gem5::System::_getRequestorId
RequestorID _getRequestorId(const SimObject *requestor, const std::string &requestor_name)
helper function for getRequestorId
Definition: system.cc:593
gem5::System::stripSystemName
std::string stripSystemName(const std::string &requestor_name) const
Strips off the system name from a requestor name.
Definition: system.cc:533
gem5::System::Threads::quiesceTick
void quiesceTick(ContextID id, Tick when)
Definition: system.cc:182
gem5::System::requestors
std::vector< RequestorInfo > requestors
This array is a per-system list of all devices capable of issuing a memory system request and an asso...
Definition: system.hh:442
str.hh
gem5::System::Threads::empty
bool empty() const
Definition: system.hh:217
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::System::redirectPaths
std::vector< RedirectPath * > redirectPaths
Definition: system.hh:640
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::System::Threads::threads
std::vector< Thread > threads
Definition: system.hh:133
gem5::System::_systemPort
SystemPort _systemPort
Definition: system.hh:111
gem5::System::deviceMemMap
std::unordered_map< RequestorID, std::vector< memory::AbstractMemory * > > deviceMemMap
Definition: system.hh:115
gem5::System
Definition: system.hh:77
gem5::System::kvmVM
KvmVM *const kvmVM
Definition: system.hh:423
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::System::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: system.cc:376
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Packet::requestorId
RequestorID requestorId() const
Definition: packet.hh:767
gem5::Serializable::unserializeSection
void unserializeSection(CheckpointIn &cp, const char *name)
Unserialize an a child object.
Definition: serialize.cc:81
gem5::System::physmem
memory::PhysicalMemory physmem
Definition: system.hh:425
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::System::systemList
static std::vector< System * > systemList
Definition: system.hh:621
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::BaseKvmCPU
Base class for KVM based CPU models.
Definition: base.hh:87
debug.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::memory::AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:110
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PCEvent
Definition: pc_event.hh:45
gem5::System::getRequestorName
std::string getRequestorName(RequestorID requestor_id)
Get the name of an object for a given request id.
Definition: system.cc:637
gem5::System::getGlobalRequestorId
RequestorID getGlobalRequestorId(const std::string &requestor_name)
Registers a GLOBAL RequestorID, which is a RequestorID not related to any particular SimObject; since...
Definition: system.cc:580
gem5::BaseCPU
Definition: base.hh:107
gem5::System::getRequestorId
RequestorID getRequestorId(const SimObject *requestor, std::string subrequestor={})
Request an id used to create a request object in the system.
Definition: system.cc:586
gem5::EventManager::reschedule
void reschedule(Event &event, Tick when, bool always=false)
Definition: eventq.hh:1037
compiler.hh
gem5::System::memoryMode
enums::MemoryMode memoryMode
Definition: system.hh:429
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::DrainState::Drained
@ Drained
Buffers drained, ready for serialization/handover.
gem5::System::Threads::Thread::quiesce
void quiesce() const
Definition: system.cc:95
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
std::pair
STL pair class.
Definition: stl.hh:58
gem5::System::allocPhysPages
Addr allocPhysPages(int npages, int poolID=0)
Allocate npages contiguous unused physical pages.
Definition: system.cc:355
gem5::System::Threads::begin
const_iterator begin() const
Definition: system.hh:233
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::System::freeMemSize
Addr freeMemSize(int poolID=0) const
Amount of physical memory that is still free.
Definition: system.cc:369
gem5::System::remove
bool remove(PCEvent *event) override
Definition: system.cc:312
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
DPRINTFS
#define DPRINTFS(x, s,...)
Definition: trace.hh:193
gem5::Workload::trapToGdb
bool trapToGdb(int signal, ContextID ctx_id)
Definition: workload.cc:80
gem5::System::memSize
Addr memSize(int poolID=0) const
Amount of physical memory that exists.
Definition: system.cc:362
base.hh
gem5::System::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: system.cc:443
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
vm.hh
full_system.hh
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:280
gem5::System::leafRequestorName
std::string leafRequestorName(const SimObject *requestor, const std::string &subrequestor)
Helper function for constructing the full (sub)requestor name by providing the root requestor and the...
Definition: system.cc:624
gem5::System::trapToGdb
bool trapToGdb(int signal, ContextID ctx_id) const
Definition: system.cc:505
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::System::multiThread
const bool multiThread
Definition: system.hh:318
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::System::isDeviceMemAddr
bool isDeviceMemAddr(const PacketPtr &pkt) const
Similar to isMemAddr but for devices.
Definition: system.cc:389
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::optParamIn
bool optParamIn(CheckpointIn &cp, const std::string &name, T &param, bool do_warn=true)
This function is used for restoring optional parameters from the checkpoint.
Definition: serialize.hh:357
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:260
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::System::ShadowRomRanges
AddrRangeList ShadowRomRanges
Definition: system.hh:427
gem5::System::init_param
uint64_t init_param
Definition: system.hh:328
gem5::Workload::replaceThreadContext
virtual void replaceThreadContext(ThreadContext *tc)
Definition: workload.cc:54
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::System::Threads::thread
Thread & thread(ContextID id)
Definition: system.hh:136
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:116
physical.hh
gem5::System::Threads::Thread::name
std::string name() const
Definition: system.cc:87
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::System::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: system.cc:416
gem5::System::_m5opRange
const AddrRange _m5opRange
Range for memory-mapped m5 pseudo ops.
Definition: system.hh:584
gem5::System::printSystems
static void printSystems()
Definition: system.cc:511
gem5::memory::PhysicalMemory::isMemAddr
bool isMemAddr(Addr addr) const
Check if a physical address is within a range of a memory that is part of the global address map.
Definition: physical.cc:256
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::System::validKvmEnvironment
bool validKvmEnvironment() const
Verify gem5 configuration will support KVM emulation.
Definition: system.cc:337
gem5::Request::wbRequestorId
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
Definition: request.hh:255
gem5::System::registerThreadContext
void registerThreadContext(ThreadContext *tc, ContextID assigned=InvalidContextID)
Definition: system.cc:290
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
mem
bool_vector8 mem[]
Definition: reset_stim.h:43
gem5::System::replaceThreadContext
void replaceThreadContext(ThreadContext *tc, ContextID context_id)
Definition: system.cc:322
gem5::printSystems
void printSystems()
Definition: system.cc:527
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
trace.hh
gem5::System::Threads::insert
void insert(ThreadContext *tc, ContextID id=InvalidContextID)
Definition: system.cc:104
symtab.hh
gem5::PCEventScope::schedule
virtual bool schedule(PCEvent *event)=0
gem5::Workload::setSystem
virtual void setSystem(System *sys)
Definition: workload.hh:85
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:71
std::list< AddrRange >
gem5::System::~System
~System()
Definition: system.cc:269
gem5::Workload::registerThreadContext
virtual void registerThreadContext(ThreadContext *tc)
Definition: workload.cc:39
gem5::System::Threads::findFree
ThreadContext * findFree()
Definition: system.cc:147
gem5::Request::intRequestorId
@ intRequestorId
This requestor id is used for message signaled interrupts.
Definition: request.hh:262
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Workload::recordQuiesce
void recordQuiesce()
Definition: workload.hh:87
gem5::Packet::getAddrRange
AddrRange getAddrRange() const
Get address range to which this packet belongs.
Definition: packet.cc:225
gem5::memory::PhysicalMemory::getConfAddrRanges
AddrRangeList getConfAddrRanges() const
Get the memory ranges for all memories that are to be reported to the configuration table.
Definition: physical.cc:262
object_file.hh
gem5::System::Threads::numRunning
int numRunning() const
Definition: system.cc:157
thread_context.hh
gem5::System::_cacheLineSize
const unsigned int _cacheLineSize
Definition: system.hh:431
gem5::Request::invldRequestorId
@ invldRequestorId
Invalid requestor id for assertion checking only.
Definition: request.hh:267
byteswap.hh
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::System::thermalModel
ThermalModel * thermalModel
Definition: system.hh:444

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