gem5  v21.1.0.2
misc.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_MISC_HH__
30 #define __ARCH_POWER_INSTS_MISC_HH__
31 
33 
34 namespace gem5
35 {
36 
37 namespace PowerISA
38 {
39 
43 class MiscOp : public PowerStaticInst
44 {
45  protected:
47 
48  std::string generateDisassembly(
49  Addr pc, const loader::SymbolTable *symtab) const override;
50 };
51 
52 } // namespace PowerISA
53 } // namespace gem5
54 
55 #endif //__ARCH_POWER_INSTS_MISC_HH__
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::PowerISA::MiscOp
Class for misc operations.
Definition: misc.hh:43
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::PowerStaticInst::PowerStaticInst
PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:48
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
static_inst.hh
gem5::PowerISA::PowerStaticInst
Definition: static_inst.hh:42
gem5::PowerISA::MiscOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:37

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