gem5 v24.0.0.0
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static_inst.hh
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1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_POWER_INSTS_STATICINST_HH__
30#define __ARCH_POWER_INSTS_STATICINST_HH__
31
32#include "arch/power/pcstate.hh"
33#include "arch/power/types.hh"
34#include "base/trace.hh"
35#include "cpu/static_inst.hh"
36#include "cpu/thread_context.hh"
37
38namespace gem5
39{
40
41namespace PowerISA
42{
43
45{
46 protected:
48
49 // Constructor
50 PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
51 : StaticInst(mnem, __opClass), machInst(_machInst)
52 {
53 }
54
55 // Insert a condition value into a CR (condition register) field
56 inline uint32_t
57 insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
58 {
59 uint32_t bits = value << ((7 - bf) * 4);
60 uint32_t mask = ~(0xf << ((7 - bf) * 4));
61 return (cr & mask) | bits;
62 }
63
66 void
67 printReg(std::ostream &os, RegId reg) const;
68
69 std::string generateDisassembly(
70 Addr pc, const loader::SymbolTable *symtab) const override;
71
72 void
73 advancePC(PCStateBase &pc_state) const override
74 {
75 pc_state.as<PCState>().advance();
76 }
77
78 void
79 advancePC(ThreadContext *tc) const override
80 {
81 PCState pc = tc->pcState().as<PCState>();
82 pc.advance();
83 tc->pcState(pc);
84 }
85
86 std::unique_ptr<PCStateBase>
87 buildRetPC(const PCStateBase &cur_pc,
88 const PCStateBase &call_pc) const override
89 {
90 PCStateBase *ret_pc = call_pc.clone();
91 ret_pc->as<PCState>().advance();
92 return std::unique_ptr<PCStateBase>{ret_pc};
93 }
94
95 size_t
96 asBytes(void *buf, size_t max_size) override
97 {
98 return simpleAsBytes(buf, max_size, machInst);
99 }
100};
101
102} // namespace PowerISA
103} // namespace gem5
104
105#endif //__ARCH_POWER_INSTS_STATICINST_HH__
Target & as()
Definition pcstate.hh:73
virtual PCStateBase * clone() const =0
void printReg(std::ostream &os, RegId reg) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
void advancePC(ThreadContext *tc) const override
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
uint32_t insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
void advancePC(PCStateBase &pc_state) const override
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
size_t asBytes(void *buf, size_t max_size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
Base, ISA-independent static instruction class.
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual const PCStateBase & pcState() const =0
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
Bitfield< 4 > pc
Bitfield< 25, 23 > bf
Definition types.hh:74
Bitfield< 5, 3 > reg
Definition types.hh:92
Bitfield< 17 > os
Definition misc.hh:838
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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