gem5  v21.1.0.2
static_inst.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_STATICINST_HH__
30 #define __ARCH_POWER_INSTS_STATICINST_HH__
31 
32 #include "arch/power/types.hh"
33 #include "base/trace.hh"
34 #include "cpu/static_inst.hh"
35 
36 namespace gem5
37 {
38 
39 namespace PowerISA
40 {
41 
43 {
44  protected:
46 
47  // Constructor
48  PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
49  : StaticInst(mnem, __opClass), machInst(_machInst)
50  {
51  }
52 
53  // Insert a condition value into a CR (condition register) field
54  inline uint32_t
55  insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
56  {
57  uint32_t bits = value << ((7 - bf) * 4);
58  uint32_t mask = ~(0xf << ((7 - bf) * 4));
59  return (cr & mask) | bits;
60  }
61 
64  void
65  printReg(std::ostream &os, RegId reg) const;
66 
67  std::string generateDisassembly(
68  Addr pc, const loader::SymbolTable *symtab) const override;
69 
70  void
71  advancePC(PowerISA::PCState &pcState) const override
72  {
73  pcState.advance();
74  }
75 
76  PCState
77  buildRetPC(const PCState &curPC, const PCState &callPC) const override
78  {
79  PCState retPC = callPC;
80  retPC.advance();
81  return retPC;
82  }
83 
84  size_t
85  asBytes(void *buf, size_t max_size) override
86  {
87  return simpleAsBytes(buf, max_size, machInst);
88  }
89 };
90 
91 } // namespace PowerISA
92 } // namespace gem5
93 
94 #endif //__ARCH_POWER_INSTS_STATICINST_HH__
gem5::PowerISA::PowerStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:45
gem5::PowerISA::bf
Bitfield< 25, 23 > bf
Definition: types.hh:74
gem5::PowerISA::PowerStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:65
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:383
gem5::PowerISA::PowerStaticInst::printReg
void printReg(std::ostream &os, RegId reg) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:40
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::PowerStaticInst::advancePC
void advancePC(PowerISA::PCState &pcState) const override
Definition: static_inst.hh:71
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::PowerISA::PowerStaticInst::PowerStaticInst
PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:48
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::PowerISA::PowerStaticInst::insertCRField
uint32_t insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
Definition: static_inst.hh:55
gem5::PowerISA::PowerStaticInst::asBytes
size_t asBytes(void *buf, size_t max_size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:85
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:181
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::PowerISA::PowerStaticInst::buildRetPC
PCState buildRetPC(const PCState &curPC, const PCState &callPC) const override
Definition: static_inst.hh:77
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
trace.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerISA::PowerStaticInst
Definition: static_inst.hh:42
types.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88

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