gem5  v22.0.0.2
static_inst.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_STATICINST_HH__
30 #define __ARCH_POWER_INSTS_STATICINST_HH__
31 
32 #include "arch/power/pcstate.hh"
33 #include "arch/power/types.hh"
34 #include "base/trace.hh"
35 #include "cpu/static_inst.hh"
36 #include "cpu/thread_context.hh"
37 
38 namespace gem5
39 {
40 
41 namespace PowerISA
42 {
43 
45 {
46  protected:
48 
49  // Constructor
50  PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
51  : StaticInst(mnem, __opClass), machInst(_machInst)
52  {
53  }
54 
55  // Insert a condition value into a CR (condition register) field
56  inline uint32_t
57  insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
58  {
59  uint32_t bits = value << ((7 - bf) * 4);
60  uint32_t mask = ~(0xf << ((7 - bf) * 4));
61  return (cr & mask) | bits;
62  }
63 
66  void
67  printReg(std::ostream &os, RegId reg) const;
68 
69  std::string generateDisassembly(
70  Addr pc, const loader::SymbolTable *symtab) const override;
71 
72  void
73  advancePC(PCStateBase &pc_state) const override
74  {
75  pc_state.as<PCState>().advance();
76  }
77 
78  void
79  advancePC(ThreadContext *tc) const override
80  {
81  PCState pc = tc->pcState().as<PCState>();
82  pc.advance();
83  tc->pcState(pc);
84  }
85 
86  std::unique_ptr<PCStateBase>
87  buildRetPC(const PCStateBase &cur_pc,
88  const PCStateBase &call_pc) const override
89  {
90  PCStateBase *ret_pc = call_pc.clone();
91  ret_pc->as<PCState>().advance();
92  return std::unique_ptr<PCStateBase>{ret_pc};
93  }
94 
95  size_t
96  asBytes(void *buf, size_t max_size) override
97  {
98  return simpleAsBytes(buf, max_size, machInst);
99  }
100 };
101 
102 } // namespace PowerISA
103 } // namespace gem5
104 
105 #endif //__ARCH_POWER_INSTS_STATICINST_HH__
gem5::PowerISA::PowerStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:47
gem5::PowerISA::PowerStaticInst::buildRetPC
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
Definition: static_inst.hh:87
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::PowerISA::bf
Bitfield< 25, 23 > bf
Definition: types.hh:74
gem5::PowerISA::PowerStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:65
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:356
gem5::PowerISA::PowerStaticInst::printReg
void printReg(std::ostream &os, RegId reg) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:40
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::PowerISA::PowerStaticInst::PowerStaticInst
PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:50
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::PowerISA::PowerStaticInst::advancePC
void advancePC(ThreadContext *tc) const override
Definition: static_inst.hh:79
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
pcstate.hh
gem5::PowerISA::PowerStaticInst::insertCRField
uint32_t insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const
Definition: static_inst.hh:57
gem5::X86ISA::misc_reg::cr
static RegIndex cr(int index)
Definition: misc.hh:419
gem5::PowerISA::PowerStaticInst::asBytes
size_t asBytes(void *buf, size_t max_size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:96
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::PowerStaticInst::advancePC
void advancePC(PCStateBase &pc_state) const override
Definition: static_inst.hh:73
trace.hh
gem5::PCStateBase
Definition: pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
thread_context.hh
gem5::PowerISA::PowerStaticInst
Definition: static_inst.hh:44
types.hh
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126

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