gem5  v22.1.0.0
reg_abi.cc
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27 
28 #include "arch/arm/reg_abi.hh"
29 #include "arch/arm/regs/int.hh"
30 
31 namespace gem5
32 {
33 
34 namespace ArmISA
35 {
36 
40 };
44 };
45 
46 } // namespace ArmISA
47 } // namespace gem5
STL vector class.
Definition: stl.hh:37
constexpr RegId X0
Definition: int.hh:240
constexpr RegId R4
Definition: int.hh:190
constexpr RegId X6
Definition: int.hh:246
constexpr RegId R6
Definition: int.hh:192
constexpr RegId X1
Definition: int.hh:241
constexpr RegId X3
Definition: int.hh:243
constexpr RegId X4
Definition: int.hh:244
constexpr RegId R3
Definition: int.hh:189
constexpr RegId R5
Definition: int.hh:191
constexpr RegId X2
Definition: int.hh:242
constexpr RegId R2
Definition: int.hh:188
constexpr RegId R1
Definition: int.hh:187
constexpr RegId X5
Definition: int.hh:245
constexpr RegId R0
Definition: int.hh:186
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
static const std::vector< RegId > ArgumentRegs
Definition: reg_abi.hh:44
static const std::vector< RegId > ArgumentRegs
Definition: reg_abi.hh:49

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