gem5  v21.2.1.1
int.hh
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40 
41 #include <cassert>
42 
43 #ifndef __ARCH_ARM_REGS_INT_HH__
44 #define __ARCH_ARM_REGS_INT_HH__
45 
46 #include "arch/arm/types.hh"
47 #include "base/logging.hh"
48 #include "sim/core.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ArmISA
54 {
55 
56 BitUnion32(PackedIntReg)
57  Bitfield<31, 16> uh1;
58  Bitfield<15, 0> uh0;
59  SignedBitfield<31, 16> sh1;
60  SignedBitfield<15, 0> sh0;
61  Bitfield<31, 0> uw;
62  SignedBitfield<31, 0> sw;
63 EndBitUnion(PackedIntReg)
64 
65 enum IntRegIndex
66 {
67  /* All the unique register indices. */
68  INTREG_R0,
69  INTREG_R1,
70  INTREG_R2,
71  INTREG_R3,
72  INTREG_R4,
73  INTREG_R5,
74  INTREG_R6,
75  INTREG_R7,
76  INTREG_R8,
77  INTREG_R9,
78  INTREG_R10,
79  INTREG_R11,
80  INTREG_R12,
81  INTREG_R13,
82  INTREG_SP = INTREG_R13,
83  INTREG_R14,
84  INTREG_LR = INTREG_R14,
85  INTREG_R15,
86  INTREG_PC = INTREG_R15,
87 
88  INTREG_R13_SVC,
89  INTREG_SP_SVC = INTREG_R13_SVC,
90  INTREG_R14_SVC,
91  INTREG_LR_SVC = INTREG_R14_SVC,
92 
93  INTREG_R13_MON,
94  INTREG_SP_MON = INTREG_R13_MON,
95  INTREG_R14_MON,
96  INTREG_LR_MON = INTREG_R14_MON,
97 
98  INTREG_R13_HYP,
99  INTREG_SP_HYP = INTREG_R13_HYP,
100 
101  INTREG_R13_ABT,
102  INTREG_SP_ABT = INTREG_R13_ABT,
103  INTREG_R14_ABT,
104  INTREG_LR_ABT = INTREG_R14_ABT,
105 
106  INTREG_R13_UND,
107  INTREG_SP_UND = INTREG_R13_UND,
108  INTREG_R14_UND,
109  INTREG_LR_UND = INTREG_R14_UND,
110 
111  INTREG_R13_IRQ,
112  INTREG_SP_IRQ = INTREG_R13_IRQ,
113  INTREG_R14_IRQ,
114  INTREG_LR_IRQ = INTREG_R14_IRQ,
115 
116  INTREG_R8_FIQ,
117  INTREG_R9_FIQ,
118  INTREG_R10_FIQ,
119  INTREG_R11_FIQ,
120  INTREG_R12_FIQ,
121  INTREG_R13_FIQ,
122  INTREG_SP_FIQ = INTREG_R13_FIQ,
123  INTREG_R14_FIQ,
124  INTREG_LR_FIQ = INTREG_R14_FIQ,
125 
126  INTREG_ZERO,
127  INTREG_UREG0,
128  INTREG_UREG1,
129  INTREG_UREG2,
130 
131  INTREG_SP0,
132  INTREG_SP1,
133  INTREG_SP2,
134  INTREG_SP3,
135 
136  NUM_INTREGS,
137  NUM_ARCH_INTREGS = 32,
138 
139  /* AArch64 registers */
140  INTREG_X0 = 0,
141  INTREG_X1,
142  INTREG_X2,
143  INTREG_X3,
144  INTREG_X4,
145  INTREG_X5,
146  INTREG_X6,
147  INTREG_X7,
148  INTREG_X8,
149  INTREG_X9,
150  INTREG_X10,
151  INTREG_X11,
152  INTREG_X12,
153  INTREG_X13,
154  INTREG_X14,
155  INTREG_X15,
156  INTREG_X16,
157  INTREG_X17,
158  INTREG_X18,
159  INTREG_X19,
160  INTREG_X20,
161  INTREG_X21,
162  INTREG_X22,
163  INTREG_X23,
164  INTREG_X24,
165  INTREG_X25,
166  INTREG_X26,
167  INTREG_X27,
168  INTREG_X28,
169  INTREG_X29,
170  INTREG_X30,
171  INTREG_X31,
172 
173  INTREG_SPX = NUM_INTREGS,
174 
175  /* All the aliased indexes. */
176 
177  /* USR mode */
178  INTREG_R0_USR = INTREG_R0,
179  INTREG_R1_USR = INTREG_R1,
180  INTREG_R2_USR = INTREG_R2,
181  INTREG_R3_USR = INTREG_R3,
182  INTREG_R4_USR = INTREG_R4,
183  INTREG_R5_USR = INTREG_R5,
184  INTREG_R6_USR = INTREG_R6,
185  INTREG_R7_USR = INTREG_R7,
186  INTREG_R8_USR = INTREG_R8,
187  INTREG_R9_USR = INTREG_R9,
188  INTREG_R10_USR = INTREG_R10,
189  INTREG_R11_USR = INTREG_R11,
190  INTREG_R12_USR = INTREG_R12,
191  INTREG_R13_USR = INTREG_R13,
192  INTREG_SP_USR = INTREG_SP,
193  INTREG_R14_USR = INTREG_R14,
194  INTREG_LR_USR = INTREG_LR,
195  INTREG_R15_USR = INTREG_R15,
196  INTREG_PC_USR = INTREG_PC,
197 
198  /* SVC mode */
199  INTREG_R0_SVC = INTREG_R0,
200  INTREG_R1_SVC = INTREG_R1,
201  INTREG_R2_SVC = INTREG_R2,
202  INTREG_R3_SVC = INTREG_R3,
203  INTREG_R4_SVC = INTREG_R4,
204  INTREG_R5_SVC = INTREG_R5,
205  INTREG_R6_SVC = INTREG_R6,
206  INTREG_R7_SVC = INTREG_R7,
207  INTREG_R8_SVC = INTREG_R8,
208  INTREG_R9_SVC = INTREG_R9,
209  INTREG_R10_SVC = INTREG_R10,
210  INTREG_R11_SVC = INTREG_R11,
211  INTREG_R12_SVC = INTREG_R12,
212  INTREG_PC_SVC = INTREG_PC,
213  INTREG_R15_SVC = INTREG_R15,
214 
215  /* MON mode */
216  INTREG_R0_MON = INTREG_R0,
217  INTREG_R1_MON = INTREG_R1,
218  INTREG_R2_MON = INTREG_R2,
219  INTREG_R3_MON = INTREG_R3,
220  INTREG_R4_MON = INTREG_R4,
221  INTREG_R5_MON = INTREG_R5,
222  INTREG_R6_MON = INTREG_R6,
223  INTREG_R7_MON = INTREG_R7,
224  INTREG_R8_MON = INTREG_R8,
225  INTREG_R9_MON = INTREG_R9,
226  INTREG_R10_MON = INTREG_R10,
227  INTREG_R11_MON = INTREG_R11,
228  INTREG_R12_MON = INTREG_R12,
229  INTREG_PC_MON = INTREG_PC,
230  INTREG_R15_MON = INTREG_R15,
231 
232  /* ABT mode */
233  INTREG_R0_ABT = INTREG_R0,
234  INTREG_R1_ABT = INTREG_R1,
235  INTREG_R2_ABT = INTREG_R2,
236  INTREG_R3_ABT = INTREG_R3,
237  INTREG_R4_ABT = INTREG_R4,
238  INTREG_R5_ABT = INTREG_R5,
239  INTREG_R6_ABT = INTREG_R6,
240  INTREG_R7_ABT = INTREG_R7,
241  INTREG_R8_ABT = INTREG_R8,
242  INTREG_R9_ABT = INTREG_R9,
243  INTREG_R10_ABT = INTREG_R10,
244  INTREG_R11_ABT = INTREG_R11,
245  INTREG_R12_ABT = INTREG_R12,
246  INTREG_PC_ABT = INTREG_PC,
247  INTREG_R15_ABT = INTREG_R15,
248 
249  /* HYP mode */
250  INTREG_R0_HYP = INTREG_R0,
251  INTREG_R1_HYP = INTREG_R1,
252  INTREG_R2_HYP = INTREG_R2,
253  INTREG_R3_HYP = INTREG_R3,
254  INTREG_R4_HYP = INTREG_R4,
255  INTREG_R5_HYP = INTREG_R5,
256  INTREG_R6_HYP = INTREG_R6,
257  INTREG_R7_HYP = INTREG_R7,
258  INTREG_R8_HYP = INTREG_R8,
259  INTREG_R9_HYP = INTREG_R9,
260  INTREG_R10_HYP = INTREG_R10,
261  INTREG_R11_HYP = INTREG_R11,
262  INTREG_R12_HYP = INTREG_R12,
263  INTREG_LR_HYP = INTREG_LR,
264  INTREG_R14_HYP = INTREG_R14,
265  INTREG_PC_HYP = INTREG_PC,
266  INTREG_R15_HYP = INTREG_R15,
267 
268  /* UND mode */
269  INTREG_R0_UND = INTREG_R0,
270  INTREG_R1_UND = INTREG_R1,
271  INTREG_R2_UND = INTREG_R2,
272  INTREG_R3_UND = INTREG_R3,
273  INTREG_R4_UND = INTREG_R4,
274  INTREG_R5_UND = INTREG_R5,
275  INTREG_R6_UND = INTREG_R6,
276  INTREG_R7_UND = INTREG_R7,
277  INTREG_R8_UND = INTREG_R8,
278  INTREG_R9_UND = INTREG_R9,
279  INTREG_R10_UND = INTREG_R10,
280  INTREG_R11_UND = INTREG_R11,
281  INTREG_R12_UND = INTREG_R12,
282  INTREG_PC_UND = INTREG_PC,
283  INTREG_R15_UND = INTREG_R15,
284 
285  /* IRQ mode */
286  INTREG_R0_IRQ = INTREG_R0,
287  INTREG_R1_IRQ = INTREG_R1,
288  INTREG_R2_IRQ = INTREG_R2,
289  INTREG_R3_IRQ = INTREG_R3,
290  INTREG_R4_IRQ = INTREG_R4,
291  INTREG_R5_IRQ = INTREG_R5,
292  INTREG_R6_IRQ = INTREG_R6,
293  INTREG_R7_IRQ = INTREG_R7,
294  INTREG_R8_IRQ = INTREG_R8,
295  INTREG_R9_IRQ = INTREG_R9,
296  INTREG_R10_IRQ = INTREG_R10,
297  INTREG_R11_IRQ = INTREG_R11,
298  INTREG_R12_IRQ = INTREG_R12,
299  INTREG_PC_IRQ = INTREG_PC,
300  INTREG_R15_IRQ = INTREG_R15,
301 
302  /* FIQ mode */
303  INTREG_R0_FIQ = INTREG_R0,
304  INTREG_R1_FIQ = INTREG_R1,
305  INTREG_R2_FIQ = INTREG_R2,
306  INTREG_R3_FIQ = INTREG_R3,
307  INTREG_R4_FIQ = INTREG_R4,
308  INTREG_R5_FIQ = INTREG_R5,
309  INTREG_R6_FIQ = INTREG_R6,
310  INTREG_R7_FIQ = INTREG_R7,
311  INTREG_PC_FIQ = INTREG_PC,
312  INTREG_R15_FIQ = INTREG_R15
313 };
314 
315 typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
316 
318  INTREG_R0, INTREG_R1, INTREG_R2, INTREG_R3,
319  INTREG_R4, INTREG_R5, INTREG_R6, INTREG_R7,
320  INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
321  INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
322  INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
323  INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
324  INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
325  INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
326 };
327 
329  INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
330  INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
331  INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
332  INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
333  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
334  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
335  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
336  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
337 };
338 
339 static inline IntRegIndex
340 INTREG_USR(unsigned index)
341 {
342  assert(index < NUM_ARCH_INTREGS);
343  return IntRegUsrMap[index];
344 }
345 
347  INTREG_R0_HYP, INTREG_R1_HYP, INTREG_R2_HYP, INTREG_R3_HYP,
348  INTREG_R4_HYP, INTREG_R5_HYP, INTREG_R6_HYP, INTREG_R7_HYP,
349  INTREG_R8_HYP, INTREG_R9_HYP, INTREG_R10_HYP, INTREG_R11_HYP,
350  INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
351  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
352  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
353  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
354  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
355 };
356 
357 static inline IntRegIndex
358 INTREG_HYP(unsigned index)
359 {
360  assert(index < NUM_ARCH_INTREGS);
361  return IntRegHypMap[index];
362 }
363 
365  INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
366  INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
367  INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
368  INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
369  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
370  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
371  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
372  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
373 };
374 
375 static inline IntRegIndex
376 INTREG_SVC(unsigned index)
377 {
378  assert(index < NUM_ARCH_INTREGS);
379  return IntRegSvcMap[index];
380 }
381 
383  INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
384  INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
385  INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
386  INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
387  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
388  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
389  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
390  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
391 };
392 
393 static inline IntRegIndex
394 INTREG_MON(unsigned index)
395 {
396  assert(index < NUM_ARCH_INTREGS);
397  return IntRegMonMap[index];
398 }
399 
401  INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
402  INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
403  INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
404  INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
405  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
406  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
407  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
408  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
409 };
410 
411 static inline IntRegIndex
412 INTREG_ABT(unsigned index)
413 {
414  assert(index < NUM_ARCH_INTREGS);
415  return IntRegAbtMap[index];
416 }
417 
419  INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
420  INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
421  INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
422  INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
423  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
424  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
425  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
426  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
427 };
428 
429 static inline IntRegIndex
430 INTREG_UND(unsigned index)
431 {
432  assert(index < NUM_ARCH_INTREGS);
433  return IntRegUndMap[index];
434 }
435 
437  INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
438  INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
439  INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
440  INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
441  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
442  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
443  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
444  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
445 };
446 
447 static inline IntRegIndex
448 INTREG_IRQ(unsigned index)
449 {
450  assert(index < NUM_ARCH_INTREGS);
451  return IntRegIrqMap[index];
452 }
453 
455  INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
456  INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
457  INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
458  INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
459  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
460  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
461  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
462  INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
463 };
464 
465 static inline IntRegIndex
466 INTREG_FIQ(unsigned index)
467 {
468  assert(index < NUM_ARCH_INTREGS);
469  return IntRegFiqMap[index];
470 }
471 
472 static const unsigned intRegsPerMode = NUM_INTREGS;
473 
474 static inline int
476 {
477  assert(reg < NUM_ARCH_INTREGS);
478  return mode * intRegsPerMode + reg;
479 }
480 
481 static inline int
483 {
484  int mode = reg / intRegsPerMode;
485  reg = reg % intRegsPerMode;
486  switch (mode) {
487  case MODE_USER:
488  case MODE_SYSTEM:
489  return INTREG_USR(reg);
490  case MODE_FIQ:
491  return INTREG_FIQ(reg);
492  case MODE_IRQ:
493  return INTREG_IRQ(reg);
494  case MODE_SVC:
495  return INTREG_SVC(reg);
496  case MODE_MON:
497  return INTREG_MON(reg);
498  case MODE_ABORT:
499  return INTREG_ABT(reg);
500  case MODE_HYP:
501  return INTREG_HYP(reg);
502  case MODE_UNDEFINED:
503  return INTREG_UND(reg);
504  default:
505  panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
506  curTick(), reg, mode);
507  }
508 }
509 
510 
511 static inline IntRegIndex
512 makeSP(IntRegIndex reg)
513 {
514  if (reg == INTREG_X31)
515  reg = INTREG_SPX;
516  return reg;
517 }
518 
519 static inline IntRegIndex
520 makeZero(IntRegIndex reg)
521 {
522  if (reg == INTREG_X31)
523  reg = INTREG_ZERO;
524  return reg;
525 }
526 
527 static inline bool
528 isSP(IntRegIndex reg)
529 {
530  return reg == INTREG_SPX;
531 }
532 
533 // Semantically meaningful register indices
534 const int ReturnValueReg = 0;
535 const int ReturnValueReg1 = 1;
536 const int ReturnValueReg2 = 2;
537 const int NumArgumentRegs = 4;
538 const int NumArgumentRegs64 = 8;
539 const int ArgumentReg0 = 0;
540 const int ArgumentReg1 = 1;
541 const int ArgumentReg2 = 2;
542 const int ArgumentReg3 = 3;
543 const int FramePointerReg = 11;
544 const int StackPointerReg = INTREG_SP;
546 const int PCReg = INTREG_PC;
547 
551 
552 } // namespace ArmISA
553 } // namespace gem5
554 
555 #endif
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::ArmISA::ArgumentReg3
const int ArgumentReg3
Definition: int.hh:542
gem5::ArmISA::FramePointerReg
const int FramePointerReg
Definition: int.hh:543
gem5::ArmISA::intRegInMode
static int intRegInMode(OperatingMode mode, int reg)
Definition: int.hh:475
gem5::ArmISA::INTREG_FIQ
static IntRegIndex INTREG_FIQ(unsigned index)
Definition: int.hh:466
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:284
gem5::ArmISA::INTREG_MON
static IntRegIndex INTREG_MON(unsigned index)
Definition: int.hh:394
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:285
gem5::ArmISA::NumArgumentRegs64
const int NumArgumentRegs64
Definition: int.hh:538
gem5::ArmISA::isSP
static bool isSP(IntRegIndex reg)
Definition: int.hh:528
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:282
gem5::ArmISA::ArgumentReg0
const int ArgumentReg0
Definition: int.hh:539
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::INTREG_SVC
static IntRegIndex INTREG_SVC(unsigned index)
Definition: int.hh:376
gem5::ArmISA::IntRegMap
IntRegIndex IntRegMap[NUM_ARCH_INTREGS]
Definition: int.hh:313
gem5::ArmISA::INTREG_UND
static IntRegIndex INTREG_UND(unsigned index)
Definition: int.hh:430
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:288
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:283
gem5::ArmISA::INTREG_USR
static IntRegIndex INTREG_USR(unsigned index)
Definition: int.hh:340
gem5::ArmISA::INTREG_HYP
static IntRegIndex INTREG_HYP(unsigned index)
Definition: int.hh:358
gem5::ArmISA::IntRegFiqMap
const IntRegMap IntRegFiqMap
Definition: int.hh:454
gem5::ArmISA::ReturnAddressReg
const int ReturnAddressReg
Definition: int.hh:545
gem5::ArmISA::IntRegUsrMap
const IntRegMap IntRegUsrMap
Definition: int.hh:328
gem5::ArmISA::NumArgumentRegs
const int NumArgumentRegs
Definition: int.hh:537
gem5::ArmISA::ReturnValueReg1
const int ReturnValueReg1
Definition: int.hh:535
types.hh
gem5::ArmISA::ArgumentReg2
const int ArgumentReg2
Definition: int.hh:541
gem5::ArmISA::uw
Bitfield< 31, 0 > uw
Definition: int.hh:61
gem5::ArmISA::IntReg64Map
const IntRegMap IntReg64Map
Definition: int.hh:317
gem5::SparcISA::INTREG_UREG0
@ INTREG_UREG0
Definition: int.hh:57
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:287
gem5::ArmISA::BitUnion32
BitUnion32(PackedIntReg) Bitfield< 31
gem5::ArmISA::IntRegSvcMap
const IntRegMap IntRegSvcMap
Definition: int.hh:364
gem5::ArmISA::makeZero
static IntRegIndex makeZero(IntRegIndex reg)
Definition: int.hh:520
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::sw
SignedBitfield< 31, 0 > sw
Definition: int.hh:62
gem5::ArmISA::SyscallSuccessReg
const int SyscallSuccessReg
Definition: int.hh:550
gem5::ArmISA::IntRegUndMap
const IntRegMap IntRegUndMap
Definition: int.hh:418
gem5::PowerISA::INTREG_LR
@ INTREG_LR
Definition: int.hh:64
gem5::ArmISA::SyscallPseudoReturnReg
const int SyscallPseudoReturnReg
Definition: int.hh:549
gem5::ArmISA::IntRegAbtMap
const IntRegMap IntRegAbtMap
Definition: int.hh:400
gem5::ArmISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:544
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::makeSP
static IntRegIndex makeSP(IntRegIndex reg)
Definition: int.hh:512
gem5::ArmISA::uh1
uh1
Definition: int.hh:57
gem5::ArmISA::INTREG_IRQ
static IntRegIndex INTREG_IRQ(unsigned index)
Definition: int.hh:448
gem5::ArmISA::EndBitUnion
EndBitUnion(PackedIntReg) enum IntRegIndex
Definition: int.hh:63
gem5::ArmISA::IntRegIrqMap
const IntRegMap IntRegIrqMap
Definition: int.hh:436
gem5::ArmISA::INTREG_ABT
static IntRegIndex INTREG_ABT(unsigned index)
Definition: int.hh:412
core.hh
gem5::ArmISA::ReturnValueReg2
const int ReturnValueReg2
Definition: int.hh:536
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:289
gem5::ArmISA::intRegsPerMode
static const unsigned intRegsPerMode
Definition: int.hh:472
gem5::ArmISA::flattenIntRegModeIndex
static int flattenIntRegModeIndex(int reg)
Definition: int.hh:482
logging.hh
gem5::ArmISA::ArgumentReg1
const int ArgumentReg1
Definition: int.hh:540
gem5::ArmISA::IntRegHypMap
const IntRegMap IntRegHypMap
Definition: int.hh:346
gem5::ArmISA::uh0
Bitfield< 15, 0 > uh0
Definition: int.hh:58
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:286
gem5::ArmISA::SyscallNumReg
const int SyscallNumReg
Definition: int.hh:548
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::sh1
SignedBitfield< 31, 16 > sh1
Definition: int.hh:59
gem5::ArmISA::ReturnValueReg
const int ReturnValueReg
Definition: int.hh:534
gem5::ArmISA::IntRegMonMap
const IntRegMap IntRegMonMap
Definition: int.hh:382
gem5::ArmISA::PCReg
const int PCReg
Definition: int.hh:546
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::sh0
SignedBitfield< 15, 0 > sh0
Definition: int.hh:60

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