gem5  v22.0.0.2
int.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010-2014 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2009 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include <cassert>
42 
43 #ifndef __ARCH_ARM_REGS_INT_HH__
44 #define __ARCH_ARM_REGS_INT_HH__
45 
46 #include "arch/arm/types.hh"
47 #include "base/logging.hh"
48 #include "cpu/reg_class.hh"
49 #include "sim/core.hh"
50 
51 namespace gem5
52 {
53 
54 namespace ArmISA
55 {
56 
57 BitUnion32(PackedIntReg)
58  Bitfield<31, 16> uh1;
59  Bitfield<15, 0> uh0;
60  SignedBitfield<31, 16> sh1;
61  SignedBitfield<15, 0> sh0;
62  Bitfield<31, 0> uw;
63  SignedBitfield<31, 0> sw;
64 EndBitUnion(PackedIntReg)
65 
66 namespace int_reg
67 {
68 
69 enum : RegIndex
70 {
71  /* All the unique register indices. */
72  _R0Idx,
73  _R1Idx,
74  _R2Idx,
75  _R3Idx,
76  _R4Idx,
77  _R5Idx,
78  _R6Idx,
79  _R7Idx,
80  _R8Idx,
81  _R9Idx,
82  _R10Idx,
83  _R11Idx,
84  _R12Idx,
85  _R13Idx,
86  _R14Idx,
87  _R15Idx,
88 
89  _R13SvcIdx,
90  _R14SvcIdx,
91 
92  _R13MonIdx,
93  _R14MonIdx,
94 
95  _R13HypIdx,
96 
97  _R13AbtIdx,
98  _R14AbtIdx,
99 
100  _R13UndIdx,
101  _R14UndIdx,
102 
103  _R13IrqIdx,
104  _R14IrqIdx,
105 
106  _R8FiqIdx,
107  _R9FiqIdx,
108  _R10FiqIdx,
109  _R11FiqIdx,
110  _R12FiqIdx,
111  _R13FiqIdx,
112  _R14FiqIdx,
113 
114  _ZeroIdx,
115  _Ureg0Idx,
116  _Ureg1Idx,
117  _Ureg2Idx,
118 
119  _Sp0Idx,
120  _Sp1Idx,
121  _Sp2Idx,
122  _Sp3Idx,
123 
124  NumRegs,
125  _SpxIdx = NumRegs,
126 
127  NumArchRegs = 32,
128 
129  _X0Idx = 0,
130  _X1Idx,
131  _X2Idx,
132  _X3Idx,
133  _X4Idx,
134  _X5Idx,
135  _X6Idx,
136  _X7Idx,
137  _X8Idx,
138  _X9Idx,
139  _X10Idx,
140  _X11Idx,
141  _X12Idx,
142  _X13Idx,
143  _X14Idx,
144  _X15Idx,
145  _X16Idx,
146  _X17Idx,
147  _X18Idx,
148  _X19Idx,
149  _X20Idx,
150  _X21Idx,
151  _X22Idx,
152  _X23Idx,
153  _X24Idx,
154  _X25Idx,
155  _X26Idx,
156  _X27Idx,
157  _X28Idx,
158  _X29Idx,
159  _X30Idx,
160  _X31Idx
161 };
162 
163 inline constexpr RegId
164  /* All the unique register indices. */
181 
182  R13Svc(IntRegClass, _R13SvcIdx),
183  R14Svc(IntRegClass, _R14SvcIdx),
184 
185  R13Mon(IntRegClass, _R13MonIdx),
186  R14Mon(IntRegClass, _R14MonIdx),
187 
188  R13Hyp(IntRegClass, _R13HypIdx),
189 
190  R13Abt(IntRegClass, _R13AbtIdx),
191  R14Abt(IntRegClass, _R14AbtIdx),
192 
193  R13Und(IntRegClass, _R13UndIdx),
194  R14Und(IntRegClass, _R14UndIdx),
195 
196  R13Irq(IntRegClass, _R13IrqIdx),
197  R14Irq(IntRegClass, _R14IrqIdx),
198 
199  R8Fiq(IntRegClass, _R8FiqIdx),
200  R9Fiq(IntRegClass, _R9FiqIdx),
201  R10Fiq(IntRegClass, _R10FiqIdx),
202  R11Fiq(IntRegClass, _R11FiqIdx),
203  R12Fiq(IntRegClass, _R12FiqIdx),
204  R13Fiq(IntRegClass, _R13FiqIdx),
205  R14Fiq(IntRegClass, _R14FiqIdx),
206 
208  Ureg0(IntRegClass, _Ureg0Idx),
209  Ureg1(IntRegClass, _Ureg1Idx),
210  Ureg2(IntRegClass, _Ureg2Idx),
211 
212  Sp0(IntRegClass, _Sp0Idx),
213  Sp1(IntRegClass, _Sp1Idx),
214  Sp2(IntRegClass, _Sp2Idx),
215  Sp3(IntRegClass, _Sp3Idx),
216 
217  Spx(IntRegClass, _SpxIdx),
218 
219  X0(IntRegClass, _X0Idx),
220  X1(IntRegClass, _X1Idx),
221  X2(IntRegClass, _X2Idx),
222  X3(IntRegClass, _X3Idx),
223  X4(IntRegClass, _X4Idx),
224  X5(IntRegClass, _X5Idx),
225  X6(IntRegClass, _X6Idx),
226  X7(IntRegClass, _X7Idx),
227  X8(IntRegClass, _X8Idx),
228  X9(IntRegClass, _X9Idx),
229  X10(IntRegClass, _X10Idx),
230  X11(IntRegClass, _X11Idx),
231  X12(IntRegClass, _X12Idx),
232  X13(IntRegClass, _X13Idx),
233  X14(IntRegClass, _X14Idx),
234  X15(IntRegClass, _X15Idx),
235  X16(IntRegClass, _X16Idx),
236  X17(IntRegClass, _X17Idx),
237  X18(IntRegClass, _X18Idx),
238  X19(IntRegClass, _X19Idx),
239  X20(IntRegClass, _X20Idx),
240  X21(IntRegClass, _X21Idx),
241  X22(IntRegClass, _X22Idx),
242  X23(IntRegClass, _X23Idx),
243  X24(IntRegClass, _X24Idx),
244  X25(IntRegClass, _X25Idx),
245  X26(IntRegClass, _X26Idx),
246  X27(IntRegClass, _X27Idx),
247  X28(IntRegClass, _X28Idx),
248  X29(IntRegClass, _X29Idx),
249  X30(IntRegClass, _X30Idx),
250  X31(IntRegClass, _X31Idx);
251 
252 inline constexpr auto
253  &Sp = R13,
254  &Lr = R14,
255  &Pc = R15,
256 
257  &SpSvc = R13Svc,
258  &LRSvc = R14Svc,
259 
260  &SPMon = R13Mon,
261  &LRMon = R14Mon,
262 
263  &SPHyp = R13Hyp,
264 
265  &SPAbt = R13Abt,
266  &LRAbt = R14Abt,
267 
268  &SPUnd = R13Und,
269  &LRUnd = R14Und,
270 
271  &SPIrq = R13Irq,
272  &LRIrq = R14Irq,
273 
274  &SPFiq = R13Fiq,
275  &LRFiq = R14Fiq,
276 
277  /* USR mode */
278  &R0Usr = R0,
279  &R1Usr = R1,
280  &R2Usr = R2,
281  &R3Usr = R3,
282  &R4Usr = R4,
283  &R5Usr = R5,
284  &R6Usr = R6,
285  &R7Usr = R7,
286  &R8Usr = R8,
287  &R9Usr = R9,
288  &R10Usr = R10,
289  &R11Usr = R11,
290  &R12Usr = R12,
291  &R13Usr = R13,
292  &SPUsr = Sp,
293  &R14Usr = R14,
294  &LRUsr = Lr,
295  &R15Usr = R15,
296  &PcUsr = Pc,
297 
298  /* SVC mode */
299  &R0Svc = R0,
300  &R1Svc = R1,
301  &R2Svc = R2,
302  &R3Svc = R3,
303  &R4Svc = R4,
304  &R5Svc = R5,
305  &R6Svc = R6,
306  &R7Svc = R7,
307  &R8Svc = R8,
308  &R9Svc = R9,
309  &R10Svc = R10,
310  &R11Svc = R11,
311  &R12Svc = R12,
312  &PcSvc = Pc,
313  &R15Svc = R15,
314 
315  /* MON mode */
316  &R0Mon = R0,
317  &R1Mon = R1,
318  &R2Mon = R2,
319  &R3Mon = R3,
320  &R4Mon = R4,
321  &R5Mon = R5,
322  &R6Mon = R6,
323  &R7Mon = R7,
324  &R8Mon = R8,
325  &R9Mon = R9,
326  &R10Mon = R10,
327  &R11Mon = R11,
328  &R12Mon = R12,
329  &PcMon = Pc,
330  &R15Mon = R15,
331 
332  /* ABT mode */
333  &R0Abt = R0,
334  &R1Abt = R1,
335  &R2Abt = R2,
336  &R3Abt = R3,
337  &R4Abt = R4,
338  &R5Abt = R5,
339  &R6Abt = R6,
340  &R7Abt = R7,
341  &R8Abt = R8,
342  &R9Abt = R9,
343  &R10Abt = R10,
344  &R11Abt = R11,
345  &R12Abt = R12,
346  &PcAbt = Pc,
347  &R15Abt = R15,
348 
349  /* HYP mode */
350  &R0Hyp = R0,
351  &R1Hyp = R1,
352  &R2Hyp = R2,
353  &R3Hyp = R3,
354  &R4Hyp = R4,
355  &R5Hyp = R5,
356  &R6Hyp = R6,
357  &R7Hyp = R7,
358  &R8Hyp = R8,
359  &R9Hyp = R9,
360  &R10Hyp = R10,
361  &R11Hyp = R11,
362  &R12Hyp = R12,
363  &LRHyp = Lr,
364  &R14Hyp = R14,
365  &PcHyp = Pc,
366  &R15Hyp = R15,
367 
368  /* UND mode */
369  &R0Und = R0,
370  &R1Und = R1,
371  &R2Und = R2,
372  &R3Und = R3,
373  &R4Und = R4,
374  &R5Und = R5,
375  &R6Und = R6,
376  &R7Und = R7,
377  &R8Und = R8,
378  &R9Und = R9,
379  &R10Und = R10,
380  &R11Und = R11,
381  &R12Und = R12,
382  &PcUnd = Pc,
383  &R15Und = R15,
384 
385  /* IRQ mode */
386  &R0Irq = R0,
387  &R1Irq = R1,
388  &R2Irq = R2,
389  &R3Irq = R3,
390  &R4Irq = R4,
391  &R5Irq = R5,
392  &R6Irq = R6,
393  &R7Irq = R7,
394  &R8Irq = R8,
395  &R9Irq = R9,
396  &R10Irq = R10,
397  &R11Irq = R11,
398  &R12Irq = R12,
399  &PcIrq = Pc,
400  &R15Irq = R15,
401 
402  /* FIQ mode */
403  &R0Fiq = R0,
404  &R1Fiq = R1,
405  &R2Fiq = R2,
406  &R3Fiq = R3,
407  &R4Fiq = R4,
408  &R5Fiq = R5,
409  &R6Fiq = R6,
410  &R7Fiq = R7,
411  &PcFiq = Pc,
412  &R15Fiq = R15;
413 
414 typedef const RegId RegMap[NumArchRegs];
415 
416 const RegMap Reg64Map = {
417  R0, R1, R2, R3, R4, R5, R6, R7,
418  R8Usr, R9Usr, R10Usr, R11Usr, R12Usr, R13Usr, R14Usr, R13Hyp,
419  R14Irq, R13Irq, R14Svc, R13Svc, R14Abt, R13Abt, R14Und, R13Und,
420  R8Fiq, R9Fiq, R10Fiq, R11Fiq, R12Fiq, R13Fiq, R14Fiq, Zero
421 };
422 
423 static inline RegId
424 x(unsigned index)
425 {
426  assert(index < NumArchRegs);
427  return RegId(IntRegClass, _X0Idx + index);
428 }
429 
430 const RegMap RegUsrMap = {
431  R0Usr, R1Usr, R2Usr, R3Usr, R4Usr, R5Usr, R6Usr, R7Usr,
432  R8Usr, R9Usr, R10Usr, R11Usr, R12Usr, R13Usr, R14Usr, R15Usr,
433  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
435 };
436 
437 static inline const RegId &
438 usr(unsigned index)
439 {
440  assert(index < NumArchRegs);
441  return RegUsrMap[index];
442 }
443 
444 const RegMap RegHypMap = {
445  R0Hyp, R1Hyp, R2Hyp, R3Hyp, R4Hyp, R5Hyp, R6Hyp, R7Hyp,
446  R8Hyp, R9Hyp, R10Hyp, R11Hyp, R12Hyp, R13Hyp, R14Hyp, R15Hyp,
447  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
449 };
450 
451 static inline const RegId &
452 hyp(unsigned index)
453 {
454  assert(index < NumArchRegs);
455  return RegHypMap[index];
456 }
457 
458 const RegMap RegSvcMap = {
459  R0Svc, R1Svc, R2Svc, R3Svc, R4Svc, R5Svc, R6Svc, R7Svc,
460  R8Svc, R9Svc, R10Svc, R11Svc, R12Svc, R13Svc, R14Svc, R15Svc,
461  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
463 };
464 
465 static inline const RegId &
466 svc(unsigned index)
467 {
468  assert(index < NumArchRegs);
469  return RegSvcMap[index];
470 }
471 
472 const RegMap RegMonMap = {
473  R0Mon, R1Mon, R2Mon, R3Mon, R4Mon, R5Mon, R6Mon, R7Mon,
474  R8Mon, R9Mon, R10Mon, R11Mon, R12Mon, R13Mon, R14Mon, R15Mon,
475  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
477 };
478 
479 static inline const RegId &
480 mon(unsigned index)
481 {
482  assert(index < NumArchRegs);
483  return RegMonMap[index];
484 }
485 
486 const RegMap RegAbtMap = {
487  R0Abt, R1Abt, R2Abt, R3Abt, R4Abt, R5Abt, R6Abt, R7Abt,
488  R8Abt, R9Abt, R10Abt, R11Abt, R12Abt, R13Abt, R14Abt, R15Abt,
489  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
491 };
492 
493 static inline const RegId &
494 abt(unsigned index)
495 {
496  assert(index < NumArchRegs);
497  return RegAbtMap[index];
498 }
499 
500 const RegMap RegUndMap = {
501  R0Und, R1Und, R2Und, R3Und, R4Und, R5Und, R6Und, R7Und,
502  R8Und, R9Und, R10Und, R11Und, R12Und, R13Und, R14Und, R15Und,
503  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
505 };
506 
507 static inline const RegId &
508 und(unsigned index)
509 {
510  assert(index < NumArchRegs);
511  return RegUndMap[index];
512 }
513 
514 const RegMap RegIrqMap = {
515  R0Irq, R1Irq, R2Irq, R3Irq, R4Irq, R5Irq, R6Irq, R7Irq,
516  R8Irq, R9Irq, R10Irq, R11Irq, R12Irq, R13Irq, R14Irq, R15Irq,
517  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
519 };
520 
521 static inline const RegId &
522 irq(unsigned index)
523 {
524  assert(index < NumArchRegs);
525  return RegIrqMap[index];
526 }
527 
528 const RegMap RegFiqMap = {
529  R0Fiq, R1Fiq, R2Fiq, R3Fiq, R4Fiq, R5Fiq, R6Fiq, R7Fiq,
530  R8Fiq, R9Fiq, R10Fiq, R11Fiq, R12Fiq, R13Fiq, R14Fiq, R15Fiq,
531  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
533 };
534 
535 static inline const RegId &
536 fiq(unsigned index)
537 {
538  assert(index < NumArchRegs);
539  return RegFiqMap[index];
540 }
541 
542 static const unsigned regsPerMode = NumRegs;
543 
544 static inline int
545 regInMode(OperatingMode mode, int reg)
546 {
547  assert(reg < NumArchRegs);
548  return mode * regsPerMode + reg;
549 }
550 
551 } // namespace int_reg
552 
553 static inline int
555 {
556  int mode = reg / int_reg::regsPerMode;
557  reg = reg % int_reg::regsPerMode;
558  switch (mode) {
559  case MODE_USER:
560  case MODE_SYSTEM:
561  return int_reg::usr(reg);
562  case MODE_FIQ:
563  return int_reg::fiq(reg);
564  case MODE_IRQ:
565  return int_reg::irq(reg);
566  case MODE_SVC:
567  return int_reg::svc(reg);
568  case MODE_MON:
569  return int_reg::mon(reg);
570  case MODE_ABORT:
571  return int_reg::abt(reg);
572  case MODE_HYP:
573  return int_reg::hyp(reg);
574  case MODE_UNDEFINED:
575  return int_reg::und(reg);
576  default:
577  panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
578  curTick(), reg, mode);
579  }
580 }
581 
582 
583 static inline RegIndex
585 {
586  if (reg == int_reg::X31)
587  reg = int_reg::Spx;
588  return reg;
589 }
590 
591 static inline bool
593 {
594  return (reg == int_reg::X31 || reg == int_reg::Spx);
595 }
596 
597 static inline bool
599 {
600  return reg == int_reg::Spx;
601 }
602 
603 static inline bool
605 {
606  return (reg == int_reg::X31 || reg == int_reg::Zero);
607 }
608 
609 static inline bool
611 {
612  return reg == int_reg::Zero;
613 }
614 
615 static inline RegIndex
617 {
618  if (reg == int_reg::X31)
619  reg = int_reg::Zero;
620  return reg;
621 }
622 
623 // Semantically meaningful register indices
624 inline constexpr size_t NumArgumentRegs = 4;
625 inline constexpr size_t NumArgumentRegs64 = 8;
626 inline constexpr auto
627  &ReturnValueReg = int_reg::X0,
628  &ReturnValueReg1 = int_reg::X1,
629  &ArgumentReg0 = int_reg::X0,
630  &ArgumentReg1 = int_reg::X1,
631  &ArgumentReg2 = int_reg::X2,
632  &FramePointerReg = int_reg::X11,
633  &StackPointerReg = int_reg::Sp,
635 
639 
640 } // namespace ArmISA
641 } // namespace gem5
642 
643 #endif
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::PowerISA::int_reg::_R10Idx
@ _R10Idx
Definition: int.hh:56
gem5::ArmISA::NumArgumentRegs64
constexpr size_t NumArgumentRegs64
Definition: int.hh:625
gem5::PowerISA::int_reg::R14
constexpr RegId R14(IntRegClass, _R14Idx)
gem5::PowerISA::int_reg::_R11Idx
@ _R11Idx
Definition: int.hh:57
gem5::PowerISA::int_reg::_R7Idx
@ _R7Idx
Definition: int.hh:53
gem5::ArmISA::MODE_SVC
@ MODE_SVC
Definition: types.hh:291
gem5::PowerISA::int_reg::R3
constexpr RegId R3(IntRegClass, _R3Idx)
gem5::PowerISA::int_reg::NumArchRegs
@ NumArchRegs
Definition: int.hh:79
gem5::ArmISA::MODE_MON
@ MODE_MON
Definition: types.hh:292
gem5::ArmISA::ArgumentReg0
constexpr auto & ArgumentReg0
Definition: int.hh:629
gem5::PowerISA::int_reg::R1
constexpr RegId R1(IntRegClass, _R1Idx)
gem5::PowerISA::int_reg::_R8Idx
@ _R8Idx
Definition: int.hh:54
gem5::ArmISA::MODE_FIQ
@ MODE_FIQ
Definition: types.hh:289
gem5::ArmISA::makeZero
static RegIndex makeZero(RegIndex reg)
Definition: int.hh:616
gem5::ArmISA::ArgumentReg2
constexpr auto & ArgumentReg2
Definition: int.hh:631
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::couldBeSP
static bool couldBeSP(RegIndex reg)
Definition: int.hh:592
gem5::ArmISA::FramePointerReg
constexpr auto & FramePointerReg
Definition: int.hh:632
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition: types.hh:295
gem5::PowerISA::int_reg::_R5Idx
@ _R5Idx
Definition: int.hh:51
gem5::ArmISA::MODE_IRQ
@ MODE_IRQ
Definition: types.hh:290
gem5::PowerISA::int_reg::R6
constexpr RegId R6(IntRegClass, _R6Idx)
gem5::ArmISA::SyscallSuccessReg
constexpr auto & SyscallSuccessReg
Definition: int.hh:638
gem5::PowerISA::int_reg::R7
constexpr RegId R7(IntRegClass, _R7Idx)
gem5::ArmISA::SyscallNumReg
constexpr auto & SyscallNumReg
Definition: int.hh:636
gem5::PowerISA::int_reg::R4
constexpr RegId R4(IntRegClass, _R4Idx)
gem5::ArmISA::isSP
static bool isSP(RegIndex reg)
Definition: int.hh:598
types.hh
gem5::PowerISA::int_reg::_R9Idx
@ _R9Idx
Definition: int.hh:55
gem5::ArmISA::uw
Bitfield< 31, 0 > uw
Definition: int.hh:62
gem5::PowerISA::int_reg::_R12Idx
@ _R12Idx
Definition: int.hh:58
gem5::ArmISA::ReturnAddressReg
constexpr auto & ReturnAddressReg
Definition: int.hh:634
gem5::PowerISA::int_reg::R10
constexpr RegId R10(IntRegClass, _R10Idx)
gem5::ArmISA::irq
Bitfield< 1 > irq
Definition: misc_types.hh:331
gem5::PowerISA::int_reg::_R14Idx
@ _R14Idx
Definition: int.hh:60
gem5::PowerISA::int_reg::NumRegs
@ NumRegs
Definition: int.hh:92
gem5::ArmISA::SyscallPseudoReturnReg
constexpr auto & SyscallPseudoReturnReg
Definition: int.hh:637
gem5::ArmISA::MODE_HYP
@ MODE_HYP
Definition: types.hh:294
gem5::ArmISA::BitUnion32
BitUnion32(PackedIntReg) Bitfield< 31
gem5::PowerISA::int_reg::R8
constexpr RegId R8(IntRegClass, _R8Idx)
gem5::VegaISA::x
Bitfield< 4 > x
Definition: pagetable.hh:61
gem5::PowerISA::int_reg::R2
constexpr RegId R2(IntRegClass, _R2Idx)
gem5::PowerISA::int_reg::R11
constexpr RegId R11(IntRegClass, _R11Idx)
gem5::PowerISA::int_reg::R9
constexpr RegId R9(IntRegClass, _R9Idx)
gem5::PowerISA::int_reg::R0
constexpr RegId R0(IntRegClass, _R0Idx)
gem5::ArmISA::isZero
static bool isZero(RegIndex reg)
Definition: int.hh:610
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:288
gem5::ArmISA::sw
SignedBitfield< 31, 0 > sw
Definition: int.hh:63
gem5::PowerISA::int_reg::_R6Idx
@ _R6Idx
Definition: int.hh:52
gem5::X86ISA::usr
Bitfield< 16 > usr
Definition: misc.hh:802
gem5::ArmISA::cc_reg::_ZeroIdx
@ _ZeroIdx
Definition: cc.hh:59
gem5::PowerISA::int_reg::_R1Idx
@ _R1Idx
Definition: int.hh:47
gem5::PowerISA::int_reg::_R4Idx
@ _R4Idx
Definition: int.hh:50
gem5::ArmISA::fiq
Bitfield< 2 > fiq
Definition: misc_types.hh:330
gem5::ArmISA::NumArgumentRegs
constexpr size_t NumArgumentRegs
Definition: int.hh:624
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ArmISA::uh1
uh1
Definition: int.hh:58
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::PowerISA::int_reg::_R0Idx
@ _R0Idx
Definition: int.hh:46
gem5::PowerISA::int_reg::_R13Idx
@ _R13Idx
Definition: int.hh:59
gem5::PowerISA::int_reg::_R3Idx
@ _R3Idx
Definition: int.hh:49
gem5::PowerISA::int_reg::_R15Idx
@ _R15Idx
Definition: int.hh:61
gem5::PowerISA::int_reg::R15
constexpr RegId R15(IntRegClass, _R15Idx)
gem5::PowerISA::int_reg::Lr
constexpr RegId Lr(IntRegClass, _LrIdx)
core.hh
reg_class.hh
gem5::ArmISA::MODE_SYSTEM
@ MODE_SYSTEM
Definition: types.hh:296
gem5::ArmISA::flattenIntRegModeIndex
static int flattenIntRegModeIndex(int reg)
Definition: int.hh:554
gem5::ArmISA::StackPointerReg
constexpr auto & StackPointerReg
Definition: int.hh:633
logging.hh
gem5::PowerISA::int_reg::_R2Idx
@ _R2Idx
Definition: int.hh:48
gem5::ArmISA::ReturnValueReg1
constexpr auto & ReturnValueReg1
Definition: int.hh:628
gem5::ArmISA::uh0
Bitfield< 15, 0 > uh0
Definition: int.hh:59
gem5::Pc
Definition: pc.hh:46
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::PowerISA::int_reg::R5
constexpr RegId R5(IntRegClass, _R5Idx)
gem5::ArmISA::MODE_ABORT
@ MODE_ABORT
Definition: types.hh:293
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::cc_reg::Zero
constexpr RegId Zero(CCRegClass, _ZeroIdx)
gem5::ArmISA::couldBeZero
static bool couldBeZero(RegIndex reg)
Definition: int.hh:604
gem5::ArmISA::sh1
SignedBitfield< 31, 16 > sh1
Definition: int.hh:60
gem5::ArmISA::EndBitUnion
EndBitUnion(PackedIntReg) namespace int_reg
Definition: int.hh:64
gem5::PowerISA::int_reg::R12
constexpr RegId R12(IntRegClass, _R12Idx)
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::ArmISA::makeSP
static RegIndex makeSP(RegIndex reg)
Definition: int.hh:584
gem5::PowerISA::int_reg::R13
constexpr RegId R13(IntRegClass, _R13Idx)
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::ArgumentReg1
constexpr auto & ArgumentReg1
Definition: int.hh:630
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::ArmISA::ReturnValueReg
constexpr auto & ReturnValueReg
Definition: int.hh:627
gem5::ArmISA::sh0
SignedBitfield< 15, 0 > sh0
Definition: int.hh:61

Generated on Thu Jul 28 2022 13:32:24 for gem5 by doxygen 1.8.17