gem5  v22.1.0.0
int.hh
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40 
41 #include <cassert>
42 
43 #ifndef __ARCH_ARM_REGS_INT_HH__
44 #define __ARCH_ARM_REGS_INT_HH__
45 
46 #include "arch/arm/types.hh"
47 #include "base/logging.hh"
48 #include "cpu/reg_class.hh"
49 #include "debug/IntRegs.hh"
50 #include "sim/core.hh"
51 
52 namespace gem5
53 {
54 
55 namespace ArmISA
56 {
57 
58 BitUnion32(PackedIntReg)
59  Bitfield<31, 16> uh1;
60  Bitfield<15, 0> uh0;
61  SignedBitfield<31, 16> sh1;
62  SignedBitfield<15, 0> sh0;
63  Bitfield<31, 0> uw;
64  SignedBitfield<31, 0> sw;
65 EndBitUnion(PackedIntReg)
66 
67 namespace int_reg
68 {
69 
70 enum : RegIndex
71 {
72  /* All the unique register indices. */
73  _R0Idx,
74  _R1Idx,
75  _R2Idx,
76  _R3Idx,
77  _R4Idx,
78  _R5Idx,
79  _R6Idx,
80  _R7Idx,
81  _R8Idx,
82  _R9Idx,
83  _R10Idx,
84  _R11Idx,
85  _R12Idx,
86  _R13Idx,
87  _R14Idx,
88  _R15Idx,
89 
90  _R13SvcIdx,
91  _R14SvcIdx,
92 
93  _R13MonIdx,
94  _R14MonIdx,
95 
96  _R13HypIdx,
97 
98  _R13AbtIdx,
99  _R14AbtIdx,
100 
101  _R13UndIdx,
102  _R14UndIdx,
103 
104  _R13IrqIdx,
105  _R14IrqIdx,
106 
107  _R8FiqIdx,
108  _R9FiqIdx,
109  _R10FiqIdx,
110  _R11FiqIdx,
111  _R12FiqIdx,
112  _R13FiqIdx,
113  _R14FiqIdx,
114 
115  _ZeroIdx,
116  _Ureg0Idx,
117  _Ureg1Idx,
118  _Ureg2Idx,
119 
120  _Sp0Idx,
121  _Sp1Idx,
122  _Sp2Idx,
123  _Sp3Idx,
124 
125  NumRegs,
126  _SpxIdx = NumRegs,
127 
128  NumArchRegs = 32,
129 
130  _X0Idx = 0,
131  _X1Idx,
132  _X2Idx,
133  _X3Idx,
134  _X4Idx,
135  _X5Idx,
136  _X6Idx,
137  _X7Idx,
138  _X8Idx,
139  _X9Idx,
140  _X10Idx,
141  _X11Idx,
142  _X12Idx,
143  _X13Idx,
144  _X14Idx,
145  _X15Idx,
146  _X16Idx,
147  _X17Idx,
148  _X18Idx,
149  _X19Idx,
150  _X20Idx,
151  _X21Idx,
152  _X22Idx,
153  _X23Idx,
154  _X24Idx,
155  _X25Idx,
156  _X26Idx,
157  _X27Idx,
158  _X28Idx,
159  _X29Idx,
160  _X30Idx,
161  _X31Idx
162 };
163 
164 } // namespace int_reg
165 
167 {
168  RegId flatten(const BaseISA &isa, const RegId &id) const override;
169 };
170 
172 
173 inline constexpr RegClass intRegClass =
175  ops(intRegClassOps).
176  needsFlattening();
177 
178 inline constexpr RegClass flatIntRegClass =
180 
181 namespace int_reg
182 {
183 
184 inline constexpr RegId
185  /* All the unique register indices. */
202 
203  R13Svc = intRegClass[_R13SvcIdx],
204  R14Svc = intRegClass[_R14SvcIdx],
205 
206  R13Mon = intRegClass[_R13MonIdx],
207  R14Mon = intRegClass[_R14MonIdx],
208 
209  R13Hyp = intRegClass[_R13HypIdx],
210 
211  R13Abt = intRegClass[_R13AbtIdx],
212  R14Abt = intRegClass[_R14AbtIdx],
213 
214  R13Und = intRegClass[_R13UndIdx],
215  R14Und = intRegClass[_R14UndIdx],
216 
217  R13Irq = intRegClass[_R13IrqIdx],
218  R14Irq = intRegClass[_R14IrqIdx],
219 
220  R8Fiq = intRegClass[_R8FiqIdx],
221  R9Fiq = intRegClass[_R9FiqIdx],
222  R10Fiq = intRegClass[_R10FiqIdx],
223  R11Fiq = intRegClass[_R11FiqIdx],
224  R12Fiq = intRegClass[_R12FiqIdx],
225  R13Fiq = intRegClass[_R13FiqIdx],
226  R14Fiq = intRegClass[_R14FiqIdx],
227 
230  Ureg1 = intRegClass[_Ureg1Idx],
231  Ureg2 = intRegClass[_Ureg2Idx],
232 
233  Sp0 = intRegClass[_Sp0Idx],
234  Sp1 = intRegClass[_Sp1Idx],
235  Sp2 = intRegClass[_Sp2Idx],
236  Sp3 = intRegClass[_Sp3Idx],
237 
238  Spx = intRegClass[_SpxIdx],
239 
240  X0 = intRegClass[_X0Idx],
241  X1 = intRegClass[_X1Idx],
242  X2 = intRegClass[_X2Idx],
243  X3 = intRegClass[_X3Idx],
244  X4 = intRegClass[_X4Idx],
245  X5 = intRegClass[_X5Idx],
246  X6 = intRegClass[_X6Idx],
247  X7 = intRegClass[_X7Idx],
248  X8 = intRegClass[_X8Idx],
249  X9 = intRegClass[_X9Idx],
250  X10 = intRegClass[_X10Idx],
251  X11 = intRegClass[_X11Idx],
252  X12 = intRegClass[_X12Idx],
253  X13 = intRegClass[_X13Idx],
254  X14 = intRegClass[_X14Idx],
255  X15 = intRegClass[_X15Idx],
256  X16 = intRegClass[_X16Idx],
257  X17 = intRegClass[_X17Idx],
258  X18 = intRegClass[_X18Idx],
259  X19 = intRegClass[_X19Idx],
260  X20 = intRegClass[_X20Idx],
261  X21 = intRegClass[_X21Idx],
262  X22 = intRegClass[_X22Idx],
263  X23 = intRegClass[_X23Idx],
264  X24 = intRegClass[_X24Idx],
265  X25 = intRegClass[_X25Idx],
266  X26 = intRegClass[_X26Idx],
267  X27 = intRegClass[_X27Idx],
268  X28 = intRegClass[_X28Idx],
269  X29 = intRegClass[_X29Idx],
270  X30 = intRegClass[_X30Idx],
271  X31 = intRegClass[_X31Idx];
272 
273 inline constexpr auto
274  &Sp = R13,
275  &Lr = R14,
276  &Pc = R15,
277 
280 
283 
285 
288 
291 
294 
297 
298  /* USR mode */
299  &R0Usr = R0,
300  &R1Usr = R1,
301  &R2Usr = R2,
302  &R3Usr = R3,
303  &R4Usr = R4,
304  &R5Usr = R5,
305  &R6Usr = R6,
306  &R7Usr = R7,
307  &R8Usr = R8,
308  &R9Usr = R9,
313  &SPUsr = Sp,
315  &LRUsr = Lr,
317  &PcUsr = Pc,
318 
319  /* SVC mode */
320  &R0Svc = R0,
321  &R1Svc = R1,
322  &R2Svc = R2,
323  &R3Svc = R3,
324  &R4Svc = R4,
325  &R5Svc = R5,
326  &R6Svc = R6,
327  &R7Svc = R7,
328  &R8Svc = R8,
329  &R9Svc = R9,
333  &PcSvc = Pc,
335 
336  /* MON mode */
337  &R0Mon = R0,
338  &R1Mon = R1,
339  &R2Mon = R2,
340  &R3Mon = R3,
341  &R4Mon = R4,
342  &R5Mon = R5,
343  &R6Mon = R6,
344  &R7Mon = R7,
345  &R8Mon = R8,
346  &R9Mon = R9,
350  &PcMon = Pc,
352 
353  /* ABT mode */
354  &R0Abt = R0,
355  &R1Abt = R1,
356  &R2Abt = R2,
357  &R3Abt = R3,
358  &R4Abt = R4,
359  &R5Abt = R5,
360  &R6Abt = R6,
361  &R7Abt = R7,
362  &R8Abt = R8,
363  &R9Abt = R9,
367  &PcAbt = Pc,
369 
370  /* HYP mode */
371  &R0Hyp = R0,
372  &R1Hyp = R1,
373  &R2Hyp = R2,
374  &R3Hyp = R3,
375  &R4Hyp = R4,
376  &R5Hyp = R5,
377  &R6Hyp = R6,
378  &R7Hyp = R7,
379  &R8Hyp = R8,
380  &R9Hyp = R9,
384  &LRHyp = Lr,
386  &PcHyp = Pc,
388 
389  /* UND mode */
390  &R0Und = R0,
391  &R1Und = R1,
392  &R2Und = R2,
393  &R3Und = R3,
394  &R4Und = R4,
395  &R5Und = R5,
396  &R6Und = R6,
397  &R7Und = R7,
398  &R8Und = R8,
399  &R9Und = R9,
403  &PcUnd = Pc,
405 
406  /* IRQ mode */
407  &R0Irq = R0,
408  &R1Irq = R1,
409  &R2Irq = R2,
410  &R3Irq = R3,
411  &R4Irq = R4,
412  &R5Irq = R5,
413  &R6Irq = R6,
414  &R7Irq = R7,
415  &R8Irq = R8,
416  &R9Irq = R9,
420  &PcIrq = Pc,
422 
423  /* FIQ mode */
424  &R0Fiq = R0,
425  &R1Fiq = R1,
426  &R2Fiq = R2,
427  &R3Fiq = R3,
428  &R4Fiq = R4,
429  &R5Fiq = R5,
430  &R6Fiq = R6,
431  &R7Fiq = R7,
432  &PcFiq = Pc,
434 
435 typedef const RegId RegMap[NumArchRegs];
436 
437 const RegMap Reg64Map = {
438  R0, R1, R2, R3, R4, R5, R6, R7,
442 };
443 
444 static inline RegId
445 x(unsigned index)
446 {
447  assert(index < NumArchRegs);
448  return intRegClass[_X0Idx + index];
449 }
450 
451 const RegMap RegUsrMap = {
454  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
456 };
457 
458 static inline const RegId &
459 usr(unsigned index)
460 {
461  assert(index < NumArchRegs);
462  return RegUsrMap[index];
463 }
464 
465 const RegMap RegHypMap = {
468  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
470 };
471 
472 static inline const RegId &
473 hyp(unsigned index)
474 {
475  assert(index < NumArchRegs);
476  return RegHypMap[index];
477 }
478 
479 const RegMap RegSvcMap = {
482  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
484 };
485 
486 static inline const RegId &
487 svc(unsigned index)
488 {
489  assert(index < NumArchRegs);
490  return RegSvcMap[index];
491 }
492 
493 const RegMap RegMonMap = {
496  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
498 };
499 
500 static inline const RegId &
501 mon(unsigned index)
502 {
503  assert(index < NumArchRegs);
504  return RegMonMap[index];
505 }
506 
507 const RegMap RegAbtMap = {
510  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
512 };
513 
514 static inline const RegId &
515 abt(unsigned index)
516 {
517  assert(index < NumArchRegs);
518  return RegAbtMap[index];
519 }
520 
521 const RegMap RegUndMap = {
524  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
526 };
527 
528 static inline const RegId &
529 und(unsigned index)
530 {
531  assert(index < NumArchRegs);
532  return RegUndMap[index];
533 }
534 
535 const RegMap RegIrqMap = {
538  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
540 };
541 
542 static inline const RegId &
543 irq(unsigned index)
544 {
545  assert(index < NumArchRegs);
546  return RegIrqMap[index];
547 }
548 
549 const RegMap RegFiqMap = {
552  Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
554 };
555 
556 static inline const RegId &
557 fiq(unsigned index)
558 {
559  assert(index < NumArchRegs);
560  return RegFiqMap[index];
561 }
562 
563 static const unsigned regsPerMode = NumRegs;
564 
565 static inline int
567 {
568  assert(reg < NumArchRegs);
569  return mode * regsPerMode + reg;
570 }
571 
572 } // namespace int_reg
573 
574 static inline const RegId &
576 {
577  int mode = reg / int_reg::regsPerMode;
579  switch (mode) {
580  case MODE_USER:
581  case MODE_SYSTEM:
582  return int_reg::usr(reg);
583  case MODE_FIQ:
584  return int_reg::fiq(reg);
585  case MODE_IRQ:
586  return int_reg::irq(reg);
587  case MODE_SVC:
588  return int_reg::svc(reg);
589  case MODE_MON:
590  return int_reg::mon(reg);
591  case MODE_ABORT:
592  return int_reg::abt(reg);
593  case MODE_HYP:
594  return int_reg::hyp(reg);
595  case MODE_UNDEFINED:
596  return int_reg::und(reg);
597  default:
598  panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
599  curTick(), reg, mode);
600  }
601 }
602 
603 
604 static inline RegIndex
606 {
607  if (reg == int_reg::X31)
608  reg = int_reg::Spx;
609  return reg;
610 }
611 
612 static inline bool
614 {
615  return (reg == int_reg::X31 || reg == int_reg::Spx);
616 }
617 
618 static inline bool
620 {
621  return reg == int_reg::Spx;
622 }
623 
624 static inline bool
626 {
627  return (reg == int_reg::X31 || reg == int_reg::Zero);
628 }
629 
630 static inline bool
632 {
633  return reg == int_reg::Zero;
634 }
635 
636 static inline RegIndex
638 {
639  if (reg == int_reg::X31)
640  reg = int_reg::Zero;
641  return reg;
642 }
643 
644 // Semantically meaningful register indices
645 inline constexpr size_t NumArgumentRegs = 4;
646 inline constexpr size_t NumArgumentRegs64 = 8;
647 inline constexpr auto
656 
660 
661 } // namespace ArmISA
662 } // namespace gem5
663 
664 #endif
RegId flatten(const BaseISA &isa, const RegId &id) const override
Flatten register id id using information in the ISA object isa.
Definition: int.cc:55
Definition: pc.hh:47
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
constexpr auto & R11Svc
Definition: int.hh:331
constexpr auto & R9Irq
Definition: int.hh:416
constexpr auto & R5Hyp
Definition: int.hh:376
static const RegId & usr(unsigned index)
Definition: int.hh:459
constexpr RegId X0
Definition: int.hh:240
constexpr auto & LRIrq
Definition: int.hh:293
constexpr RegId R14Und
Definition: int.hh:215
constexpr RegId X30
Definition: int.hh:270
static const RegId & hyp(unsigned index)
Definition: int.hh:473
constexpr auto & PcHyp
Definition: int.hh:386
constexpr RegId X17
Definition: int.hh:257
constexpr RegId R4
Definition: int.hh:190
constexpr RegId X6
Definition: int.hh:246
constexpr RegId Sp2
Definition: int.hh:235
constexpr auto & R15Svc
Definition: int.hh:334
constexpr auto & R0Fiq
Definition: int.hh:424
constexpr RegId R9
Definition: int.hh:195
const RegMap RegIrqMap
Definition: int.hh:535
constexpr RegId R6
Definition: int.hh:192
constexpr auto & R9Abt
Definition: int.hh:363
constexpr auto & R8Irq
Definition: int.hh:415
constexpr auto & R6Usr
Definition: int.hh:305
constexpr auto & R3Und
Definition: int.hh:393
constexpr RegId R14Abt
Definition: int.hh:212
constexpr auto & R0Mon
Definition: int.hh:337
constexpr auto & SPUsr
Definition: int.hh:313
constexpr auto & R11Abt
Definition: int.hh:365
constexpr RegId R9Fiq
Definition: int.hh:221
constexpr RegId Sp3
Definition: int.hh:236
static const RegId & und(unsigned index)
Definition: int.hh:529
constexpr auto & LRHyp
Definition: int.hh:384
constexpr auto & LRMon
Definition: int.hh:282
constexpr RegId X13
Definition: int.hh:253
constexpr auto & R1Irq
Definition: int.hh:408
constexpr auto & Sp
Definition: int.hh:274
constexpr RegId R14Mon
Definition: int.hh:207
constexpr RegId X14
Definition: int.hh:254
constexpr auto & R13Usr
Definition: int.hh:312
constexpr RegId X1
Definition: int.hh:241
static const RegId & fiq(unsigned index)
Definition: int.hh:557
constexpr auto & R11Usr
Definition: int.hh:310
constexpr auto & R11Mon
Definition: int.hh:348
constexpr auto & R4Fiq
Definition: int.hh:428
constexpr RegId R12
Definition: int.hh:198
const RegId RegMap[NumArchRegs]
Definition: int.hh:435
constexpr auto & R12Hyp
Definition: int.hh:383
constexpr auto & R1Abt
Definition: int.hh:355
constexpr auto & R8Svc
Definition: int.hh:328
constexpr auto & R0Und
Definition: int.hh:390
constexpr auto & R5Und
Definition: int.hh:395
constexpr auto & R12Und
Definition: int.hh:402
constexpr auto & SPMon
Definition: int.hh:281
constexpr RegId Sp0
Definition: int.hh:233
constexpr RegId X27
Definition: int.hh:267
constexpr RegId R14Fiq
Definition: int.hh:226
constexpr auto & R2Svc
Definition: int.hh:322
constexpr auto & R10Und
Definition: int.hh:400
constexpr RegId X20
Definition: int.hh:260
constexpr auto & R1Hyp
Definition: int.hh:372
constexpr RegId R13Irq
Definition: int.hh:217
constexpr auto & LRFiq
Definition: int.hh:296
constexpr auto & R2Mon
Definition: int.hh:339
constexpr RegId X18
Definition: int.hh:258
constexpr RegId R7
Definition: int.hh:193
constexpr auto & R3Hyp
Definition: int.hh:374
constexpr auto & R10Svc
Definition: int.hh:330
constexpr auto & R5Mon
Definition: int.hh:342
constexpr RegId X3
Definition: int.hh:243
constexpr RegId X29
Definition: int.hh:269
constexpr auto & R14Hyp
Definition: int.hh:385
static RegId x(unsigned index)
Definition: int.hh:445
constexpr auto & R11Hyp
Definition: int.hh:382
constexpr auto & PcAbt
Definition: int.hh:367
constexpr auto & PcIrq
Definition: int.hh:420
constexpr auto & SPFiq
Definition: int.hh:295
constexpr auto & R1Fiq
Definition: int.hh:425
constexpr auto & R1Usr
Definition: int.hh:300
constexpr auto & R4Irq
Definition: int.hh:411
constexpr RegId Sp1
Definition: int.hh:234
constexpr auto & R3Abt
Definition: int.hh:357
constexpr auto & R2Hyp
Definition: int.hh:373
constexpr RegId X12
Definition: int.hh:252
constexpr auto & SPIrq
Definition: int.hh:292
constexpr auto & R2Und
Definition: int.hh:392
constexpr auto & SPUnd
Definition: int.hh:289
constexpr auto & R3Mon
Definition: int.hh:340
constexpr auto & R8Abt
Definition: int.hh:362
constexpr RegId X26
Definition: int.hh:266
constexpr auto & R3Fiq
Definition: int.hh:427
static const RegId & abt(unsigned index)
Definition: int.hh:515
constexpr auto & R9Mon
Definition: int.hh:346
constexpr RegId X24
Definition: int.hh:264
constexpr auto & R10Hyp
Definition: int.hh:381
const RegMap RegUsrMap
Definition: int.hh:451
constexpr auto & R1Und
Definition: int.hh:391
static const RegId & svc(unsigned index)
Definition: int.hh:487
constexpr RegId X16
Definition: int.hh:256
constexpr RegId Ureg0
Definition: int.hh:229
constexpr RegId X21
Definition: int.hh:261
constexpr auto & R8Mon
Definition: int.hh:345
constexpr auto & R3Irq
Definition: int.hh:410
constexpr auto & R5Usr
Definition: int.hh:304
constexpr RegId X4
Definition: int.hh:244
const RegMap RegSvcMap
Definition: int.hh:479
constexpr auto & R11Und
Definition: int.hh:401
constexpr auto & R12Svc
Definition: int.hh:332
constexpr auto & R8Usr
Definition: int.hh:307
constexpr auto & R10Abt
Definition: int.hh:364
constexpr RegId R3
Definition: int.hh:189
constexpr RegId R11Fiq
Definition: int.hh:223
constexpr auto & R6Irq
Definition: int.hh:413
constexpr auto & LRUnd
Definition: int.hh:290
constexpr auto & R6Svc
Definition: int.hh:326
constexpr auto & R12Abt
Definition: int.hh:366
constexpr auto & R5Irq
Definition: int.hh:412
constexpr auto & R8Und
Definition: int.hh:398
constexpr auto & R2Irq
Definition: int.hh:409
constexpr RegId R13Mon
Definition: int.hh:206
constexpr RegId R8
Definition: int.hh:194
constexpr RegId X9
Definition: int.hh:249
constexpr RegId Zero
Definition: int.hh:228
constexpr auto & R0Hyp
Definition: int.hh:371
const RegMap RegFiqMap
Definition: int.hh:549
constexpr auto & R9Und
Definition: int.hh:399
constexpr auto & Pc
Definition: int.hh:276
constexpr RegId Spx
Definition: int.hh:238
constexpr auto & R15Fiq
Definition: int.hh:433
constexpr RegId R13Svc
Definition: int.hh:203
constexpr auto & R2Usr
Definition: int.hh:301
constexpr auto & R4Usr
Definition: int.hh:303
constexpr auto & R12Usr
Definition: int.hh:311
constexpr RegId Ureg1
Definition: int.hh:230
constexpr auto & R3Svc
Definition: int.hh:323
constexpr auto & R7Und
Definition: int.hh:397
constexpr RegId X23
Definition: int.hh:263
constexpr auto & PcUsr
Definition: int.hh:317
constexpr RegId X28
Definition: int.hh:268
constexpr RegId R8Fiq
Definition: int.hh:220
constexpr auto & SPAbt
Definition: int.hh:286
constexpr RegId R14Irq
Definition: int.hh:218
constexpr auto & R2Abt
Definition: int.hh:356
constexpr auto & R7Svc
Definition: int.hh:327
constexpr auto & R7Hyp
Definition: int.hh:378
constexpr auto & R6Mon
Definition: int.hh:343
constexpr auto & R6Und
Definition: int.hh:396
constexpr auto & R0Svc
Definition: int.hh:320
constexpr auto & R10Irq
Definition: int.hh:417
constexpr RegId R13Fiq
Definition: int.hh:225
const RegMap RegAbtMap
Definition: int.hh:507
constexpr RegId R13Hyp
Definition: int.hh:209
constexpr RegId R13Abt
Definition: int.hh:211
const RegMap RegMonMap
Definition: int.hh:493
constexpr RegId R14Svc
Definition: int.hh:204
const RegMap Reg64Map
Definition: int.hh:437
constexpr RegId X7
Definition: int.hh:247
constexpr auto & R12Irq
Definition: int.hh:419
constexpr RegId X19
Definition: int.hh:259
constexpr auto & LRUsr
Definition: int.hh:315
constexpr auto & R4Hyp
Definition: int.hh:375
static const RegId & mon(unsigned index)
Definition: int.hh:501
constexpr auto & PcUnd
Definition: int.hh:403
constexpr auto & LRAbt
Definition: int.hh:287
constexpr RegId R11
Definition: int.hh:197
constexpr auto & R15Hyp
Definition: int.hh:387
constexpr auto & R15Und
Definition: int.hh:404
constexpr RegId X22
Definition: int.hh:262
constexpr auto & PcMon
Definition: int.hh:350
constexpr RegId X25
Definition: int.hh:265
constexpr auto & R8Hyp
Definition: int.hh:379
constexpr auto & R2Fiq
Definition: int.hh:426
constexpr auto & R1Svc
Definition: int.hh:321
constexpr auto & R3Usr
Definition: int.hh:302
constexpr auto & R15Usr
Definition: int.hh:316
constexpr auto & R7Fiq
Definition: int.hh:431
constexpr RegId R5
Definition: int.hh:191
static const RegId & irq(unsigned index)
Definition: int.hh:543
constexpr auto & R4Abt
Definition: int.hh:358
constexpr auto & PcFiq
Definition: int.hh:432
constexpr auto & R4Svc
Definition: int.hh:324
constexpr RegId X8
Definition: int.hh:248
constexpr auto & PcSvc
Definition: int.hh:333
constexpr auto & R12Mon
Definition: int.hh:349
constexpr RegId R14
Definition: int.hh:200
constexpr auto & R10Usr
Definition: int.hh:309
constexpr auto & R4Mon
Definition: int.hh:341
constexpr RegId X31
Definition: int.hh:271
constexpr auto & R6Abt
Definition: int.hh:360
constexpr auto & R9Hyp
Definition: int.hh:380
constexpr auto & R1Mon
Definition: int.hh:338
constexpr auto & R5Svc
Definition: int.hh:325
constexpr auto & R7Abt
Definition: int.hh:361
constexpr RegId R13Und
Definition: int.hh:214
constexpr RegId X11
Definition: int.hh:251
constexpr auto & R0Usr
Definition: int.hh:299
constexpr auto & Lr
Definition: int.hh:275
constexpr RegId R10
Definition: int.hh:196
constexpr RegId X2
Definition: int.hh:242
constexpr auto & R9Usr
Definition: int.hh:308
constexpr auto & R0Irq
Definition: int.hh:407
constexpr auto & R6Hyp
Definition: int.hh:377
const RegMap RegUndMap
Definition: int.hh:521
constexpr auto & R7Mon
Definition: int.hh:344
static int regInMode(OperatingMode mode, int reg)
Definition: int.hh:566
constexpr RegId R2
Definition: int.hh:188
constexpr auto & R7Irq
Definition: int.hh:414
constexpr auto & R10Mon
Definition: int.hh:347
constexpr auto & R5Abt
Definition: int.hh:359
constexpr auto & R4Und
Definition: int.hh:394
constexpr RegId X15
Definition: int.hh:255
constexpr RegId R1
Definition: int.hh:187
constexpr auto & R5Fiq
Definition: int.hh:429
constexpr auto & SpSvc
Definition: int.hh:278
const RegMap RegHypMap
Definition: int.hh:465
constexpr RegId R15
Definition: int.hh:201
constexpr auto & R15Irq
Definition: int.hh:421
constexpr RegId X5
Definition: int.hh:245
constexpr auto & R6Fiq
Definition: int.hh:430
constexpr RegId R0
Definition: int.hh:186
constexpr auto & LRSvc
Definition: int.hh:279
constexpr RegId X10
Definition: int.hh:250
constexpr RegId R10Fiq
Definition: int.hh:222
constexpr RegId R12Fiq
Definition: int.hh:224
constexpr auto & R0Abt
Definition: int.hh:354
constexpr RegId Ureg2
Definition: int.hh:231
constexpr auto & R15Mon
Definition: int.hh:351
constexpr RegId R13
Definition: int.hh:199
constexpr auto & R7Usr
Definition: int.hh:306
constexpr auto & R14Usr
Definition: int.hh:314
constexpr auto & SPHyp
Definition: int.hh:284
constexpr auto & R15Abt
Definition: int.hh:368
static const unsigned regsPerMode
Definition: int.hh:563
constexpr auto & R11Irq
Definition: int.hh:418
constexpr auto & R9Svc
Definition: int.hh:329
constexpr auto & SyscallSuccessReg
Definition: int.hh:659
static bool isSP(RegIndex reg)
Definition: int.hh:619
@ MODE_SYSTEM
Definition: types.hh:296
@ MODE_ABORT
Definition: types.hh:293
@ MODE_UNDEFINED
Definition: types.hh:295
constexpr RegClass flatIntRegClass
Definition: int.hh:178
constexpr auto & ArgumentReg0
Definition: int.hh:650
Bitfield< 15, 0 > uh0
Definition: int.hh:60
static bool couldBeZero(RegIndex reg)
Definition: int.hh:625
static bool couldBeSP(RegIndex reg)
Definition: int.hh:613
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
Bitfield< 31, 0 > uw
Definition: int.hh:63
constexpr auto & ArgumentReg2
Definition: int.hh:652
constexpr auto & ReturnValueReg
Definition: int.hh:648
SignedBitfield< 31, 0 > sw
Definition: int.hh:64
constexpr auto & SyscallPseudoReturnReg
Definition: int.hh:658
constexpr auto & StackPointerReg
Definition: int.hh:654
constexpr auto & ArgumentReg1
Definition: int.hh:651
static bool isZero(RegIndex reg)
Definition: int.hh:631
constexpr auto & ReturnAddressReg
Definition: int.hh:655
static RegIndex makeSP(RegIndex reg)
Definition: int.hh:605
constexpr auto & SyscallNumReg
Definition: int.hh:657
constexpr auto & ReturnValueReg1
Definition: int.hh:649
constexpr size_t NumArgumentRegs
Definition: int.hh:645
EndBitUnion(PackedIntReg) namespace int_reg
Definition: int.hh:65
constexpr RegClass intRegClass
Definition: int.hh:173
static const RegId & flattenIntRegModeIndex(int reg)
Definition: int.hh:575
constexpr size_t NumArgumentRegs64
Definition: int.hh:646
SignedBitfield< 31, 16 > sh1
Definition: int.hh:61
static RegIndex makeZero(RegIndex reg)
Definition: int.hh:637
SignedBitfield< 15, 0 > sh0
Definition: int.hh:62
constexpr IntRegClassOps intRegClassOps
Definition: int.hh:171
BitUnion32(PackedIntReg) Bitfield< 31
constexpr auto & FramePointerReg
Definition: int.hh:653
Bitfield< 30, 0 > index
const int NumRegs
Definition: int.hh:67
Bitfield< 5, 3 > reg
Definition: types.hh:92
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
constexpr char IntRegClassName[]
Definition: reg_class.hh:73
@ IntRegClass
Integer register.
Definition: reg_class.hh:60

Generated on Wed Dec 21 2022 10:22:26 for gem5 by doxygen 1.9.1