gem5::ArmISA::int_reg Namespace Reference

Typedefs
typedef const RegId	RegMap[NumArchRegs]

Functions
static RegId	x (unsigned index)
static const RegId &	usr (unsigned index)
static const RegId &	hyp (unsigned index)
static const RegId &	svc (unsigned index)
static const RegId &	mon (unsigned index)
static const RegId &	abt (unsigned index)
static const RegId &	und (unsigned index)
static const RegId &	irq (unsigned index)
static const RegId &	fiq (unsigned index)
static int	regInMode (OperatingMode mode, int reg)

Variables
constexpr RegId	R0 = intRegClass[_R0Idx]
constexpr RegId	R1 = intRegClass[_R1Idx]
constexpr RegId	R2 = intRegClass[_R2Idx]
constexpr RegId	R3 = intRegClass[_R3Idx]
constexpr RegId	R4 = intRegClass[_R4Idx]
constexpr RegId	R5 = intRegClass[_R5Idx]
constexpr RegId	R6 = intRegClass[_R6Idx]
constexpr RegId	R7 = intRegClass[_R7Idx]
constexpr RegId	R8 = intRegClass[_R8Idx]
constexpr RegId	R9 = intRegClass[_R9Idx]
constexpr RegId	R10 = intRegClass[_R10Idx]
constexpr RegId	R11 = intRegClass[_R11Idx]
constexpr RegId	R12 = intRegClass[_R12Idx]
constexpr RegId	R13 = intRegClass[_R13Idx]
constexpr RegId	R14 = intRegClass[_R14Idx]
constexpr RegId	R15 = intRegClass[_R15Idx]
constexpr RegId	R13Svc = intRegClass[_R13SvcIdx]
constexpr RegId	R14Svc = intRegClass[_R14SvcIdx]
constexpr RegId	R13Mon = intRegClass[_R13MonIdx]
constexpr RegId	R14Mon = intRegClass[_R14MonIdx]
constexpr RegId	R13Hyp = intRegClass[_R13HypIdx]
constexpr RegId	R13Abt = intRegClass[_R13AbtIdx]
constexpr RegId	R14Abt = intRegClass[_R14AbtIdx]
constexpr RegId	R13Und = intRegClass[_R13UndIdx]
constexpr RegId	R14Und = intRegClass[_R14UndIdx]
constexpr RegId	R13Irq = intRegClass[_R13IrqIdx]
constexpr RegId	R14Irq = intRegClass[_R14IrqIdx]
constexpr RegId	R8Fiq = intRegClass[_R8FiqIdx]
constexpr RegId	R9Fiq = intRegClass[_R9FiqIdx]
constexpr RegId	R10Fiq = intRegClass[_R10FiqIdx]
constexpr RegId	R11Fiq = intRegClass[_R11FiqIdx]
constexpr RegId	R12Fiq = intRegClass[_R12FiqIdx]
constexpr RegId	R13Fiq = intRegClass[_R13FiqIdx]
constexpr RegId	R14Fiq = intRegClass[_R14FiqIdx]
constexpr RegId	Zero = intRegClass[_ZeroIdx]
constexpr RegId	Ureg0 = intRegClass[_Ureg0Idx]
constexpr RegId	Ureg1 = intRegClass[_Ureg1Idx]
constexpr RegId	Ureg2 = intRegClass[_Ureg2Idx]
constexpr RegId	Sp0 = intRegClass[_Sp0Idx]
constexpr RegId	Sp1 = intRegClass[_Sp1Idx]
constexpr RegId	Sp2 = intRegClass[_Sp2Idx]
constexpr RegId	Sp3 = intRegClass[_Sp3Idx]
constexpr RegId	Spx = intRegClass[_SpxIdx]
constexpr RegId	X0 = intRegClass[_X0Idx]
constexpr RegId	X1 = intRegClass[_X1Idx]
constexpr RegId	X2 = intRegClass[_X2Idx]
constexpr RegId	X3 = intRegClass[_X3Idx]
constexpr RegId	X4 = intRegClass[_X4Idx]
constexpr RegId	X5 = intRegClass[_X5Idx]
constexpr RegId	X6 = intRegClass[_X6Idx]
constexpr RegId	X7 = intRegClass[_X7Idx]
constexpr RegId	X8 = intRegClass[_X8Idx]
constexpr RegId	X9 = intRegClass[_X9Idx]
constexpr RegId	X10 = intRegClass[_X10Idx]
constexpr RegId	X11 = intRegClass[_X11Idx]
constexpr RegId	X12 = intRegClass[_X12Idx]
constexpr RegId	X13 = intRegClass[_X13Idx]
constexpr RegId	X14 = intRegClass[_X14Idx]
constexpr RegId	X15 = intRegClass[_X15Idx]
constexpr RegId	X16 = intRegClass[_X16Idx]
constexpr RegId	X17 = intRegClass[_X17Idx]
constexpr RegId	X18 = intRegClass[_X18Idx]
constexpr RegId	X19 = intRegClass[_X19Idx]
constexpr RegId	X20 = intRegClass[_X20Idx]
constexpr RegId	X21 = intRegClass[_X21Idx]
constexpr RegId	X22 = intRegClass[_X22Idx]
constexpr RegId	X23 = intRegClass[_X23Idx]
constexpr RegId	X24 = intRegClass[_X24Idx]
constexpr RegId	X25 = intRegClass[_X25Idx]
constexpr RegId	X26 = intRegClass[_X26Idx]
constexpr RegId	X27 = intRegClass[_X27Idx]
constexpr RegId	X28 = intRegClass[_X28Idx]
constexpr RegId	X29 = intRegClass[_X29Idx]
constexpr RegId	X30 = intRegClass[_X30Idx]
constexpr RegId	X31 = intRegClass[_X31Idx]
constexpr auto &	Sp = R13
constexpr auto &	Lr = R14
constexpr auto &	Pc = R15
constexpr auto &	SpSvc = R13Svc
constexpr auto &	LRSvc = R14Svc
constexpr auto &	SPMon = R13Mon
constexpr auto &	LRMon = R14Mon
constexpr auto &	SPHyp = R13Hyp
constexpr auto &	SPAbt = R13Abt
constexpr auto &	LRAbt = R14Abt
constexpr auto &	SPUnd = R13Und
constexpr auto &	LRUnd = R14Und
constexpr auto &	SPIrq = R13Irq
constexpr auto &	LRIrq = R14Irq
constexpr auto &	SPFiq = R13Fiq
constexpr auto &	LRFiq = R14Fiq
constexpr auto &	R0Usr = R0
constexpr auto &	R1Usr = R1
constexpr auto &	R2Usr = R2
constexpr auto &	R3Usr = R3
constexpr auto &	R4Usr = R4
constexpr auto &	R5Usr = R5
constexpr auto &	R6Usr = R6
constexpr auto &	R7Usr = R7
constexpr auto &	R8Usr = R8
constexpr auto &	R9Usr = R9
constexpr auto &	R10Usr = R10
constexpr auto &	R11Usr = R11
constexpr auto &	R12Usr = R12
constexpr auto &	R13Usr = R13
constexpr auto &	SPUsr = Sp
constexpr auto &	R14Usr = R14
constexpr auto &	LRUsr = Lr
constexpr auto &	R15Usr = R15
constexpr auto &	PcUsr = Pc
constexpr auto &	R0Svc = R0
constexpr auto &	R1Svc = R1
constexpr auto &	R2Svc = R2
constexpr auto &	R3Svc = R3
constexpr auto &	R4Svc = R4
constexpr auto &	R5Svc = R5
constexpr auto &	R6Svc = R6
constexpr auto &	R7Svc = R7
constexpr auto &	R8Svc = R8
constexpr auto &	R9Svc = R9
constexpr auto &	R10Svc = R10
constexpr auto &	R11Svc = R11
constexpr auto &	R12Svc = R12
constexpr auto &	PcSvc = Pc
constexpr auto &	R15Svc = R15
constexpr auto &	R0Mon = R0
constexpr auto &	R1Mon = R1
constexpr auto &	R2Mon = R2
constexpr auto &	R3Mon = R3
constexpr auto &	R4Mon = R4
constexpr auto &	R5Mon = R5
constexpr auto &	R6Mon = R6
constexpr auto &	R7Mon = R7
constexpr auto &	R8Mon = R8
constexpr auto &	R9Mon = R9
constexpr auto &	R10Mon = R10
constexpr auto &	R11Mon = R11
constexpr auto &	R12Mon = R12
constexpr auto &	PcMon = Pc
constexpr auto &	R15Mon = R15
constexpr auto &	R0Abt = R0
constexpr auto &	R1Abt = R1
constexpr auto &	R2Abt = R2
constexpr auto &	R3Abt = R3
constexpr auto &	R4Abt = R4
constexpr auto &	R5Abt = R5
constexpr auto &	R6Abt = R6
constexpr auto &	R7Abt = R7
constexpr auto &	R8Abt = R8
constexpr auto &	R9Abt = R9
constexpr auto &	R10Abt = R10
constexpr auto &	R11Abt = R11
constexpr auto &	R12Abt = R12
constexpr auto &	PcAbt = Pc
constexpr auto &	R15Abt = R15
constexpr auto &	R0Hyp = R0
constexpr auto &	R1Hyp = R1
constexpr auto &	R2Hyp = R2
constexpr auto &	R3Hyp = R3
constexpr auto &	R4Hyp = R4
constexpr auto &	R5Hyp = R5
constexpr auto &	R6Hyp = R6
constexpr auto &	R7Hyp = R7
constexpr auto &	R8Hyp = R8
constexpr auto &	R9Hyp = R9
constexpr auto &	R10Hyp = R10
constexpr auto &	R11Hyp = R11
constexpr auto &	R12Hyp = R12
constexpr auto &	LRHyp = Lr
constexpr auto &	R14Hyp = R14
constexpr auto &	PcHyp = Pc
constexpr auto &	R15Hyp = R15
constexpr auto &	R0Und = R0
constexpr auto &	R1Und = R1
constexpr auto &	R2Und = R2
constexpr auto &	R3Und = R3
constexpr auto &	R4Und = R4
constexpr auto &	R5Und = R5
constexpr auto &	R6Und = R6
constexpr auto &	R7Und = R7
constexpr auto &	R8Und = R8
constexpr auto &	R9Und = R9
constexpr auto &	R10Und = R10
constexpr auto &	R11Und = R11
constexpr auto &	R12Und = R12
constexpr auto &	PcUnd = Pc
constexpr auto &	R15Und = R15
constexpr auto &	R0Irq = R0
constexpr auto &	R1Irq = R1
constexpr auto &	R2Irq = R2
constexpr auto &	R3Irq = R3
constexpr auto &	R4Irq = R4
constexpr auto &	R5Irq = R5
constexpr auto &	R6Irq = R6
constexpr auto &	R7Irq = R7
constexpr auto &	R8Irq = R8
constexpr auto &	R9Irq = R9
constexpr auto &	R10Irq = R10
constexpr auto &	R11Irq = R11
constexpr auto &	R12Irq = R12
constexpr auto &	PcIrq = Pc
constexpr auto &	R15Irq = R15
constexpr auto &	R0Fiq = R0
constexpr auto &	R1Fiq = R1
constexpr auto &	R2Fiq = R2
constexpr auto &	R3Fiq = R3
constexpr auto &	R4Fiq = R4
constexpr auto &	R5Fiq = R5
constexpr auto &	R6Fiq = R6
constexpr auto &	R7Fiq = R7
constexpr auto &	PcFiq = Pc
constexpr auto &	R15Fiq = R15
const RegMap	Reg64Map
const RegMap	RegUsrMap
const RegMap	RegHypMap
const RegMap	RegSvcMap
const RegMap	RegMonMap
const RegMap	RegAbtMap
const RegMap	RegUndMap
const RegMap	RegIrqMap
const RegMap	RegFiqMap
static const unsigned	regsPerMode = NumRegs

Typedef Documentation

RegMap

typedef const RegId gem5::ArmISA::int_reg::RegMap[NumArchRegs]

Definition at line 435 of file int.hh.

Function Documentation

abt()

static const RegId & gem5::ArmISA::int_reg::abt ( unsigned index )

inlinestatic

Definition at line 515 of file int.hh.

References gem5::MipsISA::index, and RegAbtMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

fiq()

static const RegId & gem5::ArmISA::int_reg::fiq ( unsigned index )

inlinestatic

Definition at line 557 of file int.hh.

References gem5::MipsISA::index, and RegFiqMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

hyp()

static const RegId & gem5::ArmISA::int_reg::hyp ( unsigned index )

inlinestatic

Definition at line 473 of file int.hh.

References gem5::MipsISA::index, and RegHypMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

irq()

static const RegId & gem5::ArmISA::int_reg::irq ( unsigned index )

inlinestatic

Definition at line 543 of file int.hh.

References gem5::MipsISA::index, and RegIrqMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

mon()

static const RegId & gem5::ArmISA::int_reg::mon ( unsigned index )

inlinestatic

Definition at line 501 of file int.hh.

References gem5::MipsISA::index, and RegMonMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

regInMode()

static int gem5::ArmISA::int_reg::regInMode ( OperatingMode mode, int reg )

inlinestatic

Definition at line 566 of file int.hh.

References gem5::ArmISA::mode, gem5::X86ISA::reg, and regsPerMode.

Referenced by gem5::ArmISA::decodeMrsMsrBankedReg(), and gem5::ArmISA::MacroMemOp::MacroMemOp().

svc()

static const RegId & gem5::ArmISA::int_reg::svc ( unsigned index )

inlinestatic

Definition at line 487 of file int.hh.

References gem5::MipsISA::index, and RegSvcMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

und()

static const RegId & gem5::ArmISA::int_reg::und ( unsigned index )

inlinestatic

Definition at line 529 of file int.hh.

References gem5::MipsISA::index, and RegUndMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

usr()

static const RegId & gem5::ArmISA::int_reg::usr ( unsigned index )

inlinestatic

Definition at line 459 of file int.hh.

References gem5::MipsISA::index, and RegUsrMap.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), and gem5::ArmISA::flattenIntRegModeIndex().

x()

static RegId gem5::ArmISA::int_reg::x ( unsigned index )

inlinestatic

Definition at line 445 of file int.hh.

References gem5::MipsISA::index, and gem5::ArmISA::intRegClass.

Referenced by gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::fastmodel::FastmodelRemoteGDB::AArch64GdbRegCache::setRegs(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

Variable Documentation

Lr

auto & gem5::ArmISA::int_reg::Lr = R14

Definition at line 275 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

LRAbt

auto & gem5::ArmISA::int_reg::LRAbt = R14Abt

Definition at line 287 of file int.hh.

LRFiq

auto & gem5::ArmISA::int_reg::LRFiq = R14Fiq

Definition at line 296 of file int.hh.

LRHyp

auto & gem5::ArmISA::int_reg::LRHyp = Lr

Definition at line 384 of file int.hh.

LRIrq

auto & gem5::ArmISA::int_reg::LRIrq = R14Irq

Definition at line 293 of file int.hh.

LRMon

auto & gem5::ArmISA::int_reg::LRMon = R14Mon

Definition at line 282 of file int.hh.

LRSvc

auto & gem5::ArmISA::int_reg::LRSvc = R14Svc

Definition at line 279 of file int.hh.

LRUnd

auto & gem5::ArmISA::int_reg::LRUnd = R14Und

Definition at line 290 of file int.hh.

LRUsr

auto & gem5::ArmISA::int_reg::LRUsr = Lr

Definition at line 315 of file int.hh.

Pc

auto & gem5::ArmISA::int_reg::Pc = R15

Definition at line 276 of file int.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt(), and gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt().

PcAbt

auto & gem5::ArmISA::int_reg::PcAbt = Pc

Definition at line 367 of file int.hh.

PcFiq

auto & gem5::ArmISA::int_reg::PcFiq = Pc

Definition at line 432 of file int.hh.

PcHyp

auto & gem5::ArmISA::int_reg::PcHyp = Pc

Definition at line 386 of file int.hh.

PcIrq

auto & gem5::ArmISA::int_reg::PcIrq = Pc

Definition at line 420 of file int.hh.

PcMon

auto & gem5::ArmISA::int_reg::PcMon = Pc

Definition at line 350 of file int.hh.

PcSvc

auto & gem5::ArmISA::int_reg::PcSvc = Pc

Definition at line 333 of file int.hh.

PcUnd

auto & gem5::ArmISA::int_reg::PcUnd = Pc

Definition at line 403 of file int.hh.

PcUsr

auto & gem5::ArmISA::int_reg::PcUsr = Pc

Definition at line 317 of file int.hh.

R0

RegId gem5::ArmISA::int_reg::R0 = intRegClass[_R0Idx]

inlineconstexpr

Definition at line 186 of file int.hh.

Referenced by gem5::ArmSemihosting::call32(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::FsFreebsd::initState(), gem5::ArmISA::FsLinux::initState(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store(), and gem5::guest_abi::Result< ArmSemihosting::Abi32, ArmSemihosting::RetErrno >::store().

R0Abt

auto & gem5::ArmISA::int_reg::R0Abt = R0

Definition at line 354 of file int.hh.

R0Fiq

auto & gem5::ArmISA::int_reg::R0Fiq = R0

Definition at line 424 of file int.hh.

R0Hyp

auto & gem5::ArmISA::int_reg::R0Hyp = R0

Definition at line 371 of file int.hh.

R0Irq

auto & gem5::ArmISA::int_reg::R0Irq = R0

Definition at line 407 of file int.hh.

R0Mon

auto & gem5::ArmISA::int_reg::R0Mon = R0

Definition at line 337 of file int.hh.

R0Svc

auto & gem5::ArmISA::int_reg::R0Svc = R0

Definition at line 320 of file int.hh.

R0Und

auto & gem5::ArmISA::int_reg::R0Und = R0

Definition at line 390 of file int.hh.

R0Usr

auto & gem5::ArmISA::int_reg::R0Usr = R0

Definition at line 299 of file int.hh.

R1

RegId gem5::ArmISA::int_reg::R1 = intRegClass[_R1Idx]

Definition at line 187 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::FsFreebsd::initState(), gem5::ArmISA::FsLinux::initState(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), and gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store().

R10

RegId gem5::ArmISA::int_reg::R10 = intRegClass[_R10Idx]

Definition at line 196 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R10Abt

auto & gem5::ArmISA::int_reg::R10Abt = R10

Definition at line 364 of file int.hh.

R10Fiq

RegId gem5::ArmISA::int_reg::R10Fiq = intRegClass[_R10FiqIdx]

Definition at line 222 of file int.hh.

R10Hyp

auto & gem5::ArmISA::int_reg::R10Hyp = R10

Definition at line 381 of file int.hh.

R10Irq

auto & gem5::ArmISA::int_reg::R10Irq = R10

Definition at line 417 of file int.hh.

R10Mon

auto & gem5::ArmISA::int_reg::R10Mon = R10

Definition at line 347 of file int.hh.

R10Svc

auto & gem5::ArmISA::int_reg::R10Svc = R10

Definition at line 330 of file int.hh.

R10Und

auto & gem5::ArmISA::int_reg::R10Und = R10

Definition at line 400 of file int.hh.

R10Usr

auto & gem5::ArmISA::int_reg::R10Usr = R10

Definition at line 309 of file int.hh.

R11

RegId gem5::ArmISA::int_reg::R11 = intRegClass[_R11Idx]

Definition at line 197 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R11Abt

auto & gem5::ArmISA::int_reg::R11Abt = R11

Definition at line 365 of file int.hh.

R11Fiq

RegId gem5::ArmISA::int_reg::R11Fiq = intRegClass[_R11FiqIdx]

Definition at line 223 of file int.hh.

R11Hyp

auto & gem5::ArmISA::int_reg::R11Hyp = R11

Definition at line 382 of file int.hh.

R11Irq

auto & gem5::ArmISA::int_reg::R11Irq = R11

Definition at line 418 of file int.hh.

R11Mon

auto & gem5::ArmISA::int_reg::R11Mon = R11

Definition at line 348 of file int.hh.

R11Svc

auto & gem5::ArmISA::int_reg::R11Svc = R11

Definition at line 331 of file int.hh.

R11Und

auto & gem5::ArmISA::int_reg::R11Und = R11

Definition at line 401 of file int.hh.

R11Usr

auto & gem5::ArmISA::int_reg::R11Usr = R11

Definition at line 310 of file int.hh.

R12

RegId gem5::ArmISA::int_reg::R12 = intRegClass[_R12Idx]

Definition at line 198 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R12Abt

auto & gem5::ArmISA::int_reg::R12Abt = R12

Definition at line 366 of file int.hh.

R12Fiq

RegId gem5::ArmISA::int_reg::R12Fiq = intRegClass[_R12FiqIdx]

Definition at line 224 of file int.hh.

R12Hyp

auto & gem5::ArmISA::int_reg::R12Hyp = R12

Definition at line 383 of file int.hh.

R12Irq

auto & gem5::ArmISA::int_reg::R12Irq = R12

Definition at line 419 of file int.hh.

R12Mon

auto & gem5::ArmISA::int_reg::R12Mon = R12

Definition at line 349 of file int.hh.

R12Svc

auto & gem5::ArmISA::int_reg::R12Svc = R12

Definition at line 332 of file int.hh.

R12Und

auto & gem5::ArmISA::int_reg::R12Und = R12

Definition at line 402 of file int.hh.

R12Usr

auto & gem5::ArmISA::int_reg::R12Usr = R12

Definition at line 311 of file int.hh.

R13

RegId gem5::ArmISA::int_reg::R13 = intRegClass[_R13Idx]

Definition at line 199 of file int.hh.

R13Abt

RegId gem5::ArmISA::int_reg::R13Abt = intRegClass[_R13AbtIdx]

Definition at line 211 of file int.hh.

R13Fiq

RegId gem5::ArmISA::int_reg::R13Fiq = intRegClass[_R13FiqIdx]

Definition at line 225 of file int.hh.

R13Hyp

RegId gem5::ArmISA::int_reg::R13Hyp = intRegClass[_R13HypIdx]

Definition at line 209 of file int.hh.

R13Irq

RegId gem5::ArmISA::int_reg::R13Irq = intRegClass[_R13IrqIdx]

Definition at line 217 of file int.hh.

R13Mon

RegId gem5::ArmISA::int_reg::R13Mon = intRegClass[_R13MonIdx]

Definition at line 206 of file int.hh.

Referenced by gem5::fastmodel::CortexA76TC::readIntRegFlat(), and gem5::fastmodel::CortexA76TC::setIntRegFlat().

R13Svc

RegId gem5::ArmISA::int_reg::R13Svc = intRegClass[_R13SvcIdx]

Definition at line 203 of file int.hh.

R13Und

RegId gem5::ArmISA::int_reg::R13Und = intRegClass[_R13UndIdx]

Definition at line 214 of file int.hh.

R13Usr

auto & gem5::ArmISA::int_reg::R13Usr = R13

Definition at line 312 of file int.hh.

R14

RegId gem5::ArmISA::int_reg::R14 = intRegClass[_R14Idx]

Definition at line 200 of file int.hh.

R14Abt

RegId gem5::ArmISA::int_reg::R14Abt = intRegClass[_R14AbtIdx]

Definition at line 212 of file int.hh.

R14Fiq

RegId gem5::ArmISA::int_reg::R14Fiq = intRegClass[_R14FiqIdx]

Definition at line 226 of file int.hh.

R14Hyp

auto & gem5::ArmISA::int_reg::R14Hyp = R14

Definition at line 385 of file int.hh.

R14Irq

RegId gem5::ArmISA::int_reg::R14Irq = intRegClass[_R14IrqIdx]

Definition at line 218 of file int.hh.

R14Mon

RegId gem5::ArmISA::int_reg::R14Mon = intRegClass[_R14MonIdx]

Definition at line 207 of file int.hh.

Referenced by gem5::fastmodel::CortexA76TC::readIntRegFlat(), and gem5::fastmodel::CortexA76TC::setIntRegFlat().

R14Svc

RegId gem5::ArmISA::int_reg::R14Svc = intRegClass[_R14SvcIdx]

Definition at line 204 of file int.hh.

R14Und

RegId gem5::ArmISA::int_reg::R14Und = intRegClass[_R14UndIdx]

Definition at line 215 of file int.hh.

R14Usr

auto & gem5::ArmISA::int_reg::R14Usr = R14

Definition at line 314 of file int.hh.

R15

RegId gem5::ArmISA::int_reg::R15 = intRegClass[_R15Idx]

Definition at line 201 of file int.hh.

R15Abt

auto & gem5::ArmISA::int_reg::R15Abt = R15

Definition at line 368 of file int.hh.

R15Fiq

auto & gem5::ArmISA::int_reg::R15Fiq = R15

Definition at line 433 of file int.hh.

R15Hyp

auto & gem5::ArmISA::int_reg::R15Hyp = R15

Definition at line 387 of file int.hh.

R15Irq

auto & gem5::ArmISA::int_reg::R15Irq = R15

Definition at line 421 of file int.hh.

R15Mon

auto & gem5::ArmISA::int_reg::R15Mon = R15

Definition at line 351 of file int.hh.

R15Svc

auto & gem5::ArmISA::int_reg::R15Svc = R15

Definition at line 334 of file int.hh.

R15Und

auto & gem5::ArmISA::int_reg::R15Und = R15

Definition at line 404 of file int.hh.

R15Usr

auto & gem5::ArmISA::int_reg::R15Usr = R15

Definition at line 316 of file int.hh.

R1Abt

auto & gem5::ArmISA::int_reg::R1Abt = R1

Definition at line 355 of file int.hh.

R1Fiq

auto & gem5::ArmISA::int_reg::R1Fiq = R1

Definition at line 425 of file int.hh.

R1Hyp

auto & gem5::ArmISA::int_reg::R1Hyp = R1

Definition at line 372 of file int.hh.

R1Irq

auto & gem5::ArmISA::int_reg::R1Irq = R1

Definition at line 408 of file int.hh.

R1Mon

auto & gem5::ArmISA::int_reg::R1Mon = R1

Definition at line 338 of file int.hh.

R1Svc

auto & gem5::ArmISA::int_reg::R1Svc = R1

Definition at line 321 of file int.hh.

R1Und

auto & gem5::ArmISA::int_reg::R1Und = R1

Definition at line 391 of file int.hh.

R1Usr

auto & gem5::ArmISA::int_reg::R1Usr = R1

Definition at line 300 of file int.hh.

R2

RegId gem5::ArmISA::int_reg::R2 = intRegClass[_R2Idx]

Definition at line 188 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::DumpStats::getTaskDetails(), gem5::ArmISA::FsFreebsd::initState(), gem5::ArmISA::FsLinux::initState(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R2Abt

auto & gem5::ArmISA::int_reg::R2Abt = R2

Definition at line 356 of file int.hh.

R2Fiq

auto & gem5::ArmISA::int_reg::R2Fiq = R2

Definition at line 426 of file int.hh.

R2Hyp

auto & gem5::ArmISA::int_reg::R2Hyp = R2

Definition at line 373 of file int.hh.

R2Irq

auto & gem5::ArmISA::int_reg::R2Irq = R2

Definition at line 409 of file int.hh.

R2Mon

auto & gem5::ArmISA::int_reg::R2Mon = R2

Definition at line 339 of file int.hh.

R2Svc

auto & gem5::ArmISA::int_reg::R2Svc = R2

Definition at line 322 of file int.hh.

R2Und

auto & gem5::ArmISA::int_reg::R2Und = R2

Definition at line 392 of file int.hh.

R2Usr

auto & gem5::ArmISA::int_reg::R2Usr = R2

Definition at line 301 of file int.hh.

R3

RegId gem5::ArmISA::int_reg::R3 = intRegClass[_R3Idx]

Definition at line 189 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::FsWorkload::initState(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R3Abt

auto & gem5::ArmISA::int_reg::R3Abt = R3

Definition at line 357 of file int.hh.

R3Fiq

auto & gem5::ArmISA::int_reg::R3Fiq = R3

Definition at line 427 of file int.hh.

R3Hyp

auto & gem5::ArmISA::int_reg::R3Hyp = R3

Definition at line 374 of file int.hh.

R3Irq

auto & gem5::ArmISA::int_reg::R3Irq = R3

Definition at line 410 of file int.hh.

R3Mon

auto & gem5::ArmISA::int_reg::R3Mon = R3

Definition at line 340 of file int.hh.

R3Svc

auto & gem5::ArmISA::int_reg::R3Svc = R3

Definition at line 323 of file int.hh.

R3Und

auto & gem5::ArmISA::int_reg::R3Und = R3

Definition at line 393 of file int.hh.

R3Usr

auto & gem5::ArmISA::int_reg::R3Usr = R3

Definition at line 302 of file int.hh.

R4

RegId gem5::ArmISA::int_reg::R4 = intRegClass[_R4Idx]

Definition at line 190 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::FsWorkload::initState(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R4Abt

auto & gem5::ArmISA::int_reg::R4Abt = R4

Definition at line 358 of file int.hh.

R4Fiq

auto & gem5::ArmISA::int_reg::R4Fiq = R4

Definition at line 428 of file int.hh.

R4Hyp

auto & gem5::ArmISA::int_reg::R4Hyp = R4

Definition at line 375 of file int.hh.

R4Irq

auto & gem5::ArmISA::int_reg::R4Irq = R4

Definition at line 411 of file int.hh.

R4Mon

auto & gem5::ArmISA::int_reg::R4Mon = R4

Definition at line 341 of file int.hh.

R4Svc

auto & gem5::ArmISA::int_reg::R4Svc = R4

Definition at line 324 of file int.hh.

R4Und

auto & gem5::ArmISA::int_reg::R4Und = R4

Definition at line 394 of file int.hh.

R4Usr

auto & gem5::ArmISA::int_reg::R4Usr = R4

Definition at line 303 of file int.hh.

R5

RegId gem5::ArmISA::int_reg::R5 = intRegClass[_R5Idx]

Definition at line 191 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::FsWorkload::initState(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R5Abt

auto & gem5::ArmISA::int_reg::R5Abt = R5

Definition at line 359 of file int.hh.

R5Fiq

auto & gem5::ArmISA::int_reg::R5Fiq = R5

Definition at line 429 of file int.hh.

R5Hyp

auto & gem5::ArmISA::int_reg::R5Hyp = R5

Definition at line 376 of file int.hh.

R5Irq

auto & gem5::ArmISA::int_reg::R5Irq = R5

Definition at line 412 of file int.hh.

R5Mon

auto & gem5::ArmISA::int_reg::R5Mon = R5

Definition at line 342 of file int.hh.

R5Svc

auto & gem5::ArmISA::int_reg::R5Svc = R5

Definition at line 325 of file int.hh.

R5Und

auto & gem5::ArmISA::int_reg::R5Und = R5

Definition at line 395 of file int.hh.

R5Usr

auto & gem5::ArmISA::int_reg::R5Usr = R5

Definition at line 304 of file int.hh.

R6

RegId gem5::ArmISA::int_reg::R6 = intRegClass[_R6Idx]

Definition at line 192 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R6Abt

auto & gem5::ArmISA::int_reg::R6Abt = R6

Definition at line 360 of file int.hh.

R6Fiq

auto & gem5::ArmISA::int_reg::R6Fiq = R6

Definition at line 430 of file int.hh.

R6Hyp

auto & gem5::ArmISA::int_reg::R6Hyp = R6

Definition at line 377 of file int.hh.

R6Irq

auto & gem5::ArmISA::int_reg::R6Irq = R6

Definition at line 413 of file int.hh.

R6Mon

auto & gem5::ArmISA::int_reg::R6Mon = R6

Definition at line 343 of file int.hh.

R6Svc

auto & gem5::ArmISA::int_reg::R6Svc = R6

Definition at line 326 of file int.hh.

R6Und

auto & gem5::ArmISA::int_reg::R6Und = R6

Definition at line 396 of file int.hh.

R6Usr

auto & gem5::ArmISA::int_reg::R6Usr = R6

Definition at line 305 of file int.hh.

R7

RegId gem5::ArmISA::int_reg::R7 = intRegClass[_R7Idx]

Definition at line 193 of file int.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), gem5::ArmISA::EmuFreebsd::syscall(), and gem5::ArmISA::EmuLinux::syscall().

R7Abt

auto & gem5::ArmISA::int_reg::R7Abt = R7

Definition at line 361 of file int.hh.

R7Fiq

auto & gem5::ArmISA::int_reg::R7Fiq = R7

Definition at line 431 of file int.hh.

R7Hyp

auto & gem5::ArmISA::int_reg::R7Hyp = R7

Definition at line 378 of file int.hh.

R7Irq

auto & gem5::ArmISA::int_reg::R7Irq = R7

Definition at line 414 of file int.hh.

R7Mon

auto & gem5::ArmISA::int_reg::R7Mon = R7

Definition at line 344 of file int.hh.

R7Svc

auto & gem5::ArmISA::int_reg::R7Svc = R7

Definition at line 327 of file int.hh.

R7Und

auto & gem5::ArmISA::int_reg::R7Und = R7

Definition at line 397 of file int.hh.

R7Usr

auto & gem5::ArmISA::int_reg::R7Usr = R7

Definition at line 306 of file int.hh.

R8

RegId gem5::ArmISA::int_reg::R8 = intRegClass[_R8Idx]

Definition at line 194 of file int.hh.

Referenced by gem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >::get(), gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R8Abt

auto & gem5::ArmISA::int_reg::R8Abt = R8

Definition at line 362 of file int.hh.

R8Fiq

RegId gem5::ArmISA::int_reg::R8Fiq = intRegClass[_R8FiqIdx]

Definition at line 220 of file int.hh.

R8Hyp

auto & gem5::ArmISA::int_reg::R8Hyp = R8

Definition at line 379 of file int.hh.

R8Irq

auto & gem5::ArmISA::int_reg::R8Irq = R8

Definition at line 415 of file int.hh.

R8Mon

auto & gem5::ArmISA::int_reg::R8Mon = R8

Definition at line 345 of file int.hh.

R8Svc

auto & gem5::ArmISA::int_reg::R8Svc = R8

Definition at line 328 of file int.hh.

R8Und

auto & gem5::ArmISA::int_reg::R8Und = R8

Definition at line 398 of file int.hh.

R8Usr

auto & gem5::ArmISA::int_reg::R8Usr = R8

Definition at line 307 of file int.hh.

R9

RegId gem5::ArmISA::int_reg::R9 = intRegClass[_R9Idx]

Definition at line 195 of file int.hh.

Referenced by gem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >::get(), gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

R9Abt

auto & gem5::ArmISA::int_reg::R9Abt = R9

Definition at line 363 of file int.hh.

R9Fiq

RegId gem5::ArmISA::int_reg::R9Fiq = intRegClass[_R9FiqIdx]

Definition at line 221 of file int.hh.

R9Hyp

auto & gem5::ArmISA::int_reg::R9Hyp = R9

Definition at line 380 of file int.hh.

R9Irq

auto & gem5::ArmISA::int_reg::R9Irq = R9

Definition at line 416 of file int.hh.

R9Mon

auto & gem5::ArmISA::int_reg::R9Mon = R9

Definition at line 346 of file int.hh.

R9Svc

auto & gem5::ArmISA::int_reg::R9Svc = R9

Definition at line 329 of file int.hh.

R9Und

auto & gem5::ArmISA::int_reg::R9Und = R9

Definition at line 399 of file int.hh.

R9Usr

auto & gem5::ArmISA::int_reg::R9Usr = R9

Definition at line 308 of file int.hh.

Reg64Map

const RegMap gem5::ArmISA::int_reg::Reg64Map

Initial value:

= {
    R0,     R1,     R2,     R3,     R4,     R5,     R6,     R7,
    R8Usr,  R9Usr,  R10Usr, R11Usr, R12Usr, R13Usr, R14Usr, R13Hyp,
    R14Irq, R13Irq, R14Svc, R13Svc, R14Abt, R13Abt, R14Und, R13Und,
    R8Fiq,  R9Fiq,  R10Fiq, R11Fiq, R12Fiq, R13Fiq, R14Fiq, Zero
}

Definition at line 437 of file int.hh.

Referenced by gem5::ArmISA::ISA::updateRegMap().

RegAbtMap

const RegMap gem5::ArmISA::int_reg::RegAbtMap

Initial value:

= {
    R0Abt,  R1Abt,  R2Abt,  R3Abt,  R4Abt,  R5Abt,  R6Abt,  R7Abt,
    R8Abt,  R9Abt,  R10Abt, R11Abt, R12Abt, R13Abt, R14Abt, R15Abt,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 507 of file int.hh.

Referenced by abt(), and gem5::ArmISA::ISA::updateRegMap().

RegFiqMap

const RegMap gem5::ArmISA::int_reg::RegFiqMap

Initial value:

= {
    R0Fiq,  R1Fiq,  R2Fiq,  R3Fiq,  R4Fiq,  R5Fiq,  R6Fiq,  R7Fiq,
    R8Fiq,  R9Fiq,  R10Fiq, R11Fiq, R12Fiq, R13Fiq, R14Fiq, R15Fiq,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 549 of file int.hh.

Referenced by fiq(), and gem5::ArmISA::ISA::updateRegMap().

RegHypMap

const RegMap gem5::ArmISA::int_reg::RegHypMap

Initial value:

= {
    R0Hyp,  R1Hyp,  R2Hyp,  R3Hyp,  R4Hyp,  R5Hyp,  R6Hyp,  R7Hyp,
    R8Hyp,  R9Hyp,  R10Hyp, R11Hyp, R12Hyp, R13Hyp, R14Hyp, R15Hyp,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 465 of file int.hh.

Referenced by hyp(), and gem5::ArmISA::ISA::updateRegMap().

RegIrqMap

const RegMap gem5::ArmISA::int_reg::RegIrqMap

Initial value:

= {
    R0Irq,  R1Irq,  R2Irq,  R3Irq,  R4Irq,  R5Irq,  R6Irq,  R7Irq,
    R8Irq,  R9Irq,  R10Irq, R11Irq, R12Irq, R13Irq, R14Irq, R15Irq,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 535 of file int.hh.

Referenced by irq(), and gem5::ArmISA::ISA::updateRegMap().

RegMonMap

const RegMap gem5::ArmISA::int_reg::RegMonMap

Initial value:

= {
    R0Mon,  R1Mon,  R2Mon,  R3Mon,  R4Mon,  R5Mon,  R6Mon,  R7Mon,
    R8Mon,  R9Mon,  R10Mon, R11Mon, R12Mon, R13Mon, R14Mon, R15Mon,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 493 of file int.hh.

Referenced by mon(), and gem5::ArmISA::ISA::updateRegMap().

regsPerMode

const unsigned gem5::ArmISA::int_reg::regsPerMode = NumRegs

static

Definition at line 563 of file int.hh.

Referenced by gem5::ArmISA::flattenIntRegModeIndex(), and regInMode().

RegSvcMap

const RegMap gem5::ArmISA::int_reg::RegSvcMap

Initial value:

= {
    R0Svc,  R1Svc,  R2Svc,  R3Svc,  R4Svc,  R5Svc,  R6Svc,  R7Svc,
    R8Svc,  R9Svc,  R10Svc, R11Svc, R12Svc, R13Svc, R14Svc, R15Svc,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 479 of file int.hh.

Referenced by svc(), and gem5::ArmISA::ISA::updateRegMap().

RegUndMap

const RegMap gem5::ArmISA::int_reg::RegUndMap

Initial value:

= {
    R0Und,  R1Und,  R2Und,  R3Und,  R4Und,  R5Und,  R6Und,  R7Und,
    R8Und,  R9Und,  R10Und, R11Und, R12Und, R13Und, R14Und, R15Und,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 521 of file int.hh.

Referenced by und(), and gem5::ArmISA::ISA::updateRegMap().

RegUsrMap

const RegMap gem5::ArmISA::int_reg::RegUsrMap

Initial value:

= {
    R0Usr,  R1Usr,  R2Usr,  R3Usr,  R4Usr,  R5Usr,  R6Usr,  R7Usr,
    R8Usr,  R9Usr,  R10Usr, R11Usr, R12Usr, R13Usr, R14Usr, R15Usr,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,
    Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero,   Zero
}

Definition at line 451 of file int.hh.

Referenced by gem5::ArmISA::ISA::updateRegMap(), and usr().

Sp

auto& gem5::ArmISA::int_reg::Sp = R13

inlineconstexpr

Definition at line 274 of file int.hh.

Referenced by gem5::ArmLinux32::archClone(), gem5::MipsProcess::argsInit(), gem5::ArmISA::SrsOp::generateDisassembly(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmProcess32::initState(), gem5::ArmISA::MacroMemOp::MacroMemOp(), and gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs().

Sp0

RegId gem5::ArmISA::int_reg::Sp0 = intRegClass[_Sp0Idx]

Definition at line 233 of file int.hh.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace(), gem5::ArmISA::IntRegClassOps::flatten(), gem5::ArmProcess64::initState(), gem5::ArmISA::ISA::readMiscReg(), and gem5::ArmISA::ISA::setMiscReg().

Sp1

RegId gem5::ArmISA::int_reg::Sp1 = intRegClass[_Sp1Idx]

Definition at line 234 of file int.hh.

Referenced by gem5::ArmISA::IntRegClassOps::flatten(), gem5::ArmISA::ISA::readMiscReg(), and gem5::ArmISA::ISA::setMiscReg().

Sp2

RegId gem5::ArmISA::int_reg::Sp2 = intRegClass[_Sp2Idx]

Definition at line 235 of file int.hh.

Referenced by gem5::ArmISA::IntRegClassOps::flatten(), gem5::ArmISA::ISA::readMiscReg(), and gem5::ArmISA::ISA::setMiscReg().

Sp3

RegId gem5::ArmISA::int_reg::Sp3 = intRegClass[_Sp3Idx]

Definition at line 236 of file int.hh.

Referenced by gem5::ArmISA::IntRegClassOps::flatten().

SPAbt

auto & gem5::ArmISA::int_reg::SPAbt = R13Abt

Definition at line 286 of file int.hh.

SPFiq

auto & gem5::ArmISA::int_reg::SPFiq = R13Fiq

Definition at line 295 of file int.hh.

SPHyp

auto & gem5::ArmISA::int_reg::SPHyp = R13Hyp

Definition at line 284 of file int.hh.

SPIrq

auto & gem5::ArmISA::int_reg::SPIrq = R13Irq

Definition at line 292 of file int.hh.

SPMon

auto & gem5::ArmISA::int_reg::SPMon = R13Mon

Definition at line 281 of file int.hh.

SpSvc

auto & gem5::ArmISA::int_reg::SpSvc = R13Svc

Definition at line 278 of file int.hh.

SPUnd

auto & gem5::ArmISA::int_reg::SPUnd = R13Und

Definition at line 289 of file int.hh.

SPUsr

auto & gem5::ArmISA::int_reg::SPUsr = Sp

Definition at line 313 of file int.hh.

Spx

RegId gem5::ArmISA::int_reg::Spx = intRegClass[_SpxIdx]

Definition at line 238 of file int.hh.

Referenced by gem5::ArmISA::couldBeSP(), gem5::ArmISA::IntRegClassOps::flatten(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::isSP(), gem5::ArmISA::makeSP(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), and gem5::fastmodel::FastmodelRemoteGDB::AArch64GdbRegCache::setRegs().

Ureg0

RegId gem5::ArmISA::int_reg::Ureg0 = intRegClass[_Ureg0Idx]

Definition at line 229 of file int.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::PairMemOp::PairMemOp(), and gem5::ArmISA::ArmStaticInst::printIntReg().

Ureg1

RegId gem5::ArmISA::int_reg::Ureg1 = intRegClass[_Ureg1Idx]

Definition at line 230 of file int.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp().

Ureg2

RegId gem5::ArmISA::int_reg::Ureg2 = intRegClass[_Ureg2Idx]

Definition at line 231 of file int.hh.

X0

RegId gem5::ArmISA::int_reg::X0 = intRegClass[_X0Idx]

Definition at line 240 of file int.hh.

Referenced by gem5::ArmSemihosting::call64(), gem5::ArmISA::FsLinux::initState(), gem5::guest_abi::Result< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> >::store(), gem5::guest_abi::Result< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::store(), and gem5::guest_abi::Result< ArmSemihosting::Abi64, ArmSemihosting::RetErrno >::store().

X1

RegId gem5::ArmISA::int_reg::X1 = intRegClass[_X1Idx]

Definition at line 241 of file int.hh.

Referenced by gem5::ArmISA::DumpStats64::getTaskDetails(), and gem5::guest_abi::Result< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> >::store().

X10

RegId gem5::ArmISA::int_reg::X10 = intRegClass[_X10Idx]

Definition at line 250 of file int.hh.

X11

RegId gem5::ArmISA::int_reg::X11 = intRegClass[_X11Idx]

Definition at line 251 of file int.hh.

X12

RegId gem5::ArmISA::int_reg::X12 = intRegClass[_X12Idx]

Definition at line 252 of file int.hh.

X13

RegId gem5::ArmISA::int_reg::X13 = intRegClass[_X13Idx]

Definition at line 253 of file int.hh.

X14

RegId gem5::ArmISA::int_reg::X14 = intRegClass[_X14Idx]

Definition at line 254 of file int.hh.

X15

RegId gem5::ArmISA::int_reg::X15 = intRegClass[_X15Idx]

Definition at line 255 of file int.hh.

X16

RegId gem5::ArmISA::int_reg::X16 = intRegClass[_X16Idx]

Definition at line 256 of file int.hh.

X17

RegId gem5::ArmISA::int_reg::X17 = intRegClass[_X17Idx]

Definition at line 257 of file int.hh.

X18

RegId gem5::ArmISA::int_reg::X18 = intRegClass[_X18Idx]

Definition at line 258 of file int.hh.

X19

RegId gem5::ArmISA::int_reg::X19 = intRegClass[_X19Idx]

Definition at line 259 of file int.hh.

X2

RegId gem5::ArmISA::int_reg::X2 = intRegClass[_X2Idx]

Definition at line 242 of file int.hh.

X20

RegId gem5::ArmISA::int_reg::X20 = intRegClass[_X20Idx]

Definition at line 260 of file int.hh.

X21

RegId gem5::ArmISA::int_reg::X21 = intRegClass[_X21Idx]

Definition at line 261 of file int.hh.

X22

RegId gem5::ArmISA::int_reg::X22 = intRegClass[_X22Idx]

Definition at line 262 of file int.hh.

X23

RegId gem5::ArmISA::int_reg::X23 = intRegClass[_X23Idx]

Definition at line 263 of file int.hh.

X24

RegId gem5::ArmISA::int_reg::X24 = intRegClass[_X24Idx]

Definition at line 264 of file int.hh.

X25

RegId gem5::ArmISA::int_reg::X25 = intRegClass[_X25Idx]

Definition at line 265 of file int.hh.

X26

RegId gem5::ArmISA::int_reg::X26 = intRegClass[_X26Idx]

Definition at line 266 of file int.hh.

X27

RegId gem5::ArmISA::int_reg::X27 = intRegClass[_X27Idx]

Definition at line 267 of file int.hh.

X28

RegId gem5::ArmISA::int_reg::X28 = intRegClass[_X28Idx]

Definition at line 268 of file int.hh.

X29

RegId gem5::ArmISA::int_reg::X29 = intRegClass[_X29Idx]

Definition at line 269 of file int.hh.

X3

RegId gem5::ArmISA::int_reg::X3 = intRegClass[_X3Idx]

Definition at line 243 of file int.hh.

X30

RegId gem5::ArmISA::int_reg::X30 = intRegClass[_X30Idx]

Definition at line 270 of file int.hh.

Referenced by gem5::ArmISA::BranchRet64::generateDisassembly(), gem5::ArmISA::BranchRetA64::generateDisassembly(), and gem5::ArmISA::SkipFunc::returnFromFuncIn().

X31

RegId gem5::ArmISA::int_reg::X31 = intRegClass[_X31Idx]

Definition at line 271 of file int.hh.

Referenced by gem5::ArmISA::couldBeSP(), gem5::ArmISA::couldBeZero(), gem5::ArmISA::makeSP(), gem5::ArmISA::makeZero(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

X4

RegId gem5::ArmISA::int_reg::X4 = intRegClass[_X4Idx]

Definition at line 244 of file int.hh.

X5

RegId gem5::ArmISA::int_reg::X5 = intRegClass[_X5Idx]

Definition at line 245 of file int.hh.

Referenced by gem5::ArmISA::FsLinux::initState().

X6

RegId gem5::ArmISA::int_reg::X6 = intRegClass[_X6Idx]

Definition at line 246 of file int.hh.

X7

RegId gem5::ArmISA::int_reg::X7 = intRegClass[_X7Idx]

Definition at line 247 of file int.hh.

X8

RegId gem5::ArmISA::int_reg::X8 = intRegClass[_X8Idx]

Definition at line 248 of file int.hh.

Referenced by gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::ArmISA::EmuFreebsd::syscall(), and gem5::ArmISA::EmuLinux::syscall().

X9

RegId gem5::ArmISA::int_reg::X9 = intRegClass[_X9Idx]

Definition at line 249 of file int.hh.

Zero

RegId gem5::ArmISA::int_reg::Zero = intRegClass[_ZeroIdx]

Definition at line 228 of file int.hh.

Referenced by gem5::ArmISA::couldBeZero(), gem5::ArmISA::decodeMrsMsrBankedIntRegIndex(), gem5::ArmISA::DataImmOp::generateDisassembly(), gem5::ArmISA::DataRegOp::generateDisassembly(), gem5::ArmISA::DataXERegOp::generateDisassembly(), gem5::ArmISA::DataXImmOp::generateDisassembly(), gem5::ArmISA::DataXSRegOp::generateDisassembly(), gem5::RegImmRegShiftOp::generateDisassembly(), gem5::ArmISA::isZero(), gem5::ArmISA::makeZero(), gem5::ArmISA::ArmStaticInst::printDataInst(), and gem5::ArmISA::ArmStaticInst::printShiftOperand().