reg_abi.hh

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#ifndef __ARCH_ARM_REG_ABI_HH__
#define __ARCH_ARM_REG_ABI_HH__
 
#include <vector>
 
#include "base/logging.hh"
#include "sim/pseudo_inst.hh"
#include "sim/syscall_abi.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
struct RegABI32 : public GenericSyscallABI32
{
    static const std::vector<RegId> ArgumentRegs;
};
 
struct RegABI64 : public GenericSyscallABI64
{
    static const std::vector<RegId> ArgumentRegs;
};
 
} // namespace ArmISA
 
namespace guest_abi
{
 
template <typename ABI, typename Arg>
struct Argument<ABI, Arg,
    typename std::enable_if_t<
        std::is_base_of_v<ArmISA::RegABI32, ABI> &&
        std::is_integral_v<Arg> &&
        ABI::template IsWideV<Arg>>>
{
    static Arg
    get(ThreadContext *tc, typename ABI::State &state)
    {
        // 64 bit arguments are passed starting in an even register.
        if (state % 2)
            state++;
        panic_if(state + 1 >= ABI::ArgumentRegs.size(),
                "Ran out of syscall argument registers.");
        auto low = ABI::ArgumentRegs[state++];
        auto high = ABI::ArgumentRegs[state++];
        return (Arg)ABI::mergeRegs(tc, low, high);
    }
};
 
template <>
struct Argument<ArmISA::RegABI32, pseudo_inst::GuestAddr>
{
    using ABI = ArmISA::RegABI32;
    using Arg = pseudo_inst::GuestAddr;
 
    static Arg
    get(ThreadContext *tc, typename ABI::State &state)
    {
        panic_if(state + 1 >= ABI::ArgumentRegs.size(),
                "Ran out of syscall argument registers.");
        return (Arg)bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
    }
};
 
} // namespace guest_abi
} // namespace gem5
 
#endif // __ARCH_ARM_REG_ABI_HH__