gem5 v24.0.0.0
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bs.hh
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1/*
2 * Copyright (c) 2023 Google LLC
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4 *
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27 */
28
29#ifndef __ARCH_RISCV_BS_INST_HH__
30#define __ARCH_RISCV_BS_INST_HH__
31
33
34namespace gem5
35{
36
37namespace RiscvISA
38{
39
40class BSOp : public RiscvStaticInst
41{
42 protected:
43 uint8_t bs;
44
45 BSOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
46 : RiscvStaticInst(mnem, _machInst, __opClass), bs(0)
47 {}
48
49 std::string generateDisassembly(
50 Addr pc, const loader::SymbolTable *symtab) const override;
51};
52
53} // namespace RiscvISA
54} // namespace gem5
55
56#endif // __ARCH_RISCV_BS_INST_HH__
BSOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition bs.hh:45
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition bs.cc:43
Base class for all RISC-V static instructions.
Bitfield< 4 > pc
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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