gem5  v21.2.1.1
static_inst.hh
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29 
30 #ifndef __ARCH_RISCV_STATIC_INST_HH__
31 #define __ARCH_RISCV_STATIC_INST_HH__
32 
33 #include <string>
34 
35 #include "arch/riscv/pcstate.hh"
36 #include "arch/riscv/types.hh"
37 #include "cpu/exec_context.hh"
38 #include "cpu/static_inst.hh"
39 #include "cpu/thread_context.hh"
40 #include "mem/packet.hh"
41 
42 namespace gem5
43 {
44 
45 namespace RiscvISA
46 {
47 
52 {
53  protected:
54  RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst,
55  OpClass __opClass) :
56  StaticInst(_mnemonic, __opClass), machInst(_machInst)
57  {}
58 
59  public:
61 
62  void
63  advancePC(PCStateBase &pc) const override
64  {
65  pc.as<PCState>().advance();
66  }
67 
68  void
69  advancePC(ThreadContext *tc) const override
70  {
71  PCState pc = tc->pcState().as<PCState>();
72  pc.advance();
73  tc->pcState(pc);
74  }
75 
76  std::unique_ptr<PCStateBase>
77  buildRetPC(const PCStateBase &cur_pc,
78  const PCStateBase &call_pc) const override
79  {
80  PCStateBase *ret_pc_ptr = call_pc.clone();
81  auto &ret_pc = ret_pc_ptr->as<PCState>();
82  ret_pc.advance();
83  ret_pc.pc(cur_pc.as<PCState>().npc());
84  return std::unique_ptr<PCStateBase>{ret_pc_ptr};
85  }
86 
87  size_t
88  asBytes(void *buf, size_t size) override
89  {
90  return simpleAsBytes(buf, size, machInst);
91  }
92 };
93 
98 {
99  protected:
101 
102  RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
103  OpClass __opClass) :
104  RiscvStaticInst(mnem, _machInst, __opClass)
105  {
106  flags[IsMacroop] = true;
107  }
108 
109  ~RiscvMacroInst() { microops.clear(); }
110 
112  fetchMicroop(MicroPC upc) const override
113  {
114  return microops[upc];
115  }
116 
117  Fault
118  initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
119  {
120  panic("Tried to execute a macroop directly!\n");
121  }
122 
123  Fault
125  Trace::InstRecord *traceData) const override
126  {
127  panic("Tried to execute a macroop directly!\n");
128  }
129 
130  Fault
131  execute(ExecContext *xc, Trace::InstRecord *traceData) const override
132  {
133  panic("Tried to execute a macroop directly!\n");
134  }
135 };
136 
141 {
142  protected:
143  RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
144  OpClass __opClass) :
145  RiscvStaticInst(mnem, _machInst, __opClass)
146  {
147  flags[IsMicroop] = true;
148  }
149 
150  void advancePC(PCStateBase &pcState) const override;
151  void advancePC(ThreadContext *tc) const override;
152 };
153 
154 } // namespace RiscvISA
155 } // namespace gem5
156 
157 #endif // __ARCH_RISCV_STATIC_INST_HH__
gem5::RiscvISA::RiscvMacroInst::completeAcc
Fault completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: static_inst.hh:124
gem5::RiscvISA::RiscvStaticInst::buildRetPC
std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
Definition: static_inst.hh:77
gem5::RiscvISA::RiscvMicroInst::RiscvMicroInst
RiscvMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:143
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:51
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::RiscvISA::RiscvMacroInst::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC upc) const override
Return the microop that goes with a particular micropc.
Definition: static_inst.hh:112
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:377
gem5::RiscvISA::RiscvMacroInst
Base class for all RISC-V Macroops.
Definition: static_inst.hh:97
gem5::RiscvISA::RiscvMacroInst::initiateAcc
Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: static_inst.hh:118
gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst
RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:54
gem5::RiscvISA::RiscvMacroInst::RiscvMacroInst
RiscvMacroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:102
std::vector
STL vector class.
Definition: stl.hh:37
gem5::RiscvISA::RiscvMicroInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: static_inst.cc:43
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
pcstate.hh
gem5::RiscvISA::RiscvStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:60
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::RiscvISA::RiscvStaticInst::advancePC
void advancePC(PCStateBase &pc) const override
Definition: static_inst.hh:63
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::GenericISA::PCStateWithNext::npc
Addr npc() const
Definition: pcstate.hh:266
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RiscvISA::RiscvStaticInst::asBytes
size_t asBytes(void *buf, size_t size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:88
types.hh
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:102
static_inst.hh
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::RiscvISA::RiscvMacroInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: static_inst.hh:131
exec_context.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::RiscvISA::RiscvMicroInst
Base class for all RISC-V Microops.
Definition: static_inst.hh:140
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RiscvISA::RiscvStaticInst::advancePC
void advancePC(ThreadContext *tc) const override
Definition: static_inst.hh:69
gem5::RiscvISA::RiscvMacroInst::~RiscvMacroInst
~RiscvMacroInst()
Definition: static_inst.hh:109
thread_context.hh
gem5::RiscvISA::RiscvMacroInst::microops
std::vector< StaticInstPtr > microops
Definition: static_inst.hh:100
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::GenericISA::SimplePCState::advance
void advance() override
Definition: pcstate.hh:376
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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