gem5  v21.1.0.2
static_inst.hh
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29 
30 #ifndef __ARCH_RISCV_STATIC_INST_HH__
31 #define __ARCH_RISCV_STATIC_INST_HH__
32 
33 #include <string>
34 
35 #include "arch/riscv/types.hh"
36 #include "cpu/exec_context.hh"
37 #include "cpu/static_inst.hh"
38 #include "mem/packet.hh"
39 
40 namespace gem5
41 {
42 
43 namespace RiscvISA
44 {
45 
50 {
51  protected:
52  RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst,
53  OpClass __opClass) :
54  StaticInst(_mnemonic, __opClass), machInst(_machInst)
55  {}
56 
57  public:
59 
60  void advancePC(PCState &pc) const override { pc.advance(); }
61 
62  PCState
63  buildRetPC(const PCState &curPC, const PCState &callPC) const override
64  {
65  PCState retPC = callPC;
66  retPC.advance();
67  retPC.pc(curPC.npc());
68  return retPC;
69  }
70 
71  size_t
72  asBytes(void *buf, size_t size) override
73  {
74  return simpleAsBytes(buf, size, machInst);
75  }
76 };
77 
82 {
83  protected:
85 
86  RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
87  OpClass __opClass) :
88  RiscvStaticInst(mnem, _machInst, __opClass)
89  {
90  flags[IsMacroop] = true;
91  }
92 
93  ~RiscvMacroInst() { microops.clear(); }
94 
96  fetchMicroop(MicroPC upc) const override
97  {
98  return microops[upc];
99  }
100 
101  Fault
102  initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
103  {
104  panic("Tried to execute a macroop directly!\n");
105  }
106 
107  Fault
109  Trace::InstRecord *traceData) const override
110  {
111  panic("Tried to execute a macroop directly!\n");
112  }
113 
114  Fault
115  execute(ExecContext *xc, Trace::InstRecord *traceData) const override
116  {
117  panic("Tried to execute a macroop directly!\n");
118  }
119 };
120 
125 {
126  protected:
127  RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
128  OpClass __opClass) :
129  RiscvStaticInst(mnem, _machInst, __opClass)
130  {
131  flags[IsMicroop] = true;
132  }
133 
134  void advancePC(PCState &pcState) const override;
135 };
136 
137 } // namespace RiscvISA
138 } // namespace gem5
139 
140 #endif // __ARCH_RISCV_STATIC_INST_HH__
gem5::RiscvISA::RiscvMacroInst::completeAcc
Fault completeAcc(PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: static_inst.hh:108
gem5::GenericISA::SimplePCState::npc
Addr npc() const
Definition: types.hh:154
gem5::RiscvISA::RiscvMicroInst::RiscvMicroInst
RiscvMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:127
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition: static_inst.hh:49
gem5::RiscvISA::RiscvMacroInst::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC upc) const override
Return the microop that goes with a particular micropc.
Definition: static_inst.hh:96
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:383
gem5::RiscvISA::RiscvMacroInst
Base class for all RISC-V Macroops.
Definition: static_inst.hh:81
gem5::RiscvISA::RiscvMacroInst::initiateAcc
Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: static_inst.hh:102
gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst
RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:52
gem5::RiscvISA::RiscvMacroInst::RiscvMacroInst
RiscvMacroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:86
std::vector
STL vector class.
Definition: stl.hh:37
gem5::RefCountingPtr< StaticInst >
packet.hh
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::RiscvISA::RiscvStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:58
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RiscvISA::RiscvStaticInst::asBytes
size_t asBytes(void *buf, size_t size) override
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:72
types.hh
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
static_inst.hh
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:181
gem5::RiscvISA::RiscvMicroInst::advancePC
void advancePC(PCState &pcState) const override
Definition: static_inst.cc:42
gem5::RiscvISA::RiscvMacroInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: static_inst.hh:115
gem5::RiscvISA::RiscvStaticInst::advancePC
void advancePC(PCState &pc) const override
Definition: static_inst.hh:60
exec_context.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::RiscvISA::RiscvMicroInst
Base class for all RISC-V Microops.
Definition: static_inst.hh:124
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::RiscvMacroInst::~RiscvMacroInst
~RiscvMacroInst()
Definition: static_inst.hh:93
gem5::GenericISA::SimplePCState::pc
Addr pc() const
Definition: types.hh:151
gem5::RiscvISA::RiscvStaticInst::buildRetPC
PCState buildRetPC(const PCState &curPC, const PCState &callPC) const override
Definition: static_inst.hh:63
gem5::RiscvISA::RiscvMacroInst::microops
std::vector< StaticInstPtr > microops
Definition: static_inst.hh:84
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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