gem5
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arch
x86
regs
ccr.hh
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/*
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* Copyright (c) 2012 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_REGS_CCR_HH__
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#define __ARCH_X86_REGS_CCR_HH__
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#include "
cpu/reg_class.hh
"
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#include "debug/CCRegs.hh"
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namespace
gem5
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{
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namespace
X86ISA
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{
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namespace
cc_reg
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{
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enum :
RegIndex
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{
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_ZapsIdx
,
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_CfofIdx
,
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_DfIdx
,
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_EcfIdx
,
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_EzfIdx
,
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NumRegs
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};
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}
// namespace cc_reg
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inline
constexpr
RegClass
ccRegClass
(
CCRegClass
,
CCRegClassName
,
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cc_reg::NumRegs
, debug::CCRegs);
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namespace
cc_reg
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{
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inline
constexpr
RegId
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Zaps
=
ccRegClass
[
_ZapsIdx
],
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Cfof
=
ccRegClass
[
_CfofIdx
],
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Df
=
ccRegClass
[
_DfIdx
],
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Ecf
=
ccRegClass
[
_EcfIdx
],
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Ezf
=
ccRegClass
[
_EzfIdx
];
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}
// namespace cc_reg
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}
// namespace X86ISA
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}
// namespace gem5
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#endif
// __ARCH_X86_REGS_CCR_HH__
gem5::RegClass
Definition
reg_class.hh:186
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition
reg_class.hh:94
gem5::ArmISA::ccRegClass
constexpr RegClass ccRegClass
Definition
cc.hh:87
gem5::X86ISA::cc_reg::Cfof
constexpr RegId Cfof
Definition
ccr.hh:72
gem5::X86ISA::cc_reg::Ecf
constexpr RegId Ecf
Definition
ccr.hh:74
gem5::X86ISA::cc_reg::Df
constexpr RegId Df
Definition
ccr.hh:73
gem5::X86ISA::cc_reg::Ezf
constexpr RegId Ezf
Definition
ccr.hh:75
gem5::X86ISA::cc_reg::NumRegs
@ NumRegs
Definition
ccr.hh:59
gem5::X86ISA::cc_reg::_CfofIdx
@ _CfofIdx
Definition
ccr.hh:54
gem5::X86ISA::cc_reg::_ZapsIdx
@ _ZapsIdx
Definition
ccr.hh:53
gem5::X86ISA::cc_reg::_EcfIdx
@ _EcfIdx
Definition
ccr.hh:56
gem5::X86ISA::cc_reg::_DfIdx
@ _DfIdx
Definition
ccr.hh:55
gem5::X86ISA::cc_reg::_EzfIdx
@ _EzfIdx
Definition
ccr.hh:57
gem5::X86ISA::cc_reg::Zaps
constexpr RegId Zaps
Definition
ccr.hh:71
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::RegIndex
uint16_t RegIndex
Definition
types.hh:176
gem5::CCRegClassName
constexpr char CCRegClassName[]
Definition
reg_class.hh:81
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition
reg_class.hh:69
reg_class.hh
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