gem5  v22.1.0.0
gem5::AMDGPUDevice Member List

This is the complete list of members for gem5::AMDGPUDevice, including all inherited members.

_busAddrgem5::PciDeviceprotected
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_lastVMIDgem5::AMDGPUDeviceprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
allocateVMID(uint16_t pasid)gem5::AMDGPUDevice
AMDGPUDevice(const AMDGPUDeviceParams &p)gem5::AMDGPUDevice
BARsgem5::PciDeviceprotected
busAddr() constgem5::PciDeviceinline
cacheBlockSize() constgem5::DmaDeviceinline
checkpoint_before_mmiosgem5::AMDGPUDeviceprivate
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
configgem5::PciDeviceprotected
configDelaygem5::PciDeviceprotected
cpgem5::AMDGPUDeviceprivate
CP()gem5::AMDGPUDeviceinline
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
deallocateAllQueues()gem5::AMDGPUDevice
deallocatePasid(uint16_t pasid)gem5::AMDGPUDevice
deallocateVmid(uint16_t vmid)gem5::AMDGPUDevice
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
deviceIHgem5::AMDGPUDeviceprivate
deviceMemgem5::AMDGPUDeviceprivate
dispatchAccess(PacketPtr pkt, bool read)gem5::AMDGPUDeviceprivate
DmaDevice(const Params &p)gem5::DmaDevice
dmaPending() constgem5::DmaDeviceinline
dmaPortgem5::DmaDeviceprotected
dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)gem5::DmaDeviceinline
dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)gem5::DmaDeviceinline
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)gem5::DmaDeviceinline
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)gem5::DmaDeviceinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
doorbellsgem5::AMDGPUDeviceprivate
doorbellVMIDMapgem5::AMDGPUDeviceprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
frequency() constgem5::Clockedinline
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAddrRanges() const overridegem5::AMDGPUDevicevirtual
getBAR(Addr addr, int &num, Addr &offs)gem5::PciDeviceinlineprotected
getIH()gem5::AMDGPUDeviceinline
getMemMgr()gem5::AMDGPUDeviceinline
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::DmaDevicevirtual
getProbeManager()gem5::SimObject
getRegVal(uint32_t addr)gem5::AMDGPUDevice
getSDMAById(int id)gem5::AMDGPUDevice
getSDMAEngine(Addr offset)gem5::AMDGPUDevice
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getUsedVMIDs()gem5::AMDGPUDevice
getVM()gem5::AMDGPUDeviceinline
getVMID(Addr doorbell)gem5::AMDGPUDeviceinline
gpuMemMgrgem5::AMDGPUDeviceprivate
GPURegMap typedefgem5::AMDGPUDeviceprivate
gpuvmgem5::AMDGPUDeviceprivate
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
hostInterfacegem5::PciDeviceprotected
idMapgem5::AMDGPUDeviceprivate
init() overridegem5::DmaDevicevirtual
init_interrupt_countgem5::AMDGPUDeviceprivate
initState()gem5::SimObjectvirtual
insertQId(uint16_t vmid, int id)gem5::AMDGPUDevice
interruptLine() constgem5::PciDeviceinline
intrClear()gem5::PciDeviceinline
intrPost()gem5::AMDGPUDevice
isROM(Addr addr) constgem5::AMDGPUDeviceinlineprivate
lastVMID()gem5::AMDGPUDeviceinline
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
mapDoorbellToVMID(Addr doorbell, uint16_t vmid)gem5::AMDGPUDevice
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
mmioReadergem5::AMDGPUDeviceprivate
msicapgem5::PciDeviceprotected
MSICAP_BASEgem5::PciDeviceprotected
msix_pbagem5::PciDeviceprotected
MSIX_PBA_ENDgem5::PciDeviceprotected
MSIX_PBA_OFFSETgem5::PciDeviceprotected
msix_tablegem5::PciDeviceprotected
MSIX_TABLE_ENDgem5::PciDeviceprotected
MSIX_TABLE_OFFSETgem5::PciDeviceprotected
msixcapgem5::PciDeviceprotected
MSIXCAP_BASEgem5::PciDeviceprotected
MSIXCAP_ID_OFFSETgem5::PciDeviceprotected
MSIXCAP_MPBA_OFFSETgem5::PciDeviceprotected
MSIXCAP_MTAB_OFFSETgem5::PciDeviceprotected
MSIXCAP_MXC_OFFSETgem5::PciDeviceprotected
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
Params typedefgem5::DmaDevice
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
PciDevice(const PciDeviceParams &params)gem5::PciDevice
pciToDma(Addr pci_addr) constgem5::PciDeviceinline
pioDelaygem5::PciDeviceprotected
PioDevice(const Params &p)gem5::PioDevice
pioPortgem5::PioDeviceprotected
pm4PktProcgem5::AMDGPUDeviceprivate
pmcapgem5::PciDeviceprotected
PMCAP_BASEgem5::PciDeviceprotected
PMCAP_ID_OFFSETgem5::PciDeviceprotected
PMCAP_PC_OFFSETgem5::PciDeviceprotected
PMCAP_PMCS_OFFSETgem5::PciDeviceprotected
powerStategem5::ClockedObject
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
pxcapgem5::PciDeviceprotected
PXCAP_BASEgem5::PciDeviceprotected
read(PacketPtr pkt) overridegem5::AMDGPUDevicevirtual
readConfig(PacketPtr pkt) overridegem5::AMDGPUDevicevirtual
readDoorbell(PacketPtr pkt, Addr offset)gem5::AMDGPUDeviceprivate
readFrame(PacketPtr pkt, Addr offset)gem5::AMDGPUDeviceprivate
readMMIO(PacketPtr pkt, Addr offset)gem5::AMDGPUDeviceprivate
readROM(PacketPtr pkt)gem5::AMDGPUDeviceprivate
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regsgem5::AMDGPUDeviceprivate
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
romgem5::AMDGPUDeviceprivate
romRangegem5::AMDGPUDeviceprivate
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
sdma0gem5::AMDGPUDeviceprivate
sdma1gem5::AMDGPUDeviceprivate
sdmaEngsgem5::AMDGPUDeviceprivate
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::AMDGPUDevicevirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setDoorbellType(uint32_t offset, QueueType qt)gem5::AMDGPUDevice
setRegVal(uint32_t addr, uint32_t value)gem5::AMDGPUDevice
setSDMAEngine(Addr offset, SDMAEngine *eng)gem5::AMDGPUDevice
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
simObjectListgem5::SimObjectprivatestatic
SimObjectList typedefgem5::SimObjectprivate
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
sysgem5::PioDeviceprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
unserialize(CheckpointIn &cp) overridegem5::AMDGPUDevicevirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
usedVMIDsgem5::AMDGPUDeviceprivate
voltage() constgem5::Clockedinline
vramRequestorId()gem5::AMDGPUDeviceinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
write(PacketPtr pkt) overridegem5::AMDGPUDevicevirtual
writeConfig(PacketPtr pkt) overridegem5::AMDGPUDevicevirtual
writeDoorbell(PacketPtr pkt, Addr offset)gem5::AMDGPUDeviceprivate
writeFrame(PacketPtr pkt, Addr offset)gem5::AMDGPUDeviceprivate
writeMMIO(PacketPtr pkt, Addr offset)gem5::AMDGPUDeviceprivate
~Clocked()gem5::Clockedinlineprotectedvirtual
~DmaDevice()=defaultgem5::DmaDevicevirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~PioDevice()gem5::PioDevicevirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual
Generated on Wed Dec 21 2022 10:23:15 for gem5 by doxygen 1.9.1