gem5 v24.0.0.0
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Generic representation of an Arm interrupt pin. More...
#include <base_gic.hh>
Public Member Functions | |
void | setThreadContext (ThreadContext *tc) |
Set the thread context owning this interrupt. | |
uint32_t | num () const |
Get interrupt number. | |
bool | active () const |
True if interrupt pin is active, false otherwise. | |
virtual void | raise ()=0 |
Signal an interrupt. | |
virtual void | clear ()=0 |
Clear a signalled interrupt. | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
Public Member Functions inherited from gem5::Serializable | |
Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
Protected Member Functions | |
ArmInterruptPin (const ArmInterruptPinParams &p, ThreadContext *tc) | |
ContextID | targetContext () const |
Get the target context ID of this interrupt. | |
Protected Attributes | |
const ThreadContext * | threadContext |
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt. | |
RealView *const | platform |
Arm platform to use for interrupt generation. | |
const uint32_t | intNum |
Interrupt number to generate. | |
const ArmInterruptType | triggerType |
Interrupt triggering type. | |
bool | _active |
True if interrupt pin is active, false otherwise. | |
Friends | |
class | ArmInterruptPinGen |
Additional Inherited Members | |
Static Public Member Functions inherited from gem5::Serializable | |
static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
Generic representation of an Arm interrupt pin.
Definition at line 199 of file base_gic.hh.
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protected |
Definition at line 152 of file base_gic.cc.
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inline |
True if interrupt pin is active, false otherwise.
Definition at line 219 of file base_gic.hh.
References _active.
Referenced by gem5::Sp805::read(), gem5::Sp805::sendInt(), gem5::ArchTimer::setControl(), and gem5::ArchTimer::updateCounter().
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pure virtual |
Clear a signalled interrupt.
Implemented in gem5::ArmPPI, gem5::ArmSigInterruptPin, and gem5::ArmSPI.
Referenced by gem5::Sp805::clearInt(), gem5::ArmISA::PMU::clearInterrupt(), gem5::Scp2ApDoorbell::clearInterrupt(), gem5::GenericWatchdog::explicitRefresh(), gem5::BaseArmKvmCPU::kvmRun(), gem5::ArchTimer::setControl(), gem5::HDLcd::setInterrupts(), gem5::MmioVirtIO::setInterrupts(), gem5::Pl011::setInterrupts(), gem5::ArchTimer::updateCounter(), gem5::Pl050::updateIntCtrl(), gem5::Gicv3CPUInterface::virtualUpdate(), and gem5::Pl111::write().
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inline |
Get interrupt number.
Definition at line 216 of file base_gic.hh.
References intNum.
Referenced by gem5::Gicv3CPUInterface::setThreadContext(), and gem5::Gicv3CPUInterface::virtualUpdate().
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pure virtual |
Signal an interrupt.
Implemented in gem5::ArmPPI, gem5::ArmSigInterruptPin, and gem5::ArmSPI.
Referenced by gem5::ArchTimer::counterLimitReached(), gem5::PL031::counterMatch(), gem5::Pl011::generateInterrupt(), gem5::Pl111::generateInterrupt(), gem5::BaseArmKvmCPU::kvmRun(), gem5::ArmSigInterruptPin::raise(), gem5::ArmISA::PMU::raiseInterrupt(), gem5::Scp2ApDoorbell::raiseInterrupt(), gem5::SMMUTranslationProcess::sendEventInterrupt(), gem5::Sp805::sendInt(), gem5::HDLcd::setInterrupts(), gem5::MmioVirtIO::setInterrupts(), gem5::GenericWatchdog::timeout(), gem5::Pl050::updateIntCtrl(), and gem5::Gicv3CPUInterface::virtualUpdate().
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overridevirtual |
Serialize an object.
Output an object's state into the current checkpoint section.
cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 177 of file base_gic.cc.
References _active, and SERIALIZE_SCALAR.
void gem5::ArmInterruptPin::setThreadContext | ( | ThreadContext * | tc | ) |
Set the thread context owning this interrupt.
This method is used to set the thread context for interrupts that are thread/CPU-specific. Only devices that are used in such a context are expected to call this method.
Definition at line 160 of file base_gic.cc.
References panic_if, and threadContext.
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protected |
Get the target context ID of this interrupt.
Definition at line 169 of file base_gic.cc.
References gem5::ThreadContext::contextId(), panic_if, and threadContext.
Referenced by gem5::ArmPPI::clear(), and gem5::ArmPPI::raise().
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overridevirtual |
Unserialize an object.
Read an object's state from the current checkpoint section.
cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 183 of file base_gic.cc.
References _active, and UNSERIALIZE_SCALAR.
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friend |
Definition at line 201 of file base_gic.hh.
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protected |
True if interrupt pin is active, false otherwise.
Definition at line 255 of file base_gic.hh.
Referenced by active(), gem5::ArmPPI::clear(), gem5::ArmSigInterruptPin::clear(), gem5::ArmSPI::clear(), gem5::ArmPPI::raise(), gem5::ArmSigInterruptPin::raise(), gem5::ArmSPI::raise(), serialize(), and unserialize().
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protected |
Interrupt number to generate.
Definition at line 249 of file base_gic.hh.
Referenced by gem5::ArmPPI::clear(), gem5::ArmSPI::clear(), num(), gem5::ArmPPI::raise(), and gem5::ArmSPI::raise().
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protected |
Arm platform to use for interrupt generation.
Definition at line 246 of file base_gic.hh.
Referenced by gem5::ArmPPI::ArmPPI(), gem5::ArmSPI::ArmSPI(), gem5::ArmPPI::clear(), gem5::ArmSPI::clear(), gem5::ArmPPI::raise(), and gem5::ArmSPI::raise().
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protected |
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition at line 243 of file base_gic.hh.
Referenced by setThreadContext(), and targetContext().
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protected |
Interrupt triggering type.
Definition at line 252 of file base_gic.hh.