gem5  v21.1.0.2
base_gic.cc
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37 
38 #include "dev/arm/base_gic.hh"
39 
40 #include "cpu/thread_context.hh"
41 #include "dev/arm/realview.hh"
42 #include "params/ArmInterruptPin.hh"
43 #include "params/ArmPPI.hh"
44 #include "params/ArmSigInterruptPin.hh"
45 #include "params/ArmSPI.hh"
46 #include "params/BaseGic.hh"
47 
48 namespace gem5
49 {
50 
52  : PioDevice(p),
53  platform(p.platform)
54 {
55  RealView *const rv = dynamic_cast<RealView*>(p.platform);
56  // The platform keeps track of the GIC that is hooked up to the
57  // system. Due to quirks in gem5's configuration system, the
58  // platform can't take a GIC as parameter. Instead, we need to
59  // register with the platform when a new GIC is created. If we
60  // can't find a platform, something is seriously wrong.
61  fatal_if(!rv, "GIC model can't register with platform code");
62  rv->setGic(this);
63 }
64 
66 {
67 }
68 
69 void
71 {
73  getSystem()->setGIC(this);
74 }
75 
76 const BaseGic::Params &
78 {
79  return dynamic_cast<const Params &>(_params);
80 }
81 
82 ArmInterruptPinGen::ArmInterruptPinGen(const ArmInterruptPinParams &p)
83  : SimObject(p)
84 {
85 }
86 
87 ArmSPIGen::ArmSPIGen(const ArmSPIParams &p)
88  : ArmInterruptPinGen(p), pin(new ArmSPI(p))
89 {
90 }
91 
94 {
95  return pin;
96 }
97 
98 ArmPPIGen::ArmPPIGen(const ArmPPIParams &p)
100 {
101 }
102 
105 {
106  panic_if(!tc, "Invalid Thread Context\n");
107  ContextID cid = tc->contextId();
108 
109  auto pin_it = pins.find(cid);
110 
111  if (pin_it != pins.end()) {
112  // PPI Pin Already generated
113  return pin_it->second;
114  } else {
115  // Generate PPI Pin
116  ArmPPI *pin = new ArmPPI(ArmPPIGen::params(), tc);
117 
118  pins.insert({cid, pin});
119 
120  return pin;
121  }
122 }
123 
124 ArmSigInterruptPinGen::ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
126 {}
127 
130 {
131  return pin;
132 }
133 
134 Port &
135 ArmSigInterruptPinGen::getPort(const std::string &if_name, PortID idx)
136 {
137  if (if_name == "irq") {
138  assert(idx != InvalidPortID);
139  if (idx >= pin->sigPin.size())
140  pin->sigPin.resize(idx + 1);
141  if (!pin->sigPin.at(idx))
142  pin->sigPin.at(idx).reset(
144  csprintf("%s.irq[%d]", name(), idx), idx, this));
145  return *pin->sigPin.at(idx);
146  }
147 
148  return ArmInterruptPinGen::getPort(if_name, idx);
149 }
150 
152  const ArmInterruptPinParams &p, ThreadContext *tc)
153  : threadContext(tc), platform(dynamic_cast<RealView*>(p.platform)),
154  intNum(p.num), triggerType(p.int_type), _active(false)
155 {
156  fatal_if(!platform, "Interrupt not connected to a RealView platform");
157 }
158 
159 void
161 {
163  "InterruptLine::setThreadContext called twice\n");
164 
165  threadContext = tc;
166 }
167 
168 ContextID
170 {
171  panic_if(!threadContext, "Per-context interrupt triggered without a " \
172  "call to InterruptLine::setThreadContext.\n");
173  return threadContext->contextId();
174 }
175 
176 void
178 {
180 }
181 
182 void
184 {
186 }
187 
189  const ArmSPIParams &p)
190  : ArmInterruptPin(p, nullptr)
191 {
192 }
193 
194 void
196 {
197  _active = true;
199 }
200 
201 void
203 {
204  _active = false;
206 }
207 
209  const ArmPPIParams &p, ThreadContext *tc)
210  : ArmInterruptPin(p, tc)
211 {
212 }
213 
214 void
216 {
217  _active = true;
219 }
220 
221 void
223 {
224  _active = false;
226 }
227 
228 ArmSigInterruptPin::ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
229  : ArmInterruptPin(p, nullptr)
230 {}
231 
232 void
234 {
235  _active = true;
236  for (auto &pin : sigPin)
237  if (pin)
238  pin->raise();
239 }
240 
241 void
243 {
244  _active = false;
245  for (auto &pin : sigPin)
246  if (pin)
247  pin->lower();
248 }
249 
250 } // namespace gem5
gem5::RealView::setGic
void setGic(BaseGic *_gic)
Give platform a pointer to interrupt controller.
Definition: realview.hh:70
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ArmInterruptPin::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: base_gic.cc:177
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::ArmInterruptPin::threadContext
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition: base_gic.hh:244
gem5::BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:114
gem5::RealView::gic
BaseGic * gic
Definition: realview.hh:62
gem5::BaseGic::~BaseGic
virtual ~BaseGic()
Definition: base_gic.cc:65
gem5::ArmInterruptPin::intNum
const uint32_t intNum
Interrupt number to generate.
Definition: base_gic.hh:250
gem5::ArmSigInterruptPinGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:129
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::ArmSPIGen::ArmSPIGen
ArmSPIGen(const ArmSPIParams &p)
Definition: base_gic.cc:87
gem5::ArmSigInterruptPin::sigPin
std::vector< std::unique_ptr< IntSourcePin< ArmSigInterruptPinGen > > > sigPin
Definition: base_gic.hh:287
gem5::ArmSPI::raise
void raise() override
Signal an interrupt.
Definition: base_gic.cc:195
gem5::BaseGic::BaseGic
BaseGic(const Params &p)
Definition: base_gic.cc:51
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmInterruptPin::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: base_gic.cc:183
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::ArmSigInterruptPinGen::ArmSigInterruptPinGen
ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
Definition: base_gic.cc:124
gem5::SimObject::_params
const SimObjectParams & _params
Cached copy of the object parameters.
Definition: sim_object.hh:167
base_gic.hh
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ArmSPI::ArmSPI
ArmSPI(const ArmSPIParams &p)
Definition: base_gic.cc:188
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
realview.hh
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmInterruptPin::ArmInterruptPin
ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc)
Definition: base_gic.cc:151
gem5::ArmInterruptPin::targetContext
ContextID targetContext() const
Get the target context ID of this interrupt.
Definition: base_gic.cc:169
gem5::ArmSigInterruptPin
Definition: base_gic.hh:281
gem5::PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::ArmPPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:222
gem5::ArmPPIGen::pins
std::unordered_map< ContextID, ArmPPI * > pins
Definition: base_gic.hh:181
gem5::ArmSigInterruptPin::ArmSigInterruptPin
ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
Definition: base_gic.cc:228
gem5::ArmSigInterruptPin::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:242
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::BaseGic::clearPPInt
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ArmSPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:93
gem5::ArmInterruptPin::_active
bool _active
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:256
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::ArmPPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:104
gem5::BaseGic::params
const Params & params() const
Definition: base_gic.cc:77
gem5::ArmSigInterruptPinGen::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: base_gic.cc:135
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseGic::sendInt
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
gem5::BaseGic::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base_gic.cc:70
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
gem5::ArmPPIGen::ArmPPIGen
ArmPPIGen(const Params &p)
Definition: base_gic.cc:98
gem5::ArmPPI::raise
void raise() override
Signal an interrupt.
Definition: base_gic.cc:215
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::ArmInterruptPin::platform
RealView *const platform
Arm platform to use for interrupt generation.
Definition: base_gic.hh:247
gem5::ArmSPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:202
gem5::ArmPPI::ArmPPI
ArmPPI(const ArmPPIParams &p, ThreadContext *tc)
Definition: base_gic.cc:208
gem5::ArmSigInterruptPinGen::pin
ArmSigInterruptPin * pin
Definition: base_gic.hh:194
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::ArmInterruptPin::setThreadContext
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
Definition: base_gic.cc:160
gem5::BaseGic::clearInt
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmSPIGen::pin
ArmSPI * pin
Definition: base_gic.hh:165
gem5::RealView
Definition: realview.hh:59
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::ArmSystem::setGIC
void setGIC(BaseGic *gic)
Sets the pointer to the GIC.
Definition: system.hh:186
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:200
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::IntSourcePin
Definition: intpin.hh:112
gem5::ArmInterruptPinGen::ArmInterruptPinGen
ArmInterruptPinGen(const ArmInterruptPinParams &p)
Definition: base_gic.cc:82
gem5::BaseGic::sendPPInt
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmSPI
Definition: base_gic.hh:259
gem5::ArmPPI
Definition: base_gic.hh:270
thread_context.hh
gem5::ArmInterruptPinGen
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition: base_gic.hh:145
gem5::ArmSigInterruptPin::raise
void raise() override
Signal an interrupt.
Definition: base_gic.cc:233

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