gem5 v24.0.0.0
Loading...
Searching...
No Matches
base_gic.cc
Go to the documentation of this file.
1/*
2 * Copyright (c) 2012, 2017-2018, 2021 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "dev/arm/base_gic.hh"
39
40#include "cpu/thread_context.hh"
41#include "dev/arm/realview.hh"
42#include "debug/GIC.hh"
43#include "params/ArmInterruptPin.hh"
44#include "params/ArmPPI.hh"
45#include "params/ArmSigInterruptPin.hh"
46#include "params/ArmSPI.hh"
47#include "params/BaseGic.hh"
48
49namespace gem5
50{
51
53 : PioDevice(p),
54 platform(p.platform)
55{
56 RealView *const rv = dynamic_cast<RealView*>(p.platform);
57 // The platform keeps track of the GIC that is hooked up to the
58 // system. Due to quirks in gem5's configuration system, the
59 // platform can't take a GIC as parameter. Instead, we need to
60 // register with the platform when a new GIC is created. If we
61 // can't find a platform, something is seriously wrong.
62 fatal_if(!rv, "GIC model can't register with platform code");
63 rv->setGic(this);
64}
65
69
70void
72{
74 getSystem()->setGIC(this);
75}
76
77const BaseGic::Params &
79{
80 return dynamic_cast<const Params &>(_params);
81}
82
83ArmInterruptPinGen::ArmInterruptPinGen(const ArmInterruptPinParams &p)
84 : SimObject(p)
85{
86}
87
88ArmSPIGen::ArmSPIGen(const ArmSPIParams &p)
89 : ArmInterruptPinGen(p), pin(new ArmSPI(p))
90{
91}
92
95{
96 return pin;
97}
98
99ArmPPIGen::ArmPPIGen(const ArmPPIParams &p)
101{
102}
103
106{
107 panic_if(!tc, "Invalid Thread Context\n");
108 ContextID cid = tc->contextId();
109
110 auto pin_it = pins.find(cid);
111
112 if (pin_it != pins.end()) {
113 // PPI Pin Already generated
114 return pin_it->second;
115 } else {
116 // Generate PPI Pin
117 ArmPPI *pin = new ArmPPI(ArmPPIGen::params(), tc);
118
119 pins.insert({cid, pin});
120
121 return pin;
122 }
123}
124
125ArmSigInterruptPinGen::ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
127{}
128
134
135Port &
136ArmSigInterruptPinGen::getPort(const std::string &if_name, PortID idx)
137{
138 if (if_name == "irq") {
139 assert(idx != InvalidPortID);
140 if (idx >= pin->sigPin.size())
141 pin->sigPin.resize(idx + 1);
142 if (!pin->sigPin.at(idx))
143 pin->sigPin.at(idx).reset(
145 csprintf("%s.irq[%d]", name(), idx), idx, this));
146 return *pin->sigPin.at(idx);
147 }
148
149 return ArmInterruptPinGen::getPort(if_name, idx);
150}
151
153 const ArmInterruptPinParams &p, ThreadContext *tc)
154 : threadContext(tc), platform(dynamic_cast<RealView*>(p.platform)),
155 intNum(p.num), triggerType(p.int_type), _active(false)
156{
157}
158
159void
161{
163 "InterruptLine::setThreadContext called twice\n");
164
165 threadContext = tc;
166}
167
170{
171 panic_if(!threadContext, "Per-context interrupt triggered without a " \
172 "call to InterruptLine::setThreadContext.\n");
173 return threadContext->contextId();
174}
175
176void
181
182void
187
189 const ArmSPIParams &p)
190 : ArmInterruptPin(p, nullptr)
191{
192 fatal_if(!platform, "Interrupt not connected to a RealView platform");
193}
194
195void
197{
198 _active = true;
200}
201
202void
204{
205 _active = false;
207}
208
210 const ArmPPIParams &p, ThreadContext *tc)
211 : ArmInterruptPin(p, tc)
212{
213 fatal_if(!platform, "Interrupt not connected to a RealView platform");
214}
215
216void
218{
219 _active = true;
221}
222
223void
225{
226 _active = false;
228}
229
230ArmSigInterruptPin::ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
231 : ArmInterruptPin(p, nullptr)
232{}
233
234void
236{
237 _active = true;
238 for (auto &pin : sigPin)
239 if (pin)
240 pin->raise();
241}
242
243void
245{
246 _active = false;
247 for (auto &pin : sigPin)
248 if (pin)
249 pin->lower();
250}
251
252} // namespace gem5
Base class for ARM GIC implementations.
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition base_gic.hh:145
ArmInterruptPinGen(const ArmInterruptPinParams &p)
Definition base_gic.cc:83
Generic representation of an Arm interrupt pin.
Definition base_gic.hh:200
RealView *const platform
Arm platform to use for interrupt generation.
Definition base_gic.hh:246
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition base_gic.cc:183
ContextID targetContext() const
Get the target context ID of this interrupt.
Definition base_gic.cc:169
const uint32_t intNum
Interrupt number to generate.
Definition base_gic.hh:249
bool _active
True if interrupt pin is active, false otherwise.
Definition base_gic.hh:255
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition base_gic.cc:177
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
Definition base_gic.cc:160
virtual void raise()=0
Signal an interrupt.
ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc)
Definition base_gic.cc:152
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition base_gic.hh:243
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition base_gic.cc:105
std::unordered_map< ContextID, ArmPPI * > pins
Definition base_gic.hh:180
ArmPPIGen(const Params &p)
Definition base_gic.cc:99
void clear() override
Clear a signalled interrupt.
Definition base_gic.cc:224
ArmPPI(const ArmPPIParams &p, ThreadContext *tc)
Definition base_gic.cc:209
void raise() override
Signal an interrupt.
Definition base_gic.cc:217
ArmSPIGen(const ArmSPIParams &p)
Definition base_gic.cc:88
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition base_gic.cc:94
void raise() override
Signal an interrupt.
Definition base_gic.cc:196
ArmSPI(const ArmSPIParams &p)
Definition base_gic.cc:188
void clear() override
Clear a signalled interrupt.
Definition base_gic.cc:203
ArmSigInterruptPin * pin
Definition base_gic.hh:193
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition base_gic.cc:130
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition base_gic.cc:136
ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
Definition base_gic.cc:125
std::vector< std::unique_ptr< IntSourcePin< ArmSigInterruptPinGen > > > sigPin
Definition base_gic.hh:286
ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
Definition base_gic.cc:230
void raise() override
Signal an interrupt.
Definition base_gic.cc:235
void clear() override
Clear a signalled interrupt.
Definition base_gic.cc:244
void setGIC(BaseGic *gic)
Sets the pointer to the GIC.
Definition system.hh:168
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition base_gic.cc:71
const Params & params() const
Definition base_gic.cc:78
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
BaseGicParams Params
Definition base_gic.hh:75
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
virtual ~BaseGic()
Definition base_gic.cc:66
ArmSystem * getSystem() const
Definition base_gic.hh:114
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
BaseGic(const Params &p)
Definition base_gic.cc:52
virtual std::string name() const
Definition named.hh:47
This device is the base class which all devices senstive to an address range inherit from.
Definition io_device.hh:103
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition io_device.cc:59
Ports are used to interface objects to each other.
Definition port.hh:62
void setGic(BaseGic *_gic)
Give platform a pointer to interrupt controller.
Definition realview.hh:70
BaseGic * gic
Definition realview.hh:62
Abstract superclass for simulation objects.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual ContextID contextId() const =0
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition logging.hh:236
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
const Params & params() const
const SimObjectParams & _params
Cached copy of the object parameters.
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
const PortID InvalidPortID
Definition types.hh:246
std::ostream CheckpointOut
Definition serialize.hh:66
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
int ContextID
Globally unique thread context ID.
Definition types.hh:239
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
Declaration of top level class for the RealView platform chips.
#define UNSERIALIZE_SCALAR(scalar)
Definition serialize.hh:575
#define SERIALIZE_SCALAR(scalar)
Definition serialize.hh:568

Generated on Tue Jun 18 2024 16:24:02 for gem5 by doxygen 1.11.0