gem5  v22.0.0.2
base_gic.cc
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37 
38 #include "dev/arm/base_gic.hh"
39 
40 #include "cpu/thread_context.hh"
41 #include "dev/arm/realview.hh"
42 #include "debug/GIC.hh"
43 #include "params/ArmInterruptPin.hh"
44 #include "params/ArmPPI.hh"
45 #include "params/ArmSigInterruptPin.hh"
46 #include "params/ArmSPI.hh"
47 #include "params/BaseGic.hh"
48 
49 namespace gem5
50 {
51 
53  : PioDevice(p),
54  platform(p.platform)
55 {
56  RealView *const rv = dynamic_cast<RealView*>(p.platform);
57  // The platform keeps track of the GIC that is hooked up to the
58  // system. Due to quirks in gem5's configuration system, the
59  // platform can't take a GIC as parameter. Instead, we need to
60  // register with the platform when a new GIC is created. If we
61  // can't find a platform, something is seriously wrong.
62  fatal_if(!rv, "GIC model can't register with platform code");
63  rv->setGic(this);
64 }
65 
67 {
68 }
69 
70 void
72 {
74  getSystem()->setGIC(this);
75 }
76 
77 const BaseGic::Params &
79 {
80  return dynamic_cast<const Params &>(_params);
81 }
82 
83 ArmInterruptPinGen::ArmInterruptPinGen(const ArmInterruptPinParams &p)
84  : SimObject(p)
85 {
86 }
87 
88 ArmSPIGen::ArmSPIGen(const ArmSPIParams &p)
89  : ArmInterruptPinGen(p), pin(new ArmSPI(p))
90 {
91 }
92 
95 {
96  return pin;
97 }
98 
99 ArmPPIGen::ArmPPIGen(const ArmPPIParams &p)
101 {
102 }
103 
106 {
107  panic_if(!tc, "Invalid Thread Context\n");
108  ContextID cid = tc->contextId();
109 
110  auto pin_it = pins.find(cid);
111 
112  if (pin_it != pins.end()) {
113  // PPI Pin Already generated
114  return pin_it->second;
115  } else {
116  // Generate PPI Pin
117  ArmPPI *pin = new ArmPPI(ArmPPIGen::params(), tc);
118 
119  pins.insert({cid, pin});
120 
121  return pin;
122  }
123 }
124 
125 ArmSigInterruptPinGen::ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
127 {}
128 
131 {
132  return pin;
133 }
134 
135 Port &
136 ArmSigInterruptPinGen::getPort(const std::string &if_name, PortID idx)
137 {
138  if (if_name == "irq") {
139  assert(idx != InvalidPortID);
140  if (idx >= pin->sigPin.size())
141  pin->sigPin.resize(idx + 1);
142  if (!pin->sigPin.at(idx))
143  pin->sigPin.at(idx).reset(
145  csprintf("%s.irq[%d]", name(), idx), idx, this));
146  return *pin->sigPin.at(idx);
147  }
148 
149  return ArmInterruptPinGen::getPort(if_name, idx);
150 }
151 
153  const ArmInterruptPinParams &p, ThreadContext *tc)
154  : threadContext(tc), platform(dynamic_cast<RealView*>(p.platform)),
155  intNum(p.num), triggerType(p.int_type), _active(false)
156 {
157  fatal_if(!platform, "Interrupt not connected to a RealView platform");
158 }
159 
160 void
162 {
164  "InterruptLine::setThreadContext called twice\n");
165 
166  threadContext = tc;
167 }
168 
169 ContextID
171 {
172  panic_if(!threadContext, "Per-context interrupt triggered without a " \
173  "call to InterruptLine::setThreadContext.\n");
174  return threadContext->contextId();
175 }
176 
177 void
179 {
181 }
182 
183 void
185 {
187 }
188 
190  const ArmSPIParams &p)
191  : ArmInterruptPin(p, nullptr)
192 {
193 }
194 
195 void
197 {
198  _active = true;
200 }
201 
202 void
204 {
205  _active = false;
207 }
208 
210  const ArmPPIParams &p, ThreadContext *tc)
211  : ArmInterruptPin(p, tc)
212 {
213 }
214 
215 void
217 {
218  _active = true;
220 }
221 
222 void
224 {
225  _active = false;
227 }
228 
229 ArmSigInterruptPin::ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
230  : ArmInterruptPin(p, nullptr)
231 {}
232 
233 void
235 {
236  _active = true;
237  for (auto &pin : sigPin)
238  if (pin)
239  pin->raise();
240 }
241 
242 void
244 {
245  _active = false;
246  for (auto &pin : sigPin)
247  if (pin)
248  pin->lower();
249 }
250 
251 } // namespace gem5
gem5::RealView::setGic
void setGic(BaseGic *_gic)
Give platform a pointer to interrupt controller.
Definition: realview.hh:70
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::ArmInterruptPin::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: base_gic.cc:178
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:126
gem5::ArmInterruptPin::threadContext
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition: base_gic.hh:243
gem5::BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:114
gem5::RealView::gic
BaseGic * gic
Definition: realview.hh:62
gem5::BaseGic::~BaseGic
virtual ~BaseGic()
Definition: base_gic.cc:66
gem5::ArmInterruptPin::intNum
const uint32_t intNum
Interrupt number to generate.
Definition: base_gic.hh:249
gem5::ArmSigInterruptPinGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:130
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::ArmSPIGen::ArmSPIGen
ArmSPIGen(const ArmSPIParams &p)
Definition: base_gic.cc:88
gem5::ArmSigInterruptPin::sigPin
std::vector< std::unique_ptr< IntSourcePin< ArmSigInterruptPinGen > > > sigPin
Definition: base_gic.hh:286
gem5::ArmSPI::raise
void raise() override
Signal an interrupt.
Definition: base_gic.cc:196
gem5::BaseGic::BaseGic
BaseGic(const Params &p)
Definition: base_gic.cc:52
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmInterruptPin::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: base_gic.cc:184
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::ArmSigInterruptPinGen::ArmSigInterruptPinGen
ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
Definition: base_gic.cc:125
gem5::SimObject::_params
const SimObjectParams & _params
Cached copy of the object parameters.
Definition: sim_object.hh:167
base_gic.hh
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ArmSPI::ArmSPI
ArmSPI(const ArmSPIParams &p)
Definition: base_gic.cc:189
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
realview.hh
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:246
gem5::ArmInterruptPin::ArmInterruptPin
ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc)
Definition: base_gic.cc:152
gem5::ArmInterruptPin::targetContext
ContextID targetContext() const
Get the target context ID of this interrupt.
Definition: base_gic.cc:170
gem5::ArmSigInterruptPin
Definition: base_gic.hh:280
gem5::PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::ArmPPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:223
gem5::ArmPPIGen::pins
std::unordered_map< ContextID, ArmPPI * > pins
Definition: base_gic.hh:180
gem5::ArmSigInterruptPin::ArmSigInterruptPin
ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
Definition: base_gic.cc:229
gem5::ArmSigInterruptPin::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:243
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::BaseGic::clearPPInt
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ArmSPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:94
gem5::ArmInterruptPin::_active
bool _active
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:255
gem5::ArmPPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:105
gem5::BaseGic::params
const Params & params() const
Definition: base_gic.cc:78
gem5::ArmSigInterruptPinGen::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: base_gic.cc:136
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseGic::sendInt
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
gem5::BaseGic::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base_gic.cc:71
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
gem5::ArmPPIGen::ArmPPIGen
ArmPPIGen(const Params &p)
Definition: base_gic.cc:99
gem5::ArmPPI::raise
void raise() override
Signal an interrupt.
Definition: base_gic.cc:216
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::ArmInterruptPin::platform
RealView *const platform
Arm platform to use for interrupt generation.
Definition: base_gic.hh:246
gem5::ArmSPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:203
gem5::ArmPPI::ArmPPI
ArmPPI(const ArmPPIParams &p, ThreadContext *tc)
Definition: base_gic.cc:209
gem5::ArmSigInterruptPinGen::pin
ArmSigInterruptPin * pin
Definition: base_gic.hh:193
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::ArmInterruptPin::setThreadContext
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
Definition: base_gic.cc:161
gem5::BaseGic::clearInt
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmSPIGen::pin
ArmSPI * pin
Definition: base_gic.hh:164
gem5::RealView
Definition: realview.hh:59
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::ArmSystem::setGIC
void setGIC(BaseGic *gic)
Sets the pointer to the GIC.
Definition: system.hh:164
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:199
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::IntSourcePin
Definition: intpin.hh:112
gem5::ArmInterruptPinGen::ArmInterruptPinGen
ArmInterruptPinGen(const ArmInterruptPinParams &p)
Definition: base_gic.cc:83
gem5::BaseGic::sendPPInt
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:226
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmSPI
Definition: base_gic.hh:258
gem5::ArmPPI
Definition: base_gic.hh:269
thread_context.hh
gem5::ArmInterruptPinGen
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition: base_gic.hh:144
gem5::ArmSigInterruptPin::raise
void raise() override
Signal an interrupt.
Definition: base_gic.cc:234

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