gem5  v21.1.0.2
base_gic.hh
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37 
42 #ifndef __DEV_ARM_BASE_GIC_H__
43 #define __DEV_ARM_BASE_GIC_H__
44 
45 #include <memory>
46 #include <unordered_map>
47 #include <vector>
48 
49 #include "arch/arm/system.hh"
50 #include "dev/intpin.hh"
51 #include "dev/io_device.hh"
52 
53 #include "enums/ArmInterruptType.hh"
54 
55 namespace gem5
56 {
57 
58 class Platform;
59 class RealView;
60 class ThreadContext;
61 class ArmInterruptPin;
62 class ArmSPI;
63 class ArmPPI;
64 class ArmSigInterruptPin;
65 
66 struct ArmInterruptPinParams;
67 struct ArmPPIParams;
68 struct ArmSPIParams;
69 struct ArmSigInterruptPinParams;
70 struct BaseGicParams;
71 
72 class BaseGic : public PioDevice
73 {
74  public:
75  typedef BaseGicParams Params;
76  enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 };
77 
78  BaseGic(const Params &p);
79  virtual ~BaseGic();
80  void init() override;
81 
82  const Params &params() const;
83 
92  virtual void sendInt(uint32_t num) = 0;
93 
100  virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
101  virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
102 
111  virtual void clearInt(uint32_t num) = 0;
112 
113  ArmSystem *
114  getSystem() const
115  {
116  return (ArmSystem *) sys;
117  }
118 
120  virtual bool supportsVersion(GicVersion version) = 0;
121 
122  protected:
125 };
126 
128 {
129  public:
130  virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
131  virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
132 
133  virtual void writeDistributor(ContextID ctx, Addr daddr,
134  uint32_t data) = 0;
135  virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
136 };
137 
146 {
147  public:
148  ArmInterruptPinGen(const ArmInterruptPinParams &p);
149 
150  virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
151 };
152 
159 {
160  public:
161  ArmSPIGen(const ArmSPIParams &p);
162 
163  ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
164  protected:
166 };
167 
174 {
175  public:
176  PARAMS(ArmPPI);
177  ArmPPIGen(const Params &p);
178 
179  ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
180  protected:
181  std::unordered_map<ContextID, ArmPPI*> pins;
182 };
183 
185 {
186  public:
187  ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p);
188 
189  ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
190  Port &getPort(const std::string &if_name,
191  PortID idx = InvalidPortID) override;
192 
193  protected:
195 };
196 
201 {
202  friend class ArmInterruptPinGen;
203  protected:
204  ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc);
205 
206  public: /* Public interface */
215 
217  uint32_t num() const { return intNum; }
218 
220  bool active() const { return _active; }
221 
223  virtual void raise() = 0;
225  virtual void clear() = 0;
226 
227  public: /* Serializable interface */
228  void serialize(CheckpointOut &cp) const override;
229  void unserialize(CheckpointIn &cp) override;
230 
231  protected:
238  ContextID targetContext() const;
239 
245 
248 
250  const uint32_t intNum;
251 
253  const ArmInterruptType triggerType;
254 
256  bool _active;
257 };
258 
259 class ArmSPI : public ArmInterruptPin
260 {
261  friend class ArmSPIGen;
262  private:
263  ArmSPI(const ArmSPIParams &p);
264 
265  public:
266  void raise() override;
267  void clear() override;
268 };
269 
270 class ArmPPI : public ArmInterruptPin
271 {
272  friend class ArmPPIGen;
273  private:
274  ArmPPI(const ArmPPIParams &p, ThreadContext *tc);
275 
276  public:
277  void raise() override;
278  void clear() override;
279 };
280 
282 {
283  friend class ArmSigInterruptPinGen;
284  private:
285  ArmSigInterruptPin(const ArmSigInterruptPinParams &p);
286 
288 
289  public:
290  void raise() override;
291  void clear() override;
292 };
293 
294 } // namespace gem5
295 
296 #endif // __DEV_ARM_BASE_GIC_H__
gem5::scmi::Platform
Definition: scmi_platform.hh:264
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::ArmInterruptPin::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: base_gic.cc:177
gem5::auxv::Platform
@ Platform
Definition: aux_vector.hh:84
gem5::ArmInterruptPin::threadContext
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition: base_gic.hh:244
gem5::BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:114
io_device.hh
gem5::BaseGic::~BaseGic
virtual ~BaseGic()
Definition: base_gic.cc:65
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmInterruptPin::intNum
const uint32_t intNum
Interrupt number to generate.
Definition: base_gic.hh:250
gem5::ArmSigInterruptPinGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:129
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
gem5::ArmSPIGen::ArmSPIGen
ArmSPIGen(const ArmSPIParams &p)
Definition: base_gic.cc:87
gem5::ArmSigInterruptPin::sigPin
std::vector< std::unique_ptr< IntSourcePin< ArmSigInterruptPinGen > > > sigPin
Definition: base_gic.hh:287
gem5::BaseGic::BaseGic
BaseGic(const Params &p)
Definition: base_gic.cc:51
gem5::BaseGic::GicVersion::GIC_V3
@ GIC_V3
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ArmInterruptPin::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: base_gic.cc:183
gem5::ArmSigInterruptPinGen::ArmSigInterruptPinGen
ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
Definition: base_gic.cc:124
gem5::ArmSigInterruptPinGen
Definition: base_gic.hh:184
gem5::ArmInterruptPin::num
uint32_t num() const
Get interrupt number.
Definition: base_gic.hh:217
gem5::BaseGic::platform
Platform * platform
Platform this GIC belongs to.
Definition: base_gic.hh:124
gem5::ArmSPI::ArmSPI
ArmSPI(const ArmSPIParams &p)
Definition: base_gic.cc:188
std::vector
STL vector class.
Definition: stl.hh:37
gem5::BaseGicRegisters::readCpu
virtual uint32_t readCpu(ContextID ctx, Addr daddr)=0
gem5::BaseGic::GicVersion::GIC_V4
@ GIC_V4
system.hh
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::ArmInterruptPin::ArmInterruptPin
ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc)
Definition: base_gic.cc:151
gem5::ArmPPIGen::PARAMS
PARAMS(ArmPPI)
gem5::ArmSPIGen
Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a ...
Definition: base_gic.hh:158
gem5::ArmInterruptPin::targetContext
ContextID targetContext() const
Get the target context ID of this interrupt.
Definition: base_gic.cc:169
gem5::BaseGicRegisters
Definition: base_gic.hh:127
gem5::ArmSigInterruptPin
Definition: base_gic.hh:281
gem5::ArmPPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:222
gem5::ArmPPIGen::pins
std::unordered_map< ContextID, ArmPPI * > pins
Definition: base_gic.hh:181
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::ArmSigInterruptPin::ArmSigInterruptPin
ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
Definition: base_gic.cc:228
gem5::BaseGic
Definition: base_gic.hh:72
gem5::ArmSigInterruptPin::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:242
gem5::BaseGicRegisters::writeCpu
virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data)=0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::BaseGic::clearPPInt
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
gem5::ArmSPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:93
gem5::ArmInterruptPin::_active
bool _active
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:256
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
gem5::BaseGic::supportsVersion
virtual bool supportsVersion(GicVersion version)=0
Check if version supported.
gem5::ArmPPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:104
gem5::BaseGic::params
const Params & params() const
Definition: base_gic.cc:77
gem5::ArmSigInterruptPinGen::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: base_gic.cc:135
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseGic::sendInt
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
gem5::BaseGic::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base_gic.cc:70
gem5::BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:75
gem5::ArmPPIGen::ArmPPIGen
ArmPPIGen(const Params &p)
Definition: base_gic.cc:98
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseGicRegisters::writeDistributor
virtual void writeDistributor(ContextID ctx, Addr daddr, uint32_t data)=0
gem5::BaseGicRegisters::readDistributor
virtual uint32_t readDistributor(ContextID ctx, Addr daddr)=0
gem5::ArmInterruptPin::platform
RealView *const platform
Arm platform to use for interrupt generation.
Definition: base_gic.hh:247
gem5::ArmSPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:202
gem5::BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:76
gem5::ArmPPI::ArmPPI
ArmPPI(const ArmPPIParams &p, ThreadContext *tc)
Definition: base_gic.cc:208
gem5::ArmInterruptPinGen::get
virtual ArmInterruptPin * get(ThreadContext *tc=nullptr)=0
gem5::ArmSigInterruptPinGen::pin
ArmSigInterruptPin * pin
Definition: base_gic.hh:194
gem5::ArmInterruptPin::setThreadContext
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
Definition: base_gic.cc:160
gem5::ArmSystem
Definition: system.hh:62
gem5::BaseGic::clearInt
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::ArmSPIGen::pin
ArmSPI * pin
Definition: base_gic.hh:165
gem5::RealView
Definition: realview.hh:59
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:200
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
intpin.hh
gem5::ArmInterruptPinGen::ArmInterruptPinGen
ArmInterruptPinGen(const ArmInterruptPinParams &p)
Definition: base_gic.cc:82
gem5::BaseGic::sendPPInt
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
gem5::ArmInterruptPin::active
bool active() const
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:220
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmSPI
Definition: base_gic.hh:259
gem5::BaseGic::GicVersion::GIC_V2
@ GIC_V2
gem5::ArmPPI
Definition: base_gic.hh:270
gem5::ArmInterruptPin::triggerType
const ArmInterruptType triggerType
Interrupt triggering type.
Definition: base_gic.hh:253
gem5::ArmPPIGen
Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of gen...
Definition: base_gic.hh:173
gem5::ArmInterruptPinGen
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition: base_gic.hh:145

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