gem5 v24.0.0.0
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base_gic.hh
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1/*
2 * Copyright (c) 2012-2013, 2017-2018, 2021 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
42#ifndef __DEV_ARM_BASE_GIC_H__
43#define __DEV_ARM_BASE_GIC_H__
44
45#include <memory>
46#include <unordered_map>
47#include <vector>
48
49#include "arch/arm/system.hh"
50#include "dev/intpin.hh"
51#include "dev/io_device.hh"
52
53#include "enums/ArmInterruptType.hh"
54
55namespace gem5
56{
57
58class Platform;
59class RealView;
60class ThreadContext;
61class ArmInterruptPin;
62class ArmSPI;
63class ArmPPI;
64class ArmSigInterruptPin;
65
66struct ArmInterruptPinParams;
67struct ArmPPIParams;
68struct ArmSPIParams;
69struct ArmSigInterruptPinParams;
70struct BaseGicParams;
71
72class BaseGic : public PioDevice
73{
74 public:
75 typedef BaseGicParams Params;
76 enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 };
77
78 BaseGic(const Params &p);
79 virtual ~BaseGic();
80 void init() override;
81
82 const Params &params() const;
83
92 virtual void sendInt(uint32_t num) = 0;
93
100 virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
101 virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
102
111 virtual void clearInt(uint32_t num) = 0;
112
113 ArmSystem *
114 getSystem() const
115 {
116 return (ArmSystem *) sys;
117 }
118
120 virtual bool supportsVersion(GicVersion version) = 0;
121
122 protected: // GIC state transfer
130 virtual bool blockIntUpdate() const { return false; }
131
132 protected:
135};
136
145{
146 public:
147 ArmInterruptPinGen(const ArmInterruptPinParams &p);
148
149 virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
150};
151
158{
159 public:
160 ArmSPIGen(const ArmSPIParams &p);
161
162 ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
163 protected:
165};
166
173{
174 public:
176 ArmPPIGen(const Params &p);
177
178 ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
179 protected:
180 std::unordered_map<ContextID, ArmPPI*> pins;
181};
182
184{
185 public:
186 ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p);
187
188 ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
189 Port &getPort(const std::string &if_name,
190 PortID idx = InvalidPortID) override;
191
192 protected:
194};
195
200{
201 friend class ArmInterruptPinGen;
202 protected:
203 ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc);
204
205 public: /* Public interface */
214
216 uint32_t num() const { return intNum; }
217
219 bool active() const { return _active; }
220
222 virtual void raise() = 0;
224 virtual void clear() = 0;
225
226 public: /* Serializable interface */
227 void serialize(CheckpointOut &cp) const override;
228 void unserialize(CheckpointIn &cp) override;
229
230 protected:
237 ContextID targetContext() const;
238
244
247
249 const uint32_t intNum;
250
252 const ArmInterruptType triggerType;
253
256};
257
259{
260 friend class ArmSPIGen;
261 private:
262 ArmSPI(const ArmSPIParams &p);
263
264 public:
265 void raise() override;
266 void clear() override;
267};
268
270{
271 friend class ArmPPIGen;
272 private:
273 ArmPPI(const ArmPPIParams &p, ThreadContext *tc);
274
275 public:
276 void raise() override;
277 void clear() override;
278};
279
281{
283 private:
284 ArmSigInterruptPin(const ArmSigInterruptPinParams &p);
285
287
288 public:
289 void raise() override;
290 void clear() override;
291};
292
293} // namespace gem5
294
295#endif // __DEV_ARM_BASE_GIC_H__
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition base_gic.hh:145
virtual ArmInterruptPin * get(ThreadContext *tc=nullptr)=0
ArmInterruptPinGen(const ArmInterruptPinParams &p)
Definition base_gic.cc:83
Generic representation of an Arm interrupt pin.
Definition base_gic.hh:200
const ArmInterruptType triggerType
Interrupt triggering type.
Definition base_gic.hh:252
virtual void clear()=0
Clear a signalled interrupt.
RealView *const platform
Arm platform to use for interrupt generation.
Definition base_gic.hh:246
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition base_gic.cc:183
ContextID targetContext() const
Get the target context ID of this interrupt.
Definition base_gic.cc:169
const uint32_t intNum
Interrupt number to generate.
Definition base_gic.hh:249
bool _active
True if interrupt pin is active, false otherwise.
Definition base_gic.hh:255
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition base_gic.cc:177
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
Definition base_gic.cc:160
virtual void raise()=0
Signal an interrupt.
ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc)
Definition base_gic.cc:152
bool active() const
True if interrupt pin is active, false otherwise.
Definition base_gic.hh:219
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition base_gic.hh:243
uint32_t num() const
Get interrupt number.
Definition base_gic.hh:216
Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of gen...
Definition base_gic.hh:173
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition base_gic.cc:105
std::unordered_map< ContextID, ArmPPI * > pins
Definition base_gic.hh:180
ArmPPIGen(const Params &p)
Definition base_gic.cc:99
void clear() override
Clear a signalled interrupt.
Definition base_gic.cc:224
ArmPPI(const ArmPPIParams &p, ThreadContext *tc)
Definition base_gic.cc:209
void raise() override
Signal an interrupt.
Definition base_gic.cc:217
Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a ...
Definition base_gic.hh:158
ArmSPIGen(const ArmSPIParams &p)
Definition base_gic.cc:88
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition base_gic.cc:94
void raise() override
Signal an interrupt.
Definition base_gic.cc:196
ArmSPI(const ArmSPIParams &p)
Definition base_gic.cc:188
void clear() override
Clear a signalled interrupt.
Definition base_gic.cc:203
ArmSigInterruptPin * pin
Definition base_gic.hh:193
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition base_gic.cc:130
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition base_gic.cc:136
ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
Definition base_gic.cc:125
std::vector< std::unique_ptr< IntSourcePin< ArmSigInterruptPinGen > > > sigPin
Definition base_gic.hh:286
ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
Definition base_gic.cc:230
void raise() override
Signal an interrupt.
Definition base_gic.cc:235
void clear() override
Clear a signalled interrupt.
Definition base_gic.cc:244
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition base_gic.cc:71
const Params & params() const
Definition base_gic.cc:78
virtual bool blockIntUpdate() const
When trasferring the state between two GICs (essentially writing architectural registers) an interrup...
Definition base_gic.hh:130
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
virtual bool supportsVersion(GicVersion version)=0
Check if version supported.
BaseGicParams Params
Definition base_gic.hh:75
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
virtual ~BaseGic()
Definition base_gic.cc:66
Platform * platform
Platform this GIC belongs to.
Definition base_gic.hh:134
ArmSystem * getSystem() const
Definition base_gic.hh:114
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
BaseGic(const Params &p)
Definition base_gic.cc:52
This device is the base class which all devices senstive to an address range inherit from.
Definition io_device.hh:103
Ports are used to interface objects to each other.
Definition port.hh:62
Basic support for object serialization.
Definition serialize.hh:170
Abstract superclass for simulation objects.
SimObjectParams Params
ThreadContext is the external interface to all thread state for anything outside of the CPU.
STL vector class.
Definition stl.hh:37
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
const PortID InvalidPortID
Definition types.hh:246
std::ostream CheckpointOut
Definition serialize.hh:66
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
int ContextID
Globally unique thread context ID.
Definition types.hh:239

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