42 #ifndef __DEV_ARM_BASE_GIC_H__
43 #define __DEV_ARM_BASE_GIC_H__
46 #include <unordered_map>
53 #include "enums/ArmInterruptType.hh"
61 class ArmInterruptPin;
64 class ArmSigInterruptPin;
66 struct ArmInterruptPinParams;
69 struct ArmSigInterruptPinParams;
180 std::unordered_map<ContextID, ArmPPI*>
pins;
222 virtual void raise() = 0;
265 void raise()
override;
266 void clear()
override;
276 void raise()
override;
277 void clear()
override;
289 void raise()
override;
290 void clear()
override;
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
ArmInterruptPinGen(const ArmInterruptPinParams &p)
virtual ArmInterruptPin * get(ThreadContext *tc=nullptr)=0
Generic representation of an Arm interrupt pin.
const ArmInterruptType triggerType
Interrupt triggering type.
virtual void clear()=0
Clear a signalled interrupt.
RealView *const platform
Arm platform to use for interrupt generation.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
ContextID targetContext() const
Get the target context ID of this interrupt.
const uint32_t intNum
Interrupt number to generate.
bool _active
True if interrupt pin is active, false otherwise.
void serialize(CheckpointOut &cp) const override
Serialize an object.
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc)
bool active() const
True if interrupt pin is active, false otherwise.
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
uint32_t num() const
Get interrupt number.
Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of gen...
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
std::unordered_map< ContextID, ArmPPI * > pins
ArmPPIGen(const Params &p)
void clear() override
Clear a signalled interrupt.
ArmPPI(const ArmPPIParams &p, ThreadContext *tc)
Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a ...
ArmSPIGen(const ArmSPIParams &p)
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
ArmSPI(const ArmSPIParams &p)
void clear() override
Clear a signalled interrupt.
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
ArmSigInterruptPinGen(const ArmSigInterruptPinParams &p)
std::vector< std::unique_ptr< IntSourcePin< ArmSigInterruptPinGen > > > sigPin
ArmSigInterruptPin(const ArmSigInterruptPinParams &p)
void clear() override
Clear a signalled interrupt.
ArmSystem * getSystem() const
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
const Params & params() const
virtual bool blockIntUpdate() const
When trasferring the state between two GICs (essentially writing architectural registers) an interrup...
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
virtual bool supportsVersion(GicVersion version)=0
Check if version supported.
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
Platform * platform
Platform this GIC belongs to.
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
This device is the base class which all devices senstive to an address range inherit from.
Ports are used to interface objects to each other.
Basic support for object serialization.
Abstract superclass for simulation objects.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
const PortID InvalidPortID
std::ostream CheckpointOut
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
int ContextID
Globally unique thread context ID.