gem5  v21.1.0.2
gem5::ExecContext Member List

This is the complete list of members for gem5::ExecContext, including all inherited members.

amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)gem5::ExecContextinlinevirtual
armMonitor(Addr address)=0gem5::ExecContextpure virtual
demapPage(Addr vaddr, uint64_t asn)=0gem5::ExecContextpure virtual
getAddrMonitor()=0gem5::ExecContextpure virtual
getHtmTransactionalDepth() const =0gem5::ExecContextpure virtual
getHtmTransactionUid() const =0gem5::ExecContextpure virtual
getWritableVecPredRegOperand(const StaticInst *si, int idx)=0gem5::ExecContextpure virtual
getWritableVecRegOperand(const StaticInst *si, int idx)=0gem5::ExecContextpure virtual
inHtmTransactionalState() const =0gem5::ExecContextpure virtual
initiateHtmCmd(Request::Flags flags)=0gem5::ExecContextpure virtual
initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)gem5::ExecContextinlinevirtual
initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)gem5::ExecContextinlinevirtual
mwait(PacketPtr pkt)=0gem5::ExecContextpure virtual
mwaitAtomic(ThreadContext *tc)=0gem5::ExecContextpure virtual
newHtmTransactionUid() const =0gem5::ExecContextpure virtual
pcState() const =0gem5::ExecContextpure virtual
pcState(const TheISA::PCState &val)=0gem5::ExecContextpure virtual
readCCRegOperand(const StaticInst *si, int idx)=0gem5::ExecContextpure virtual
readFloatRegOperandBits(const StaticInst *si, int idx)=0gem5::ExecContextpure virtual
readIntRegOperand(const StaticInst *si, int idx)=0gem5::ExecContextpure virtual
readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)gem5::ExecContextinlinevirtual
readMemAccPredicate() const =0gem5::ExecContextpure virtual
readMiscReg(int misc_reg)=0gem5::ExecContextpure virtual
readMiscRegOperand(const StaticInst *si, int idx)=0gem5::ExecContextpure virtual
readPredicate() const =0gem5::ExecContextpure virtual
readStCondFailures() const =0gem5::ExecContextpure virtual
readVecElemOperand(const StaticInst *si, int idx) const =0gem5::ExecContextpure virtual
readVecPredRegOperand(const StaticInst *si, int idx) const =0gem5::ExecContextpure virtual
readVecRegOperand(const StaticInst *si, int idx) const =0gem5::ExecContextpure virtual
setCCRegOperand(const StaticInst *si, int idx, RegVal val)=0gem5::ExecContextpure virtual
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)=0gem5::ExecContextpure virtual
setIntRegOperand(const StaticInst *si, int idx, RegVal val)=0gem5::ExecContextpure virtual
setMemAccPredicate(bool val)=0gem5::ExecContextpure virtual
setMiscReg(int misc_reg, RegVal val)=0gem5::ExecContextpure virtual
setMiscRegOperand(const StaticInst *si, int idx, RegVal val)=0gem5::ExecContextpure virtual
setPredicate(bool val)=0gem5::ExecContextpure virtual
setStCondFailures(unsigned int sc_failures)=0gem5::ExecContextpure virtual
setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val)=0gem5::ExecContextpure virtual
setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val)=0gem5::ExecContextpure virtual
setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val)=0gem5::ExecContextpure virtual
tcBase() const =0gem5::ExecContextpure virtual
writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0gem5::ExecContextpure virtual

Generated on Tue Sep 21 2021 12:27:35 for gem5 by doxygen 1.8.17