gem5::ExecContext Class Reference

The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model. More...

#include <exec_context.hh>

Inheritance diagram for gem5::ExecContext:

Public Member Functions
virtual RegVal	getRegOperand (const StaticInst *si, int idx)=0
virtual void	getRegOperand (const StaticInst *si, int idx, void *val)=0
virtual void *	getWritableRegOperand (const StaticInst *si, int idx)=0
virtual void	setRegOperand (const StaticInst *si, int idx, RegVal val)=0
virtual void	setRegOperand (const StaticInst *si, int idx, const void *val)=0
virtual ThreadContext *	tcBase () const =0
	Returns a pointer to the ThreadContext.
Misc Register Interfaces
virtual RegVal	readMiscRegOperand (const StaticInst *si, int idx)=0
virtual void	setMiscRegOperand (const StaticInst *si, int idx, RegVal val)=0
virtual RegVal	readMiscReg (int misc_reg)=0
	Reads a miscellaneous register, handling any architectural side effects due to reading that register.
virtual void	setMiscReg (int misc_reg, RegVal val)=0
	Sets a miscellaneous register, handling any architectural side effects due to writing that register.
PC Control
virtual const PCStateBase &	pcState () const =0
virtual void	pcState (const PCStateBase &val)=0
Memory Interface
virtual Fault	readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Perform an atomic memory read operation.
virtual Fault	initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)
	Initiate a timing memory read operation.
virtual Fault	initiateMemMgmtCmd (Request::Flags flags)=0
	Initiate a memory management command with no valid address.
virtual Fault	writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0
	For atomic-mode contexts, perform an atomic memory write operation.
virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)
virtual Fault	initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
	For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)
virtual void	setStCondFailures (unsigned int sc_failures)=0
	Sets the number of consecutive store conditional failures.
virtual unsigned int	readStCondFailures () const =0
	Returns the number of consecutive store conditional failures.
ARM-Specific Interfaces
virtual bool	readPredicate () const =0
virtual void	setPredicate (bool val)=0
virtual bool	readMemAccPredicate () const =0
virtual void	setMemAccPredicate (bool val)=0
virtual uint64_t	newHtmTransactionUid () const =0
virtual uint64_t	getHtmTransactionUid () const =0
virtual bool	inHtmTransactionalState () const =0
virtual uint64_t	getHtmTransactionalDepth () const =0
X86-Specific Interfaces
virtual void	demapPage (Addr vaddr, uint64_t asn)=0
	Invalidate a page in the DTLB and ITLB.
virtual void	armMonitor (Addr address)=0
virtual bool	mwait (PacketPtr pkt)=0
virtual void	mwaitAtomic (ThreadContext *tc)=0
virtual AddressMonitor *	getAddrMonitor ()=0

Detailed Description

The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model.

Register accessor methods in this class typically provide the index of the instruction's operand (e.g., 0 or 1), not the architectural register index, to simplify the implementation of register renaming. The architectural register index can be found by indexing into the instruction's own operand index table.

Note

The methods in this class typically take a raw pointer to the StaticInst is provided instead of a ref-counted StaticInstPtr to reduce overhead as an argument. This is fine as long as the implementation doesn't copy the pointer into any long-term storage (which is pretty hard to imagine they would have reason to do).

Definition at line 71 of file exec_context.hh.

Member Function Documentation

amoMem()

virtual Fault gem5::ExecContext::amoMem ( Addr addr, uint8_t * data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op )

inlinevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented in gem5::SimpleExecContext.

Definition at line 166 of file exec_context.hh.

References panic.

armMonitor()

virtual void gem5::ExecContext::armMonitor ( Addr address )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

demapPage()

virtual void gem5::ExecContext::demapPage ( Addr vaddr, uint64_t asn )

pure virtual

Invalidate a page in the DTLB and ITLB.

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

getAddrMonitor()

virtual AddressMonitor * gem5::ExecContext::getAddrMonitor ( )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

getHtmTransactionalDepth()

virtual uint64_t gem5::ExecContext::getHtmTransactionalDepth ( ) const

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

getHtmTransactionUid()

virtual uint64_t gem5::ExecContext::getHtmTransactionUid ( ) const

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

getRegOperand() [1/2]

virtual RegVal gem5::ExecContext::getRegOperand ( const StaticInst * si, int idx )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

Referenced by gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), and gem5::RiscvISA::VsSegIntrlvMicroInst::execute().

getRegOperand() [2/2]

virtual void gem5::ExecContext::getRegOperand ( const StaticInst * si, int idx, void * val )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

getWritableRegOperand()

virtual void * gem5::ExecContext::getWritableRegOperand ( const StaticInst * si, int idx )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

Referenced by gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), and gem5::RiscvISA::VsSegIntrlvMicroInst::execute().

inHtmTransactionalState()

virtual bool gem5::ExecContext::inHtmTransactionalState ( ) const

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

initiateMemAMO()

virtual Fault gem5::ExecContext::initiateMemAMO ( Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op )

inlinevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented in gem5::minor::ExecContext, and gem5::SimpleExecContext.

Definition at line 177 of file exec_context.hh.

References panic.

initiateMemMgmtCmd()

virtual Fault gem5::ExecContext::initiateMemMgmtCmd ( Request::Flags flags )

pure virtual

Initiate a memory management command with no valid address.

Currently, these instructions need to bypass squashing in the O3 model Examples include HTM commands and TLBI commands. e.g. tell Ruby we're starting/stopping a HTM transaction, or tell Ruby to issue a TLBI operation

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

initiateMemRead()

virtual Fault gem5::ExecContext::initiateMemRead ( Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > & byte_enable )

inlinevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented in gem5::minor::ExecContext, and gem5::SimpleExecContext.

Definition at line 138 of file exec_context.hh.

References panic.

Referenced by gem5::X86ISA::initiateMemRead().

mwait()

virtual bool gem5::ExecContext::mwait ( PacketPtr pkt )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

mwaitAtomic()

virtual void gem5::ExecContext::mwaitAtomic ( ThreadContext * tc )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

newHtmTransactionUid()

virtual uint64_t gem5::ExecContext::newHtmTransactionUid ( ) const

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

pcState() [1/2]

virtual const PCStateBase & gem5::ExecContext::pcState ( ) const

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

Referenced by gem5::DebugStep::execute(), gem5::DecoderFaultInst::execute(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::RiscvISA::SystemOp::executeEBreakOrSemihosting(), gem5::RiscvSemihosting::isSemihostingEBreak(), gem5::ArmISA::ArmStaticInst::readPC(), gem5::ArmISA::ArmStaticInst::setAIWNextPC(), gem5::ArmISA::ArmStaticInst::setIWNextPC(), and gem5::ArmISA::ArmStaticInst::setNextPC().

pcState() [2/2]

virtual void gem5::ExecContext::pcState ( const PCStateBase & val )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

readMem()

virtual Fault gem5::ExecContext::readMem ( Addr addr, uint8_t * data, unsigned int size, Request::Flags flags, const std::vector< bool > & byte_enable )

inlinevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented in gem5::SimpleExecContext.

Definition at line 124 of file exec_context.hh.

References panic.

Referenced by gem5::X86ISA::readMemAtomic(), and gem5::X86ISA::readPackedMemAtomic().

readMemAccPredicate()

virtual bool gem5::ExecContext::readMemAccPredicate ( ) const

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

readMiscReg()

virtual RegVal gem5::ExecContext::readMiscReg ( int misc_reg )

pure virtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

Referenced by gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::RiscvISA::VxsatMicroInst::execute(), and gem5::ArmISA::ISA::handleLockedSnoopHit().

readMiscRegOperand()

virtual RegVal gem5::ExecContext::readMiscRegOperand ( const StaticInst * si, int idx )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

readPredicate()

virtual bool gem5::ExecContext::readPredicate ( ) const

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

readStCondFailures()

virtual unsigned int gem5::ExecContext::readStCondFailures ( ) const

pure virtual

Returns the number of consecutive store conditional failures.

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

setMemAccPredicate()

virtual void gem5::ExecContext::setMemAccPredicate ( bool val )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

setMiscReg()

virtual void gem5::ExecContext::setMiscReg ( int misc_reg, RegVal val )

pure virtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

Referenced by gem5::RiscvISA::VxsatMicroInst::execute(), gem5::ArmISA::ISA::globalClearExclusive(), gem5::ArmISA::ISA::handleLockedRead(), and gem5::ArmISA::ISA::handleLockedSnoopHit().

setMiscRegOperand()

virtual void gem5::ExecContext::setMiscRegOperand ( const StaticInst * si, int idx, RegVal val )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

setPredicate()

virtual void gem5::ExecContext::setPredicate ( bool val )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

setRegOperand() [1/2]

virtual void gem5::ExecContext::setRegOperand ( const StaticInst * si, int idx, const void * val )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

setRegOperand() [2/2]

virtual void gem5::ExecContext::setRegOperand ( const StaticInst * si, int idx, RegVal val )

pure virtual

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

setStCondFailures()

virtual void gem5::ExecContext::setStCondFailures ( unsigned int sc_failures )

pure virtual

Sets the number of consecutive store conditional failures.

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

tcBase()

virtual ThreadContext * gem5::ExecContext::tcBase ( ) const

pure virtual

Returns a pointer to the ThreadContext.

Implemented in gem5::CheckerCPU, gem5::minor::ExecContext, gem5::o3::DynInst, and gem5::SimpleExecContext.

Referenced by gem5::DebugStep::execute(), gem5::McrMrcImplDefined::execute(), gem5::McrMrcMiscInst::execute(), gem5::MiscRegImplDefined64::execute(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), gem5::X86ISA::MicroHalt::execute(), gem5::RiscvISA::SystemOp::executeEBreakOrSemihosting(), gem5::ArmISA::ISA::globalClearExclusive(), gem5::ArmISA::ISA::handleLockedRead(), gem5::ArmISA::ISA::handleLockedSnoop(), gem5::ArmISA::ISA::handleLockedSnoopHit(), gem5::ArmISA::ISA::handleLockedWrite(), gem5::RiscvSemihosting::isSemihostingEBreak(), gem5::TlbiOp64::performTlbi(), gem5::TlbiOp::performTlbi(), gem5::MipsISA::readRegOtherThread(), gem5::MipsISA::setRegOtherThread(), and gem5::ArmISA::ArmStaticInst::softwareBreakpoint32().

writeMem()

virtual Fault gem5::ExecContext::writeMem ( uint8_t * data, unsigned int size, Addr addr, Request::Flags flags, uint64_t * res, const std::vector< bool > & byte_enable )

pure virtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implemented in gem5::minor::ExecContext, and gem5::SimpleExecContext.

Referenced by gem5::X86ISA::writeMemAtomic(), gem5::X86ISA::writeMemTiming(), and gem5::X86ISA::writePackedMem().

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The documentation for this class was generated from the following file:

• cpu/exec_context.hh