_busAddr | gem5::PciDevice | protected |
_drainManager | gem5::Drainable | private |
_drainState | gem5::Drainable | mutableprivate |
_name | gem5::Named | private |
_objNameResolver | gem5::SimObject | privatestatic |
_params | gem5::SimObject | protected |
acceptArp | gem5::NSGigE | protected |
acceptBroadcast | gem5::NSGigE | protected |
acceptMulticast | gem5::NSGigE | protected |
acceptPerfect | gem5::NSGigE | protected |
acceptUnicast | gem5::NSGigE | protected |
addStat(statistics::Info *info) | gem5::statistics::Group | |
addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
BARs | gem5::PciDevice | protected |
busAddr() const | gem5::PciDevice | inline |
cacheBlockSize() const | gem5::DmaDevice | inline |
clockDomain | gem5::Clocked | private |
Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
Clocked(Clocked &)=delete | gem5::Clocked | protected |
clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
clockPeriod() const | gem5::Clocked | inline |
clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
config | gem5::PciDevice | protected |
configDelay | gem5::PciDevice | protected |
cpuInterrupt() | gem5::NSGigE | protected |
cpuIntrAck() | gem5::NSGigE | inline |
cpuIntrClear() | gem5::NSGigE | protected |
cpuIntrPending() const | gem5::NSGigE | |
cpuIntrPost(Tick when) | gem5::NSGigE | protected |
cpuPendingIntr | gem5::NSGigE | protected |
CRDD | gem5::NSGigE | protected |
CTDD | gem5::NSGigE | protected |
curCycle() const | gem5::Clocked | inline |
currentSection() | gem5::Serializable | static |
cycle | gem5::Clocked | mutableprivate |
cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
deschedule(Event &event) | gem5::EventManager | inline |
deschedule(Event *event) | gem5::EventManager | inline |
devIntrChangeMask() | gem5::NSGigE | protected |
devIntrClear(uint32_t interrupts) | gem5::NSGigE | protected |
devIntrPost(uint32_t interrupts) | gem5::NSGigE | protected |
dmaDataFree | gem5::NSGigE | protected |
dmaDescFree | gem5::NSGigE | protected |
DmaDevice(const Params &p) | gem5::DmaDevice | |
dmaIdle enum value | gem5::NSGigE | |
dmaPending() const | gem5::DmaDevice | inline |
dmaPort | gem5::DmaDevice | protected |
dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
dmaReadDelay | gem5::NSGigE | protected |
dmaReadFactor | gem5::NSGigE | protected |
dmaReading enum value | gem5::NSGigE | |
dmaReadWaiting enum value | gem5::NSGigE | |
DmaState enum name | gem5::NSGigE | |
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
dmaWriteDelay | gem5::NSGigE | protected |
dmaWriteFactor | gem5::NSGigE | protected |
dmaWriteWaiting enum value | gem5::NSGigE | |
dmaWriting enum value | gem5::NSGigE | |
dmDrain() | gem5::Drainable | private |
dmDrainResume() | gem5::Drainable | private |
doRxDmaRead() | gem5::NSGigE | protected |
doRxDmaWrite() | gem5::NSGigE | protected |
doTxDmaRead() | gem5::NSGigE | protected |
doTxDmaWrite() | gem5::NSGigE | protected |
drain() override | gem5::SimObject | inlinevirtual |
Drainable() | gem5::Drainable | protected |
drainResume() override | gem5::NSGigE | virtual |
drainState() const | gem5::Drainable | inline |
eepromAddress | gem5::NSGigE | protected |
eepromBitsToRx | gem5::NSGigE | protected |
eepromClk | gem5::NSGigE | protected |
eepromData | gem5::NSGigE | protected |
eepromGetAddress enum value | gem5::NSGigE | |
eepromGetOpcode enum value | gem5::NSGigE | |
eepromKick() | gem5::NSGigE | protected |
eepromOpcode | gem5::NSGigE | protected |
eepromRead enum value | gem5::NSGigE | |
eepromStart enum value | gem5::NSGigE | |
EEPROMState enum name | gem5::NSGigE | |
eepromState | gem5::NSGigE | protected |
EtherDevBase(const Params ¶ms) | gem5::EtherDevBase | inline |
EtherDevice(const Params ¶ms) | gem5::EtherDevice | inline |
etherDeviceStats | gem5::EtherDevice | protected |
EventManager(EventManager &em) | gem5::EventManager | inline |
EventManager(EventManager *em) | gem5::EventManager | inline |
EventManager(EventQueue *eq) | gem5::EventManager | inline |
eventq | gem5::EventManager | protected |
eventQueue() const | gem5::EventManager | inline |
extstsEnable | gem5::NSGigE | protected |
find(const char *name) | gem5::SimObject | static |
frequency() const | gem5::Clocked | inline |
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
getAddrRanges() const override | gem5::PciDevice | virtual |
getBAR(Addr addr, int &num, Addr &offs) | gem5::PciDevice | inlineprotected |
getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::NSGigE | virtual |
getProbeManager() | gem5::SimObject | |
getSimObjectResolver() | gem5::SimObject | static |
getStatGroups() const | gem5::statistics::Group | |
getStats() const | gem5::statistics::Group | |
Group()=delete | gem5::statistics::Group | |
Group(const Group &)=delete | gem5::statistics::Group | |
Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
hostInterface | gem5::PciDevice | protected |
init() override | gem5::DmaDevice | virtual |
initState() | gem5::SimObject | virtual |
interface | gem5::NSGigE | protected |
interruptLine() const | gem5::PciDevice | inline |
intrClear() | gem5::PciDevice | inline |
intrDelay | gem5::NSGigE | protected |
intrEvent | gem5::NSGigE | protected |
intrPost() | gem5::PciDevice | inline |
intrTick | gem5::NSGigE | protected |
ioEnable | gem5::NSGigE | protected |
loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
memInvalidate() | gem5::SimObject | inlinevirtual |
memWriteback() | gem5::SimObject | inlinevirtual |
mergedParent | gem5::statistics::Group | private |
mergedStatGroups | gem5::statistics::Group | private |
mergeStatGroup(Group *block) | gem5::statistics::Group | |
msicap | gem5::PciDevice | protected |
MSICAP_BASE | gem5::PciDevice | protected |
msix_pba | gem5::PciDevice | protected |
MSIX_PBA_END | gem5::PciDevice | protected |
MSIX_PBA_OFFSET | gem5::PciDevice | protected |
msix_table | gem5::PciDevice | protected |
MSIX_TABLE_END | gem5::PciDevice | protected |
MSIX_TABLE_OFFSET | gem5::PciDevice | protected |
msixcap | gem5::PciDevice | protected |
MSIXCAP_BASE | gem5::PciDevice | protected |
MSIXCAP_ID_OFFSET | gem5::PciDevice | protected |
MSIXCAP_MPBA_OFFSET | gem5::PciDevice | protected |
MSIXCAP_MTAB_OFFSET | gem5::PciDevice | protected |
MSIXCAP_MXC_OFFSET | gem5::PciDevice | protected |
multicastHashEnable | gem5::NSGigE | protected |
name() const | gem5::Named | inlinevirtual |
Named(const std::string &name_) | gem5::Named | inline |
nextCycle() const | gem5::Clocked | inline |
notifyFork() | gem5::Drainable | inlinevirtual |
NSGigE(const Params ¶ms) | gem5::NSGigE | |
gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
PARAMS(NSGigE) | gem5::NSGigE | |
Params typedef | gem5::EtherDevBase | |
params() const | gem5::SimObject | inline |
path | gem5::Serializable | privatestatic |
PciDevice(const PciDeviceParams ¶ms) | gem5::PciDevice | |
pciToDma(Addr pci_addr) const | gem5::PciDevice | inline |
pioDelay | gem5::PciDevice | protected |
PioDevice(const Params &p) | gem5::PioDevice | |
pioPort | gem5::PioDevice | protected |
pmcap | gem5::PciDevice | protected |
PMCAP_BASE | gem5::PciDevice | protected |
PMCAP_ID_OFFSET | gem5::PciDevice | protected |
PMCAP_PC_OFFSET | gem5::PciDevice | protected |
PMCAP_PMCS_OFFSET | gem5::PciDevice | protected |
powerState | gem5::ClockedObject | |
preDumpStats() | gem5::statistics::Group | virtual |
probeManager | gem5::SimObject | private |
pxcap | gem5::PciDevice | protected |
PXCAP_BASE | gem5::PciDevice | protected |
read(PacketPtr pkt) override | gem5::NSGigE | virtual |
readConfig(PacketPtr pkt) | gem5::PciDevice | virtual |
recvPacket(EthPacketPtr packet) | gem5::NSGigE | |
regProbeListeners() | gem5::SimObject | virtual |
regProbePoints() | gem5::SimObject | virtual |
regs | gem5::NSGigE | protected |
regsReset() | gem5::NSGigE | protected |
regStats() | gem5::statistics::Group | virtual |
reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
resetClock() const | gem5::Clocked | inlineprotected |
resetStats() | gem5::statistics::Group | virtual |
resolveStat(std::string name) const | gem5::statistics::Group | |
rom | gem5::NSGigE | protected |
rxAdvance enum value | gem5::NSGigE | |
rxDelay | gem5::NSGigE | protected |
rxDesc32 | gem5::NSGigE | protected |
rxDesc64 | gem5::NSGigE | protected |
rxDescCnt | gem5::NSGigE | protected |
rxDescRead enum value | gem5::NSGigE | |
rxDescRefr enum value | gem5::NSGigE | |
rxDescWrite enum value | gem5::NSGigE | |
rxDmaAddr | gem5::NSGigE | protected |
rxDmaData | gem5::NSGigE | protected |
rxDmaFree | gem5::NSGigE | protected |
rxDmaLen | gem5::NSGigE | protected |
rxDmaReadDone() | gem5::NSGigE | protected |
rxDmaReadEvent | gem5::NSGigE | protected |
rxDmaState | gem5::NSGigE | protected |
rxDmaWriteDone() | gem5::NSGigE | protected |
rxDmaWriteEvent | gem5::NSGigE | protected |
rxDump() const | gem5::NSGigE | protected |
rxEnable | gem5::NSGigE | protected |
rxFifo | gem5::NSGigE | protected |
rxFifoBlock enum value | gem5::NSGigE | |
rxFilter(const EthPacketPtr &packet) | gem5::NSGigE | protected |
rxFilterEnable | gem5::NSGigE | protected |
rxFragPtr | gem5::NSGigE | protected |
rxFragWrite enum value | gem5::NSGigE | |
rxHalt | gem5::NSGigE | protected |
rxIdle enum value | gem5::NSGigE | |
rxKick() | gem5::NSGigE | protected |
rxKickEvent | gem5::NSGigE | protected |
rxKickTick | gem5::NSGigE | protected |
rxPacket | gem5::NSGigE | protected |
rxPacketBufPtr | gem5::NSGigE | protected |
rxPktBytes | gem5::NSGigE | protected |
rxReset() | gem5::NSGigE | protected |
RxState enum name | gem5::NSGigE | |
rxState | gem5::NSGigE | protected |
rxXferLen | gem5::NSGigE | protected |
schedule(Event &event, Tick when) | gem5::EventManager | inline |
schedule(Event *event, Tick when) | gem5::EventManager | inline |
Serializable() | gem5::Serializable | |
serialize(CheckpointOut &cp) const override | gem5::NSGigE | virtual |
serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
setCurTick(Tick newVal) | gem5::EventManager | inline |
setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
signalDrainDone() const | gem5::Drainable | inlineprotected |
SimObject(const Params &p) | gem5::SimObject | |
SimObjectList typedef | gem5::SimObject | private |
simObjectList | gem5::SimObject | privatestatic |
startup() | gem5::SimObject | virtual |
statGroups | gem5::statistics::Group | private |
stats | gem5::statistics::Group | private |
sys | gem5::PioDevice | protected |
tick | gem5::Clocked | mutableprivate |
ticksToCycles(Tick t) const | gem5::Clocked | inline |
transferDone() | gem5::NSGigE | |
transmit() | gem5::NSGigE | protected |
txAdvance enum value | gem5::NSGigE | |
txDelay | gem5::NSGigE | protected |
txDesc32 | gem5::NSGigE | protected |
txDesc64 | gem5::NSGigE | protected |
txDescCnt | gem5::NSGigE | protected |
txDescRead enum value | gem5::NSGigE | |
txDescRefr enum value | gem5::NSGigE | |
txDescWrite enum value | gem5::NSGigE | |
txDmaAddr | gem5::NSGigE | protected |
txDmaData | gem5::NSGigE | protected |
txDmaFree | gem5::NSGigE | protected |
txDmaLen | gem5::NSGigE | protected |
txDmaReadDone() | gem5::NSGigE | protected |
txDmaReadEvent | gem5::NSGigE | protected |
txDmaState | gem5::NSGigE | protected |
txDmaWriteDone() | gem5::NSGigE | protected |
txDmaWriteEvent | gem5::NSGigE | protected |
txDump() const | gem5::NSGigE | protected |
txEnable | gem5::NSGigE | protected |
txEvent | gem5::NSGigE | protected |
txEventTransmit() | gem5::NSGigE | inlineprotected |
txFifo | gem5::NSGigE | protected |
txFifoBlock enum value | gem5::NSGigE | |
txFragPtr | gem5::NSGigE | protected |
txFragRead enum value | gem5::NSGigE | |
txHalt | gem5::NSGigE | protected |
txIdle enum value | gem5::NSGigE | |
txKick() | gem5::NSGigE | protected |
txKickEvent | gem5::NSGigE | protected |
txKickTick | gem5::NSGigE | protected |
txPacket | gem5::NSGigE | protected |
txPacketBufPtr | gem5::NSGigE | protected |
txReset() | gem5::NSGigE | protected |
TxState enum name | gem5::NSGigE | |
txState | gem5::NSGigE | protected |
txXferLen | gem5::NSGigE | protected |
unserialize(CheckpointIn &cp) override | gem5::NSGigE | virtual |
unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
update() const | gem5::Clocked | inlineprivate |
updateClockPeriod() | gem5::Clocked | inline |
voltage() const | gem5::Clocked | inline |
wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
write(PacketPtr pkt) override | gem5::NSGigE | virtual |
writeConfig(PacketPtr pkt) override | gem5::NSGigE | virtual |
~Clocked() | gem5::Clocked | inlineprotectedvirtual |
~DmaDevice()=default | gem5::DmaDevice | virtual |
~Drainable() | gem5::Drainable | protectedvirtual |
~Group() | gem5::statistics::Group | virtual |
~Named()=default | gem5::Named | virtual |
~NSGigE() | gem5::NSGigE | |
~PioDevice() | gem5::PioDevice | virtual |
~Serializable() | gem5::Serializable | virtual |
~SimObject() | gem5::SimObject | virtual |