gem5  v21.1.0.2
gem5::NonCachingSimpleCPU Member List

This is the complete list of members for gem5::NonCachingSimpleCPU, including all inherited members.

_cacheLineSizegem5::BaseCPUprotected
_cpuIdgem5::BaseCPUprotected
_dataRequestorIdgem5::BaseCPUprotected
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_instRequestorIdgem5::BaseCPUprotected
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_pidgem5::BaseCPUprotected
_socketIdgem5::BaseCPUprotected
_statusgem5::BaseSimpleCPUprotected
_switchedOutgem5::BaseCPUprotected
_taskIdgem5::BaseCPUprotected
activateContext(ThreadID thread_num) overridegem5::AtomicSimpleCPUvirtual
activeThreadsgem5::BaseSimpleCPU
addressMonitorgem5::BaseCPUprivate
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
advancePC(const Fault &fault)gem5::BaseSimpleCPU
amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) overridegem5::AtomicSimpleCPUvirtual
armMonitor(ThreadID tid, Addr address)gem5::BaseCPU
AtomicSimpleCPU(const AtomicSimpleCPUParams &params)gem5::AtomicSimpleCPU
BaseCPU(const Params &params, bool is_checker=false)gem5::BaseCPU
BaseSimpleCPU(const BaseSimpleCPUParams &params)gem5::BaseSimpleCPU
baseStatsgem5::BaseCPU
branchPredgem5::BaseSimpleCPUprotected
cacheLineSize() constgem5::BaseCPUinline
checkergem5::BaseSimpleCPU
checkForInterrupts()gem5::BaseSimpleCPU
checkInterrupts(ThreadID tid) constgem5::BaseCPUinline
checkPcEventQueue()gem5::BaseSimpleCPUprotected
clearInterrupt(ThreadID tid, int int_num, int index)gem5::BaseCPUinline
clearInterrupts(ThreadID tid)gem5::BaseCPUinline
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
contextToThread(ContextID cid)gem5::BaseCPUinline
countInst()gem5::BaseSimpleCPU
CPU_STATE_ON enum valuegem5::BaseCPUprotected
CPU_STATE_SLEEP enum valuegem5::BaseCPUprotected
CPU_STATE_WAKEUP enum valuegem5::BaseCPUprotected
cpuId() constgem5::BaseCPUinline
cpuListgem5::BaseCPUprivatestatic
CPUState enum namegem5::BaseCPUprotected
curCycle() constgem5::Clockedinline
curMacroStaticInstgem5::BaseSimpleCPU
currentFunctionEndgem5::BaseCPUprivate
currentFunctionStartgem5::BaseCPUprivate
currentSection()gem5::Serializablestatic
curStaticInstgem5::BaseSimpleCPU
curThreadgem5::BaseSimpleCPUprotected
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
data_amo_reqgem5::AtomicSimpleCPUprotected
data_read_reqgem5::AtomicSimpleCPUprotected
data_write_reqgem5::AtomicSimpleCPUprotected
dataRequestorId() constgem5::BaseCPUinline
dcache_accessgem5::AtomicSimpleCPUprotected
dcache_latencygem5::AtomicSimpleCPUprotected
dcachePortgem5::AtomicSimpleCPUprotected
DcacheRetry enum valuegem5::BaseSimpleCPUprotected
DcacheWaitResponse enum valuegem5::BaseSimpleCPUprotected
DcacheWaitSwitch enum valuegem5::BaseSimpleCPUprotected
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
deschedulePowerGatingEvent()gem5::BaseCPU
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::AtomicSimpleCPUvirtual
Drainable()gem5::Drainableprotected
drainResume() overridegem5::AtomicSimpleCPUvirtual
drainState() constgem5::Drainableinline
DTBWaitResponse enum valuegem5::BaseSimpleCPUprotected
enableFunctionTrace()gem5::BaseCPUprivate
enterPwrGating()gem5::BaseCPUprotected
enterPwrGatingEventgem5::BaseCPUprotected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
Faulting enum valuegem5::BaseSimpleCPUprotected
fetchInstMem() overridegem5::NonCachingSimpleCPUprotectedvirtual
find(const char *name)gem5::SimObjectstatic
findContext(ThreadContext *tc)gem5::BaseCPU
flushTLBs()gem5::BaseCPU
frequency() constgem5::Clockedinline
functionEntryTickgem5::BaseCPUprivate
functionTraceStreamgem5::BaseCPUprivate
functionTracingEnabledgem5::BaseCPUprivate
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
genMemFragmentRequest(const RequestPtr &req, Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) constgem5::AtomicSimpleCPU
getContext(int tn)gem5::BaseCPUinlinevirtual
getCpuAddrMonitor(ThreadID tid)gem5::BaseCPUinline
getCurrentInstCount(ThreadID tid)gem5::BaseCPU
getDataPort() overridegem5::AtomicSimpleCPUinlineprotectedvirtual
getInstPort() overridegem5::AtomicSimpleCPUinlineprotectedvirtual
getInterruptController(ThreadID tid)gem5::BaseCPUinline
getPid() constgem5::BaseCPUinline
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::BaseCPUvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getTracer()gem5::BaseCPUinline
globalStatsgem5::BaseCPUprotectedstatic
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
haltContext(ThreadID thread_num) overridegem5::BaseSimpleCPUvirtual
htmSendAbortSignal(HtmFailureFaultCause cause) overridegem5::AtomicSimpleCPUinlinevirtual
icachePortgem5::AtomicSimpleCPUprotected
IcacheRetry enum valuegem5::BaseSimpleCPUprotected
IcacheWaitResponse enum valuegem5::BaseSimpleCPUprotected
IcacheWaitSwitch enum valuegem5::BaseSimpleCPUprotected
Idle enum valuegem5::BaseSimpleCPUprotected
ifetch_reqgem5::AtomicSimpleCPUprotected
init() overridegem5::AtomicSimpleCPUvirtual
initiateHtmCmd(Request::Flags flags) overridegem5::AtomicSimpleCPUinlinevirtual
initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)gem5::BaseSimpleCPUinlinevirtual
initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())gem5::BaseSimpleCPUinlinevirtual
initState()gem5::SimObjectvirtual
instCntgem5::BaseCPUprotected
instCount()gem5::BaseCPUinline
instRequestorId() constgem5::BaseCPUinline
interruptsgem5::BaseCPUprotected
invldPidgem5::BaseCPUstatic
isCpuDrained() constgem5::AtomicSimpleCPUinlineprotected
ITBWaitResponse enum valuegem5::BaseSimpleCPUprotected
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
lockedgem5::AtomicSimpleCPUprotected
memBackdoorsgem5::NonCachingSimpleCPUprotected
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
mwait(ThreadID tid, PacketPtr pkt)gem5::BaseCPU
mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)gem5::BaseCPU
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p)gem5::NonCachingSimpleCPU
notifyFork()gem5::Drainableinlinevirtual
numContexts()gem5::BaseCPUinline
numSimulatedCPUs()gem5::BaseCPUinlinestatic
numSimulatedInsts()gem5::BaseCPUinlinestatic
numSimulatedOps()gem5::BaseCPUinlinestatic
numThreadsgem5::BaseCPU
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
PARAMS(BaseCPU)gem5::BaseCPU
Params typedefgem5::ClockedObject
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
pmuProbePoint(const char *name)gem5::BaseCPUprotected
postExecute()gem5::BaseSimpleCPU
postInterrupt(ThreadID tid, int int_num, int index)gem5::BaseCPU
powerGatingOnIdlegem5::BaseCPUprotected
powerStategem5::ClockedObject
ppActiveCyclesgem5::BaseCPUprotected
ppAllCyclesgem5::BaseCPUprotected
ppCommitgem5::AtomicSimpleCPUprotected
ppRetiredBranchesgem5::BaseCPUprotected
ppRetiredInstsgem5::BaseCPUprotected
ppRetiredInstsPCgem5::BaseCPUprotected
ppRetiredLoadsgem5::BaseCPUprotected
ppRetiredStoresgem5::BaseCPUprotected
ppSleepinggem5::BaseCPUprotected
preDumpStats()gem5::statistics::Groupvirtual
preExecute()gem5::BaseSimpleCPU
previousCyclegem5::BaseCPUprotected
previousStategem5::BaseCPUprotected
printAddr(Addr a)gem5::AtomicSimpleCPU
probeInstCommit(const StaticInstPtr &inst, Addr pc)gem5::BaseCPUvirtual
probeManagergem5::SimObjectprivate
pwrGatingLatencygem5::BaseCPUprotected
readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) overridegem5::AtomicSimpleCPUvirtual
registerThreadContexts()gem5::BaseCPU
regProbeListeners()gem5::SimObjectvirtual
regProbePoints() overridegem5::AtomicSimpleCPUvirtual
regStats() overridegem5::BaseCPUvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats() overridegem5::BaseSimpleCPUvirtual
resolveStat(std::string name) constgem5::statistics::Group
Running enum valuegem5::BaseSimpleCPUprotected
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
scheduleInstStop(ThreadID tid, Counter insts, const char *cause)gem5::BaseCPU
schedulePowerGatingEvent()gem5::BaseCPU
sendPacket(RequestPort &port, const PacketPtr &pkt) overridegem5::NonCachingSimpleCPUprotectedvirtual
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::BaseCPUvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
serializeThread(CheckpointOut &cp, ThreadID tid) const overridegem5::BaseSimpleCPUvirtual
serviceInstCountEvents()gem5::BaseSimpleCPU
setCurTick(Tick newVal)gem5::EventManagerinline
setPid(uint32_t pid)gem5::BaseCPUinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
setupFetchRequest(const RequestPtr &req)gem5::BaseSimpleCPU
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
simulate_data_stallsgem5::AtomicSimpleCPUprotected
simulate_inst_stallsgem5::AtomicSimpleCPUprotected
socketId() constgem5::BaseCPUinline
startup() overridegem5::BaseCPUvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
Status enum namegem5::BaseSimpleCPUprotected
suspendContext(ThreadID thread_num) overridegem5::AtomicSimpleCPUvirtual
swapActiveThread()gem5::BaseSimpleCPUprotected
switchedOut() constgem5::BaseCPUinline
switchOut() overridegem5::AtomicSimpleCPUvirtual
syscallRetryLatencygem5::BaseCPU
systemgem5::BaseCPU
takeOverFrom(BaseCPU *old_cpu) overridegem5::AtomicSimpleCPUvirtual
taskId() constgem5::BaseCPUinline
taskId(uint32_t id)gem5::BaseCPUinline
threadContextsgem5::BaseCPUprotected
threadInfogem5::BaseSimpleCPU
threadSnoop(PacketPtr pkt, ThreadID sender)gem5::AtomicSimpleCPUprotected
tick()gem5::AtomicSimpleCPUprotected
tickEventgem5::AtomicSimpleCPUprotected
ticksToCycles(Tick t) constgem5::Clockedinline
totalInsts() const overridegem5::BaseSimpleCPUvirtual
totalOps() const overridegem5::BaseSimpleCPUvirtual
traceDatagem5::BaseSimpleCPU
traceFault()gem5::BaseSimpleCPUprotected
traceFunctions(Addr pc)gem5::BaseCPUinline
traceFunctionsInternal(Addr pc)gem5::BaseCPUprivate
tracergem5::BaseCPUprotected
tryCompleteDrain()gem5::AtomicSimpleCPUprotected
unserialize(CheckpointIn &cp) overridegem5::BaseCPUvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
unserializeThread(CheckpointIn &cp, ThreadID tid) overridegem5::BaseSimpleCPUvirtual
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
updateCycleCounters(CPUState state)gem5::BaseCPUinlineprotected
verifyMemoryMode() const overridegem5::NonCachingSimpleCPUvirtual
voltage() constgem5::Clockedinline
wakeup(ThreadID tid) overridegem5::BaseSimpleCPUvirtual
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
widthgem5::AtomicSimpleCPUprotected
workItemBegin()gem5::BaseCPUinline
workItemEnd()gem5::BaseCPUinline
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) overridegem5::AtomicSimpleCPUvirtual
zeroReggem5::BaseSimpleCPUprotected
~AtomicSimpleCPU()gem5::AtomicSimpleCPUvirtual
~BaseCPU()gem5::BaseCPUvirtual
~BaseSimpleCPU()gem5::BaseSimpleCPUvirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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