gem5  v21.1.0.2
Public Member Functions | Public Attributes | Protected Types | Protected Member Functions | Protected Attributes | List of all members
gem5::BaseSimpleCPU Class Referenceabstract

#include <base.hh>

Inheritance diagram for gem5::BaseSimpleCPU:
gem5::BaseCPU gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named gem5::AtomicSimpleCPU gem5::TimingSimpleCPU gem5::NonCachingSimpleCPU

Public Member Functions

 BaseSimpleCPU (const BaseSimpleCPUParams &params)
 
virtual ~BaseSimpleCPU ()
 
void wakeup (ThreadID tid) override
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
void checkForInterrupts ()
 
void setupFetchRequest (const RequestPtr &req)
 
void serviceInstCountEvents ()
 
void preExecute ()
 
void postExecute ()
 
void advancePC (const Fault &fault)
 
void haltContext (ThreadID thread_num) override
 Notify the CPU that the indicated context is now halted. More...
 
void resetStats () override
 Callback to reset stats. More...
 
virtual Fault readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
 
virtual Fault initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())
 
virtual Fault writeMem (uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >())
 
virtual Fault amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 
virtual Fault initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)
 
void countInst ()
 
Counter totalInsts () const override
 
Counter totalOps () const override
 
void serializeThread (CheckpointOut &cp, ThreadID tid) const override
 Serialize a single thread. More...
 
void unserializeThread (CheckpointIn &cp, ThreadID tid) override
 Unserialize one thread. More...
 
virtual Fault initiateHtmCmd (Request::Flags flags)=0
 Hardware transactional memory commands (HtmCmds), e.g. More...
 
virtual void htmSendAbortSignal (HtmFailureFaultCause cause)=0
 This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away. More...
 
- Public Member Functions inherited from gem5::BaseCPU
virtual PortgetDataPort ()=0
 Purely virtual method that returns a reference to the data port. More...
 
virtual PortgetInstPort ()=0
 Purely virtual method that returns a reference to the instruction port. More...
 
int cpuId () const
 Reads this CPU's ID. More...
 
uint32_t socketId () const
 Reads this CPU's Socket ID. More...
 
RequestorID dataRequestorId () const
 Reads this CPU's unique data requestor ID. More...
 
RequestorID instRequestorId () const
 Reads this CPU's unique instruction requestor ID. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port on this CPU. More...
 
uint32_t taskId () const
 Get cpu task id. More...
 
void taskId (uint32_t id)
 Set cpu task id. More...
 
uint32_t getPid () const
 
void setPid (uint32_t pid)
 
void workItemBegin ()
 
void workItemEnd ()
 
Tick instCount ()
 
BaseInterruptsgetInterruptController (ThreadID tid)
 
void postInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupts (ThreadID tid)
 
bool checkInterrupts (ThreadID tid) const
 
Trace::InstTracergetTracer ()
 Provide access to the tracer pointer. More...
 
virtual void activateContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now active. More...
 
virtual void suspendContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now suspended. More...
 
int findContext (ThreadContext *tc)
 Given a Thread Context pointer return the thread num. More...
 
virtual ThreadContextgetContext (int tn)
 Given a thread num get tho thread context for it. More...
 
unsigned numContexts ()
 Get the number of thread contexts available. More...
 
ThreadID contextToThread (ContextID cid)
 Convert ContextID to threadID. More...
 
 PARAMS (BaseCPU)
 
 BaseCPU (const Params &params, bool is_checker=false)
 
virtual ~BaseCPU ()
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
void regStats () override
 Callback to set stat parameters. More...
 
void regProbePoints () override
 Register probe points for this object. More...
 
void registerThreadContexts ()
 
void deschedulePowerGatingEvent ()
 
void schedulePowerGatingEvent ()
 
virtual void switchOut ()
 Prepare for another CPU to take over execution. More...
 
virtual void takeOverFrom (BaseCPU *cpu)
 Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...
 
void flushTLBs ()
 Flush all TLBs in the CPU. More...
 
bool switchedOut () const
 Determine if the CPU is switched out. More...
 
virtual void verifyMemoryMode () const
 Verify that the system is in a memory mode supported by the CPU. More...
 
unsigned int cacheLineSize () const
 Get the cache line size of the system. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize this object to the given output stream. More...
 
void unserialize (CheckpointIn &cp) override
 Reconstruct the state of this object from a checkpoint. More...
 
void scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
 Schedule an event that exits the simulation loops after a predefined number of instructions. More...
 
uint64_t getCurrentInstCount (ThreadID tid)
 Get the number of instructions executed by the specified thread on this CPU. More...
 
void traceFunctions (Addr pc)
 
void armMonitor (ThreadID tid, Addr address)
 
bool mwait (ThreadID tid, PacketPtr pkt)
 
void mwaitAtomic (ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
 
AddressMonitorgetCpuAddrMonitor (ThreadID tid)
 
virtual void probeInstCommit (const StaticInstPtr &inst, Addr pc)
 Helper method to trigger PMU probes for a committed instruction. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Public Attributes

Trace::InstRecordtraceData
 
CheckerCPUchecker
 
std::vector< SimpleExecContext * > threadInfo
 
std::list< ThreadIDactiveThreads
 
StaticInstPtr curStaticInst
 Current instruction. More...
 
StaticInstPtr curMacroStaticInst
 
- Public Attributes inherited from gem5::BaseCPU
ThreadID numThreads
 Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...
 
Systemsystem
 
gem5::BaseCPU::BaseCPUStats baseStats
 
Cycles syscallRetryLatency
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 

Protected Types

enum  Status {
  Idle, Running, Faulting, ITBWaitResponse,
  IcacheRetry, IcacheWaitResponse, IcacheWaitSwitch, DTBWaitResponse,
  DcacheRetry, DcacheWaitResponse, DcacheWaitSwitch
}
 
- Protected Types inherited from gem5::BaseCPU
enum  CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }
 

Protected Member Functions

void checkPcEventQueue ()
 
void swapActiveThread ()
 
void traceFault ()
 Handler used when encountering a fault; its purpose is to tear down the InstRecord. More...
 
- Protected Member Functions inherited from gem5::BaseCPU
void updateCycleCounters (CPUState state)
 base method keeping track of cycle progression More...
 
void enterPwrGating ()
 
probing::PMUUPtr pmuProbePoint (const char *name)
 Helper method to instantiate probe points belonging to this object. More...
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 

Protected Attributes

ThreadID curThread
 
branch_prediction::BPredUnitbranchPred
 
const RegIndex zeroReg
 
Status _status
 
- Protected Attributes inherited from gem5::BaseCPU
Tick instCnt
 Instruction count used for SPARC misc register. More...
 
int _cpuId
 
const uint32_t _socketId
 Each cpu will have a socket ID that corresponds to its physical location in the system. More...
 
RequestorID _instRequestorId
 instruction side request id that must be placed in all requests More...
 
RequestorID _dataRequestorId
 data side request id that must be placed in all requests More...
 
uint32_t _taskId
 An intrenal representation of a task identifier within gem5. More...
 
uint32_t _pid
 The current OS process ID that is executing on this processor. More...
 
bool _switchedOut
 Is the CPU switched out or active? More...
 
const unsigned int _cacheLineSize
 Cache the cache line size that we get from the system. More...
 
std::vector< BaseInterrupts * > interrupts
 
std::vector< ThreadContext * > threadContexts
 
Trace::InstTracertracer
 
Cycles previousCycle
 
CPUState previousState
 
const Cycles pwrGatingLatency
 
const bool powerGatingOnIdle
 
EventFunctionWrapper enterPwrGatingEvent
 
probing::PMUUPtr ppRetiredInsts
 Instruction commit probe point. More...
 
probing::PMUUPtr ppRetiredInstsPC
 
probing::PMUUPtr ppRetiredLoads
 Retired load instructions. More...
 
probing::PMUUPtr ppRetiredStores
 Retired store instructions. More...
 
probing::PMUUPtr ppRetiredBranches
 Retired branches (any type) More...
 
probing::PMUUPtr ppAllCycles
 CPU cycle counter even if any thread Context is suspended. More...
 
probing::PMUUPtr ppActiveCycles
 CPU cycle counter, only counts if any thread contexts is active. More...
 
ProbePointArg< bool > * ppSleeping
 ProbePoint that signals transitions of threadContexts sets. More...
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Additional Inherited Members

- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 
- Static Public Member Functions inherited from gem5::BaseCPU
static int numSimulatedCPUs ()
 
static Counter numSimulatedInsts ()
 
static Counter numSimulatedOps ()
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 
- Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t invldPid = std::numeric_limits<uint32_t>::max()
 Invalid or unknown Pid. More...
 
- Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStatsglobalStats
 Pointer to the global stat structure. More...
 

Detailed Description

Definition at line 80 of file base.hh.

Member Enumeration Documentation

◆ Status

Enumerator
Idle 
Running 
Faulting 
ITBWaitResponse 
IcacheRetry 
IcacheWaitResponse 
IcacheWaitSwitch 
DTBWaitResponse 
DcacheRetry 
DcacheWaitResponse 
DcacheWaitSwitch 

Definition at line 108 of file base.hh.

Constructor & Destructor Documentation

◆ BaseSimpleCPU()

gem5::BaseSimpleCPU::BaseSimpleCPU ( const BaseSimpleCPUParams &  params)

◆ ~BaseSimpleCPU()

gem5::BaseSimpleCPU::~BaseSimpleCPU ( )
virtual

Definition at line 195 of file base.cc.

Member Function Documentation

◆ advancePC()

void gem5::BaseSimpleCPU::advancePC ( const Fault fault)

◆ amoMem()

virtual Fault gem5::BaseSimpleCPU::amoMem ( Addr  addr,
uint8_t *  data,
unsigned  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlinevirtual

Reimplemented in gem5::AtomicSimpleCPU.

Definition at line 169 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::amoMem().

◆ checkForInterrupts()

void gem5::BaseSimpleCPU::checkForInterrupts ( )

◆ checkPcEventQueue()

void gem5::BaseSimpleCPU::checkPcEventQueue ( )
protected

◆ countInst()

void gem5::BaseSimpleCPU::countInst ( )

◆ haltContext()

void gem5::BaseSimpleCPU::haltContext ( ThreadID  thread_num)
overridevirtual

Notify the CPU that the indicated context is now halted.

Reimplemented from gem5::BaseCPU.

Definition at line 200 of file base.cc.

References gem5::BaseCPU::CPU_STATE_SLEEP, gem5::BaseCPU::suspendContext(), and gem5::BaseCPU::updateCycleCounters().

◆ htmSendAbortSignal()

virtual void gem5::BaseSimpleCPU::htmSendAbortSignal ( HtmFailureFaultCause  cause)
pure virtual

This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

This is called in the transaction's very last breath in the core. Afterwards, the core throws away its speculative state and resumes execution at the point the transaction started, i.e. reverses time. When instruction execution resumes, the core expects the memory subsystem to be in a stable, i.e. pre-speculative, state as well.

Implemented in gem5::TimingSimpleCPU, and gem5::AtomicSimpleCPU.

Referenced by gem5::SimpleThread::htmAbortTransaction().

◆ init()

void gem5::BaseSimpleCPU::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::BaseCPU.

Reimplemented in gem5::TimingSimpleCPU.

Definition at line 122 of file base.cc.

References gem5::BaseCPU::init(), and gem5::BaseCPU::threadContexts.

Referenced by gem5::AtomicSimpleCPU::init(), and gem5::TimingSimpleCPU::init().

◆ initiateHtmCmd()

virtual Fault gem5::BaseSimpleCPU::initiateHtmCmd ( Request::Flags  flags)
pure virtual

Hardware transactional memory commands (HtmCmds), e.g.

start a transaction and commit a transaction, are memory operations but are neither really (true) loads nor stores. For this reason the interface is extended and initiateHtmCmd() is used to instigate the command.

Implemented in gem5::TimingSimpleCPU, and gem5::AtomicSimpleCPU.

Referenced by gem5::SimpleExecContext::initiateHtmCmd().

◆ initiateMemAMO()

virtual Fault gem5::BaseSimpleCPU::initiateMemAMO ( Addr  addr,
unsigned  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlinevirtual

Reimplemented in gem5::TimingSimpleCPU.

Definition at line 176 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::initiateMemAMO().

◆ initiateMemRead()

virtual Fault gem5::BaseSimpleCPU::initiateMemRead ( Addr  addr,
unsigned  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
inlinevirtual

Reimplemented in gem5::TimingSimpleCPU.

Definition at line 154 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::initiateMemRead().

◆ postExecute()

void gem5::BaseSimpleCPU::postExecute ( )

Definition at line 394 of file base.cc.

References curStaticInst, curThread, gem5::Trace::InstRecord::dump(), gem5::SimpleExecContext::execContextStats, gem5::FullSystem, gem5::StaticInst::isAtomic(), gem5::StaticInst::isCall(), gem5::StaticInst::isCondCtrl(), gem5::StaticInst::isControl(), gem5::StaticInst::isFloating(), gem5::StaticInst::isInteger(), gem5::StaticInst::isLoad(), gem5::StaticInst::isMemRef(), gem5::StaticInst::isReturn(), gem5::StaticInst::isStore(), gem5::StaticInst::isVector(), gem5::SimpleExecContext::ExecContextStats::numBranches, gem5::SimpleExecContext::ExecContextStats::numCallsReturns, gem5::SimpleExecContext::ExecContextStats::numCondCtrlInsts, gem5::SimpleExecContext::ExecContextStats::numFpAluAccesses, gem5::SimpleExecContext::ExecContextStats::numFpInsts, gem5::SimpleExecContext::ExecContextStats::numIntAluAccesses, gem5::SimpleExecContext::ExecContextStats::numIntInsts, gem5::SimpleExecContext::numLoad, gem5::SimpleExecContext::ExecContextStats::numLoadInsts, gem5::SimpleExecContext::ExecContextStats::numMemRefs, gem5::SimpleExecContext::ExecContextStats::numStoreInsts, gem5::SimpleExecContext::ExecContextStats::numVecAluAccesses, gem5::SimpleExecContext::ExecContextStats::numVecInsts, gem5::StaticInst::opClass(), gem5::MipsISA::pc, gem5::BaseCPU::probeInstCommit(), gem5::SimpleExecContext::ExecContextStats::statExecutedInstType, gem5::BaseCPU::threadContexts, threadInfo, traceData, and gem5::BaseCPU::traceFunctions().

Referenced by gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::AtomicSimpleCPU::tick(), and gem5::TimingSimpleCPU::translationFault().

◆ preExecute()

void gem5::BaseSimpleCPU::preExecute ( )

◆ readMem()

virtual Fault gem5::BaseSimpleCPU::readMem ( Addr  addr,
uint8_t *  data,
unsigned  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
inlinevirtual

Reimplemented in gem5::AtomicSimpleCPU.

Definition at line 147 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::readMem().

◆ resetStats()

void gem5::BaseSimpleCPU::resetStats ( )
overridevirtual

Callback to reset stats.

Reimplemented from gem5::statistics::Group.

Definition at line 208 of file base.cc.

References _status, Idle, gem5::statistics::Group::resetStats(), and threadInfo.

◆ serializeThread()

void gem5::BaseSimpleCPU::serializeThread ( CheckpointOut cp,
ThreadID  tid 
) const
overridevirtual

Serialize a single thread.

Parameters
cpThe stream to serialize to.
tidID of the current thread.

Reimplemented from gem5::BaseCPU.

Definition at line 217 of file base.cc.

References _status, Idle, Running, and threadInfo.

◆ serviceInstCountEvents()

void gem5::BaseSimpleCPU::serviceInstCountEvents ( )

◆ setupFetchRequest()

void gem5::BaseSimpleCPU::setupFetchRequest ( const RequestPtr req)

◆ swapActiveThread()

void gem5::BaseSimpleCPU::swapActiveThread ( )
protected

◆ totalInsts()

Counter gem5::BaseSimpleCPU::totalInsts ( ) const
overridevirtual

Implements gem5::BaseCPU.

Definition at line 174 of file base.cc.

References threadInfo.

◆ totalOps()

Counter gem5::BaseSimpleCPU::totalOps ( ) const
overridevirtual

Implements gem5::BaseCPU.

Definition at line 185 of file base.cc.

References threadInfo.

◆ traceFault()

void gem5::BaseSimpleCPU::traceFault ( )
protected

Handler used when encountering a fault; its purpose is to tear down the InstRecord.

If a fault is meant to be traced, the handler won't delete the record and it will annotate the record as coming from a faulting instruction.

Definition at line 247 of file base.cc.

References gem5::Trace::InstRecord::setFaulting(), and traceData.

Referenced by gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::AtomicSimpleCPU::tick(), and gem5::TimingSimpleCPU::translationFault().

◆ unserializeThread()

void gem5::BaseSimpleCPU::unserializeThread ( CheckpointIn cp,
ThreadID  tid 
)
overridevirtual

Unserialize one thread.

Parameters
cpThe checkpoint use.
tidID of the current thread.

Reimplemented from gem5::BaseCPU.

Definition at line 225 of file base.cc.

References threadInfo.

◆ wakeup()

void gem5::BaseSimpleCPU::wakeup ( ThreadID  tid)
overridevirtual

◆ writeMem()

virtual Fault gem5::BaseSimpleCPU::writeMem ( uint8_t *  data,
unsigned  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
inlinevirtual

Reimplemented in gem5::TimingSimpleCPU, and gem5::AtomicSimpleCPU.

Definition at line 161 of file base.hh.

References panic.

Referenced by gem5::SimpleExecContext::writeMem().

Member Data Documentation

◆ _status

Status gem5::BaseSimpleCPU::_status
protected

◆ activeThreads

std::list<ThreadID> gem5::BaseSimpleCPU::activeThreads

◆ branchPred

branch_prediction::BPredUnit* gem5::BaseSimpleCPU::branchPred
protected

Definition at line 84 of file base.hh.

Referenced by advancePC(), and preExecute().

◆ checker

CheckerCPU* gem5::BaseSimpleCPU::checker

Definition at line 98 of file base.hh.

Referenced by BaseSimpleCPU().

◆ curMacroStaticInst

StaticInstPtr gem5::BaseSimpleCPU::curMacroStaticInst

◆ curStaticInst

StaticInstPtr gem5::BaseSimpleCPU::curStaticInst

◆ curThread

ThreadID gem5::BaseSimpleCPU::curThread
protected

◆ threadInfo

std::vector<SimpleExecContext*> gem5::BaseSimpleCPU::threadInfo

Definition at line 100 of file base.hh.

Referenced by gem5::AtomicSimpleCPU::activateContext(), gem5::TimingSimpleCPU::activateContext(), gem5::TimingSimpleCPU::advanceInst(), advancePC(), gem5::AtomicSimpleCPU::amoMem(), BaseSimpleCPU(), checkForInterrupts(), checkPcEventQueue(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), countInst(), gem5::AtomicSimpleCPU::drainResume(), gem5::TimingSimpleCPU::drainResume(), gem5::TimingSimpleCPU::fetch(), gem5::NonCachingSimpleCPU::fetchInstMem(), gem5::AtomicSimpleCPU::fetchInstMem(), gem5::AtomicSimpleCPU::genMemFragmentRequest(), gem5::TimingSimpleCPU::handleReadPacket(), gem5::TimingSimpleCPU::handleWritePacket(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateHtmCmd(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::AtomicSimpleCPU::isCpuDrained(), gem5::TimingSimpleCPU::isCpuDrained(), postExecute(), preExecute(), gem5::AtomicSimpleCPU::readMem(), gem5::AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), gem5::AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), gem5::TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), resetStats(), gem5::TimingSimpleCPU::sendData(), gem5::TimingSimpleCPU::sendFetch(), gem5::TimingSimpleCPU::sendSplitData(), serializeThread(), serviceInstCountEvents(), setupFetchRequest(), gem5::AtomicSimpleCPU::suspendContext(), gem5::TimingSimpleCPU::suspendContext(), swapActiveThread(), gem5::TimingSimpleCPU::switchOut(), gem5::TimingSimpleCPU::threadSnoop(), gem5::AtomicSimpleCPU::threadSnoop(), gem5::AtomicSimpleCPU::tick(), totalInsts(), totalOps(), unserializeThread(), wakeup(), gem5::AtomicSimpleCPU::writeMem(), and gem5::TimingSimpleCPU::writeMem().

◆ traceData

Trace::InstRecord* gem5::BaseSimpleCPU::traceData

◆ zeroReg

const RegIndex gem5::BaseSimpleCPU::zeroReg
protected

Definition at line 86 of file base.hh.

Referenced by preExecute().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:27:20 for gem5 by doxygen 1.8.17