#include <atomic.hh>

Inheritance diagram for gem5::AtomicSimpleCPU:

Classes
class	AtomicCPUDPort

class	AtomicCPUPort
	An AtomicCPUPort overrides the default behaviour of the recvAtomicSnoop and ignores the packet instead of panicking. More...

Public Member Functions
	AtomicSimpleCPU (const BaseAtomicSimpleCPUParams &params)

virtual	~AtomicSimpleCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

DrainState	drain () override
	Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

void	drainResume () override
	Resume execution after a successful drain.

void	switchOut () override
	Prepare for another CPU to take over execution.

void	takeOverFrom (BaseCPU *old_cpu) override
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU.

void	activateContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now active.

void	suspendContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now suspended.

bool	genMemFragmentRequest (const RequestPtr &req, Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const
	Helper function used to set up the request for a single fragment of a memory access.

Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	initiateMemMgmtCmd (Request::Flags flags) override
	Memory management commands such as hardware transactional memory commands or TLB invalidation commands are memory operations but are neither really (true) loads nor stores.

void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

void	regProbePoints () override
	Register probe points for this object.

void	printAddr (Addr a)
	Print state of address in memory system via PrintReq (for debugging).

Public Member Functions inherited from gem5::BaseSimpleCPU
	BaseSimpleCPU (const BaseSimpleCPUParams &params)

virtual	~BaseSimpleCPU ()

void	wakeup (ThreadID tid) override

void	checkForInterrupts ()

void	setupFetchRequest (const RequestPtr &req)

void	serviceInstCountEvents ()

void	preExecute ()

void	postExecute ()

void	advancePC (const Fault &fault)

void	haltContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now halted.

void	resetStats () override
	Callback to reset stats.

virtual Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)

void	countInst ()

void	countFetchInst ()

void	countCommitInst ()

Counter	totalInsts () const override

Counter	totalOps () const override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread.

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread.

Public Member Functions inherited from gem5::BaseCPU
int	cpuId () const
	Reads this CPU's ID.

uint32_t	socketId () const
	Reads this CPU's Socket ID.

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID.

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU.

uint32_t	taskId () const
	Get cpu task id.

void	taskId (uint32_t id)
	Set cpu task id.

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer.

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num.

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it.

unsigned	numContexts ()
	Get the number of thread contexts available.

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID.

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

void	startup () override
	startup() is the final initialization call before simulation.

void	regStats () override
	Callback to set stat parameters.

void	regProbePoints () override
	Register probe points for this object.

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	setReset (bool state)
	Set the reset of the CPU to be either asserted or deasserted.

void	flushTLBs ()
	Flush all TLBs in the CPU.

bool	switchedOut () const
	Determine if the CPU is switched out.

Addr	cacheLineSize () const
	Get the cache line size of the system.

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream.

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint.

void	scheduleInstStop (ThreadID tid, Counter insts, std::string cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions.

void	scheduleSimpointsInstStop (std::vector< Counter > inst_starts)
	Schedule simpoint events using the scheduleInstStop function.

void	scheduleInstStopAnyThread (Counter max_insts)
	Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function.

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU.

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction.

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
void	tick ()

bool	isCpuDrained () const
	Check if a system is in a drained state.

bool	tryCompleteDrain ()
	Try to complete a drain request.

virtual Tick	sendPacket (RequestPort &port, const PacketPtr &pkt)

virtual Tick	fetchInstMem ()

Port &	getDataPort () override
	Return a reference to the data port.

Port &	getInstPort () override
	Return a reference to the instruction port.

void	threadSnoop (PacketPtr pkt, ThreadID sender)
	Perform snoop for other cpu-local thread contexts.

Protected Member Functions inherited from gem5::BaseSimpleCPU
void	checkPcEventQueue ()

void	swapActiveThread ()

void	traceFault ()
	Handler used when encountering a fault; its purpose is to tear down the InstRecord.

Protected Member Functions inherited from gem5::BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression

void	enterPwrGating ()

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object.

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Protected Attributes
EventFunctionWrapper	tickEvent

const int	width

bool	locked

const bool	simulate_data_stalls

const bool	simulate_inst_stalls

AtomicCPUPort	icachePort

AtomicCPUDPort	dcachePort

RequestPtr	ifetch_req

RequestPtr	data_read_req

RequestPtr	data_write_req

RequestPtr	data_amo_req

bool	dcache_access

Tick	dcache_latency

ProbePointArg< std::pair< SimpleThread , const StaticInstPtr > >	ppCommit
	Probe Points.

Protected Attributes inherited from gem5::BaseSimpleCPU
ThreadID	curThread

branch_prediction::BPredUnit *	branchPred

Status	_status

std::unique_ptr< PCStateBase >	preExecuteTempPC

Protected Attributes inherited from gem5::BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register.

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system.

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5.

uint32_t	_pid
	The current OS process ID that is executing on this processor.

bool	_switchedOut
	Is the CPU switched out or active?

const Addr	_cacheLineSize
	Cache the cache line size that we get from the system.

SignalSinkPort< bool >	modelResetPort

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point.

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions.

probing::PMUUPtr	ppRetiredStores
	Retired store instructions.

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type)

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended.

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active.

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets.

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Additional Inherited Members
Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::BaseCPU
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes inherited from gem5::BaseSimpleCPU
trace::InstRecord *	traceData

CheckerCPU *	checker

std::vector< SimpleExecContext * >	threadInfo

std::list< ThreadID >	activeThreads

StaticInstPtr	curStaticInst
	Current instruction.

StaticInstPtr	curMacroStaticInst

Public Attributes inherited from gem5::BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS).

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

std::vector< std::unique_ptr< FetchCPUStats > >	fetchStats

std::vector< std::unique_ptr< ExecuteCPUStats > >	executeStats

std::vector< std::unique_ptr< CommitCPUStats > >	commitStats

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid.

Protected Types inherited from gem5::BaseSimpleCPU
enum	Status { Idle , Running , Faulting , ITBWaitResponse , IcacheRetry , IcacheWaitResponse , IcacheWaitSwitch , DTBWaitResponse , DcacheRetry , DcacheWaitResponse , DcacheWaitSwitch }

Protected Types inherited from gem5::BaseCPU
enum	CPUState { CPU_STATE_ON , CPU_STATE_SLEEP , CPU_STATE_WAKEUP }

Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure.

Detailed Description

Definition at line 53 of file atomic.hh.

Constructor & Destructor Documentation

◆ AtomicSimpleCPU()

gem5::AtomicSimpleCPU::AtomicSimpleCPU ( const BaseAtomicSimpleCPUParams & params )

Definition at line 74 of file atomic.cc.

References tick().

◆ ~AtomicSimpleCPU()

gem5::AtomicSimpleCPU::~AtomicSimpleCPU ( )

virtual

Definition at line 94 of file atomic.cc.

References gem5::EventManager::deschedule(), gem5::Event::scheduled(), and tickEvent.

Member Function Documentation

◆ activateContext()

void gem5::AtomicSimpleCPU::activateContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now active.

Reimplemented from gem5::BaseCPU.

Definition at line 220 of file atomic.cc.

References gem5::BaseSimpleCPU::_status, gem5::BaseCPU::activateContext(), gem5::BaseSimpleCPU::activeThreads, gem5::BaseCPU::baseStats, gem5::Clocked::clockEdge(), DPRINTF, gem5::BaseCPU::BaseCPUStats::numCycles, gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::Running, gem5::EventManager::schedule(), gem5::Event::scheduled(), gem5::BaseSimpleCPU::threadInfo, tickEvent, and gem5::Clocked::ticksToCycles().

◆ amoMem()

Fault gem5::AtomicSimpleCPU::amoMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op )

overridevirtual

Reimplemented from gem5::BaseSimpleCPU.

Definition at line 546 of file atomic.cc.

References gem5::X86ISA::addr, gem5::BaseCPU::cacheLineSize(), gem5::BaseSimpleCPU::curThread, data, data_amo_req, gem5::BaseCPU::dataRequestorId(), gem5::Packet::dataStatic(), dcache_access, dcache_latency, dcachePort, flags, gem5::Packet::getAddrRange(), gem5::SimpleThread::getTC(), gem5::PCStateBase::instAddr(), gem5::Packet::isError(), gem5::Packet::makeWriteCmd(), gem5::SimpleThread::mmu, gem5::Request::NO_ACCESS, gem5::NoFault, panic_if, gem5::SimpleThread::pcState(), gem5::Packet::print(), gem5::roundDown(), sendPacket(), gem5::trace::InstRecord::setMem(), gem5::BaseCPU::taskId(), gem5::SimpleExecContext::thread, gem5::BaseSimpleCPU::threadInfo, gem5::AddrRange::to_string(), gem5::BaseSimpleCPU::traceData, gem5::BaseMMU::translateAtomic(), and gem5::BaseMMU::Write.

◆ drain()

DrainState gem5::AtomicSimpleCPU::drain ( )

overridevirtual

Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Draining is mostly used before forking and creating a check point.

This function notifies an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note: An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().

Returns: DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements gem5::Drainable.

Definition at line 102 of file atomic.cc.

References gem5::BaseSimpleCPU::activeThreads, gem5::EventManager::deschedule(), gem5::BaseCPU::deschedulePowerGatingEvent(), DPRINTF, gem5::Drained, gem5::Draining, isCpuDrained(), gem5::Event::scheduled(), gem5::BaseCPU::switchedOut(), and tickEvent.

◆ drainResume()

void gem5::AtomicSimpleCPU::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 142 of file atomic.cc.

References gem5::BaseSimpleCPU::_status, gem5::ThreadContext::Active, gem5::BaseSimpleCPU::activeThreads, DPRINTF, gem5::BaseSimpleCPU::Idle, gem5::Clocked::nextCycle(), gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::Running, gem5::EventManager::schedule(), gem5::Event::scheduled(), gem5::BaseCPU::schedulePowerGatingEvent(), gem5::BaseCPU::switchedOut(), gem5::BaseCPU::threadContexts, gem5::BaseSimpleCPU::threadInfo, tickEvent, and verifyMemoryMode().

◆ fetchInstMem()

Tick gem5::AtomicSimpleCPU::fetchInstMem ( )

protectedvirtual

Reimplemented in gem5::NonCachingSimpleCPU.

Definition at line 742 of file atomic.cc.

References gem5::BaseSimpleCPU::curThread, gem5::Packet::dataStatic(), decoder, gem5::Packet::getAddrRange(), icachePort, ifetch_req, gem5::Packet::isError(), panic_if, gem5::Packet::print(), gem5::MemCmd::ReadReq, sendPacket(), gem5::BaseSimpleCPU::threadInfo, and gem5::AddrRange::to_string().

Referenced by gem5::NonCachingSimpleCPU::fetchInstMem(), and tick().

◆ genMemFragmentRequest()

bool gem5::AtomicSimpleCPU::genMemFragmentRequest	(	const RequestPtr &	req,
		Addr	frag_addr,
		int	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable,
		int &	frag_size,
		int &	size_left ) const

Helper function used to set up the request for a single fragment of a memory access.

Takes care of setting up the appropriate byte-enable mask for the fragment, given the mask for the entire memory access.

Parameters

	req	Pointer to the Request object to populate.
	frag_addr	Start address of the fragment.
	size	Total size of the memory access in bytes.
	flags	Request flags.
	byte_enable	Byte-enable mask for the entire memory access.
[out]	frag_size	Fragment size.
[in,out]	size_left	Size left to be processed in the memory access.

Returns: True if the byte-enable mask for the fragment is not all-false.

Definition at line 331 of file atomic.cc.

References gem5::addrBlockOffset(), gem5::BaseCPU::cacheLineSize(), gem5::BaseSimpleCPU::curThread, gem5::BaseCPU::dataRequestorId(), flags, gem5::isAnyActiveElement(), and gem5::BaseSimpleCPU::threadInfo.

Referenced by readMem(), and writeMem().

◆ getDataPort()

Port & gem5::AtomicSimpleCPU::getDataPort ( )

inlineoverrideprotectedvirtual

Return a reference to the data port.

Implements gem5::BaseCPU.

Definition at line 179 of file atomic.hh.

References dcachePort.

◆ getInstPort()

Port & gem5::AtomicSimpleCPU::getInstPort ( )

inlineoverrideprotectedvirtual

Return a reference to the instruction port.

Implements gem5::BaseCPU.

Definition at line 182 of file atomic.hh.

References icachePort.

◆ htmSendAbortSignal()

void gem5::AtomicSimpleCPU::htmSendAbortSignal	(	ThreadID	tid,
		uint64_t	htm_uid,
		HtmFailureFaultCause	cause )

inlineoverridevirtual

This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

This is called in the transaction's very last breath in the core. Afterwards, the core throws away its speculative state and resumes execution at the point the transaction started, i.e. reverses time. When instruction execution resumes, the core expects the memory subsystem to be in a stable, i.e. pre-speculative, state as well.

Reimplemented from gem5::BaseCPU.

Definition at line 234 of file atomic.hh.

References panic.

◆ init()

void gem5::AtomicSimpleCPU::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 63 of file atomic.cc.

References data_amo_req, data_read_req, data_write_req, ifetch_req, gem5::BaseCPU::init(), and gem5::BaseCPU::threadContexts.

◆ initiateMemMgmtCmd()

Fault gem5::AtomicSimpleCPU::initiateMemMgmtCmd ( Request::Flags flags )

inlineoverridevirtual

Memory management commands such as hardware transactional memory commands or TLB invalidation commands are memory operations but are neither really (true) loads nor stores.

For this reason the interface is extended, and initiateMemMgmtCmd() is used to instigate the command.

Implements gem5::BaseSimpleCPU.

Definition at line 227 of file atomic.hh.

References panic.

◆ isCpuDrained()

bool gem5::AtomicSimpleCPU::isCpuDrained ( ) const

inlineprotected

Check if a system is in a drained state.

We need to drain if:

We are in the middle of a microcode sequence as some CPUs (e.g., HW accelerated CPUs) can't be started in the middle of a gem5 microcode sequence.
The CPU is in a LLSC region. This shouldn't normally happen as these are executed atomically within a single tick() call. The only way this can happen at the moment is if there is an event in the PC event queue that affects the CPU state while it is in an LLSC region.
Stay at PC is true.

Definition at line 92 of file atomic.hh.

References gem5::BaseSimpleCPU::curThread, locked, gem5::PCStateBase::microPC(), gem5::SimpleThread::pcState(), gem5::SimpleExecContext::stayAtPC, gem5::SimpleExecContext::thread, and gem5::BaseSimpleCPU::threadInfo.

Referenced by drain(), switchOut(), and tryCompleteDrain().

◆ printAddr()

void gem5::AtomicSimpleCPU::printAddr ( Addr a )

Print state of address in memory system via PrintReq (for debugging).

Definition at line 769 of file atomic.cc.

References gem5::ArmISA::a, dcachePort, and gem5::RequestPort::printAddr().

◆ readMem()

Fault gem5::AtomicSimpleCPU::readMem	(	Addr	addr,
		uint8_t *	data,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = std::vector<bool>() )

overridevirtual

◆ regProbePoints()

void gem5::AtomicSimpleCPU::regProbePoints ( )

overridevirtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented from gem5::SimObject.

Definition at line 760 of file atomic.cc.

References gem5::SimObject::getProbeManager(), ppCommit, and gem5::BaseCPU::regProbePoints().

◆ sendPacket()

Tick gem5::AtomicSimpleCPU::sendPacket	(	RequestPort &	port,
		const PacketPtr &	pkt )

protectedvirtual

Reimplemented in gem5::NonCachingSimpleCPU.

Definition at line 272 of file atomic.cc.

References gem5::RequestPort::sendAtomic().

Referenced by amoMem(), fetchInstMem(), readMem(), and writeMem().

◆ suspendContext()

void gem5::AtomicSimpleCPU::suspendContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented from gem5::BaseCPU.

Definition at line 246 of file atomic.cc.

References gem5::BaseSimpleCPU::_status, gem5::BaseSimpleCPU::activeThreads, gem5::EventManager::deschedule(), DPRINTF, gem5::BaseSimpleCPU::Idle, gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::Running, gem5::Event::scheduled(), gem5::BaseCPU::suspendContext(), gem5::BaseSimpleCPU::threadInfo, and tickEvent.

◆ switchOut()

void gem5::AtomicSimpleCPU::switchOut ( )

overridevirtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented from gem5::BaseCPU.

Definition at line 192 of file atomic.cc.

References gem5::BaseSimpleCPU::_status, gem5::BaseSimpleCPU::Idle, isCpuDrained(), gem5::BaseSimpleCPU::Running, gem5::Event::scheduled(), gem5::BaseCPU::switchOut(), and tickEvent.

◆ takeOverFrom()

void gem5::AtomicSimpleCPU::takeOverFrom ( BaseCPU * cpu )

overridevirtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented from gem5::BaseCPU.

Definition at line 203 of file atomic.cc.

References gem5::Event::scheduled(), gem5::BaseCPU::takeOverFrom(), and tickEvent.

◆ threadSnoop()

void gem5::AtomicSimpleCPU::threadSnoop	(	PacketPtr	pkt,
		ThreadID	sender )

protected

Perform snoop for other cpu-local thread contexts.

Definition at line 124 of file atomic.cc.

References gem5::AtomicSimpleCPU::AtomicCPUDPort::cacheBlockMask, gem5::Packet::cmdString(), dcachePort, DPRINTF, gem5::Packet::getAddr(), gem5::BaseCPU::getCpuAddrMonitor(), gem5::BaseCPU::numThreads, gem5::BaseSimpleCPU::threadInfo, and gem5::BaseSimpleCPU::wakeup().

Referenced by writeMem().

◆ tick()

void gem5::AtomicSimpleCPU::tick ( )

protected

Definition at line 611 of file atomic.cc.

Referenced by AtomicSimpleCPU().

◆ tryCompleteDrain()

bool gem5::AtomicSimpleCPU::tryCompleteDrain ( )

protected

Try to complete a drain request.

Returns: true if the CPU is drained, false otherwise.

Definition at line 175 of file atomic.cc.

References DPRINTF, gem5::Draining, gem5::Drainable::drainState(), isCpuDrained(), and gem5::Drainable::signalDrainDone().

Referenced by tick().

◆ verifyMemoryMode()

void gem5::AtomicSimpleCPU::verifyMemoryMode ( ) const

overridevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented from gem5::BaseCPU.

Reimplemented in gem5::NonCachingSimpleCPU.

Definition at line 212 of file atomic.cc.

References fatal_if, and gem5::X86ISA::system.

Referenced by drainResume().

◆ writeMem()

Fault gem5::AtomicSimpleCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = std::vector<bool>() )

overridevirtual

Reimplemented from gem5::BaseSimpleCPU.

Definition at line 437 of file atomic.cc.

References gem5::X86ISA::addr, gem5::AtomicSimpleCPU::AtomicCPUDPort::cacheBlockMask, gem5::BaseSimpleCPU::curThread, data, data_write_req, gem5::Packet::dataStatic(), dcache_access, dcache_latency, dcachePort, flags, genMemFragmentRequest(), gem5::Packet::getAddrRange(), gem5::Packet::getConstPtr(), gem5::SimpleThread::getIsaPtr(), gem5::SimpleThread::getTC(), gem5::BaseISA::handleLockedWrite(), gem5::Packet::isError(), locked, gem5::Packet::makeWriteCmd(), gem5::SimpleThread::mmu, gem5::Request::NO_ACCESS, gem5::NoFault, panic_if, gem5::Packet::print(), sendPacket(), gem5::trace::InstRecord::setMem(), gem5::Request::STORE_NO_DATA, gem5::BaseCPU::taskId(), gem5::SimpleExecContext::thread, gem5::BaseSimpleCPU::threadInfo, threadSnoop(), gem5::AddrRange::to_string(), gem5::BaseSimpleCPU::traceData, gem5::BaseMMU::translateAtomic(), and gem5::BaseMMU::Write.

Member Data Documentation

◆ data_amo_req

RequestPtr gem5::AtomicSimpleCPU::data_amo_req

protected

Definition at line 168 of file atomic.hh.

Referenced by amoMem(), init(), and tick().

◆ data_read_req

RequestPtr gem5::AtomicSimpleCPU::data_read_req

protected

Definition at line 166 of file atomic.hh.

Referenced by init(), readMem(), and tick().

◆ data_write_req

RequestPtr gem5::AtomicSimpleCPU::data_write_req

protected

Definition at line 167 of file atomic.hh.

Referenced by init(), tick(), and writeMem().

◆ dcache_access

bool gem5::AtomicSimpleCPU::dcache_access

protected

Definition at line 170 of file atomic.hh.

Referenced by amoMem(), readMem(), tick(), and writeMem().

◆ dcache_latency

Tick gem5::AtomicSimpleCPU::dcache_latency

protected

Definition at line 171 of file atomic.hh.

Referenced by amoMem(), readMem(), tick(), and writeMem().

◆ dcachePort

AtomicCPUDPort gem5::AtomicSimpleCPU::dcachePort

protected

Definition at line 162 of file atomic.hh.

Referenced by amoMem(), getDataPort(), printAddr(), readMem(), threadSnoop(), and writeMem().

◆ icachePort

AtomicCPUPort gem5::AtomicSimpleCPU::icachePort

protected

Definition at line 161 of file atomic.hh.

Referenced by fetchInstMem(), and getInstPort().

◆ ifetch_req

RequestPtr gem5::AtomicSimpleCPU::ifetch_req

protected

Definition at line 165 of file atomic.hh.

Referenced by fetchInstMem(), gem5::NonCachingSimpleCPU::fetchInstMem(), init(), and tick().

◆ locked

bool gem5::AtomicSimpleCPU::locked

protected

Definition at line 66 of file atomic.hh.

Referenced by isCpuDrained(), readMem(), tick(), and writeMem().

◆ ppCommit

ProbePointArg<std::pair<SimpleThread *, const StaticInstPtr> >* gem5::AtomicSimpleCPU::ppCommit

protected

Probe Points.

Definition at line 174 of file atomic.hh.

Referenced by regProbePoints(), and tick().

◆ simulate_data_stalls

const bool gem5::AtomicSimpleCPU::simulate_data_stalls

protected

Definition at line 67 of file atomic.hh.

Referenced by tick().

◆ simulate_inst_stalls

const bool gem5::AtomicSimpleCPU::simulate_inst_stalls

protected

Definition at line 68 of file atomic.hh.

Referenced by tick().

◆ tickEvent

EventFunctionWrapper gem5::AtomicSimpleCPU::tickEvent

protected

Definition at line 63 of file atomic.hh.

Referenced by activateContext(), drain(), drainResume(), suspendContext(), switchOut(), takeOverFrom(), tick(), and ~AtomicSimpleCPU().

◆ width

const int gem5::AtomicSimpleCPU::width

protected

Definition at line 65 of file atomic.hh.

Referenced by tick().

The documentation for this class was generated from the following files:

cpu/simple/atomic.hh
cpu/simple/atomic.cc

Classes

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ AtomicSimpleCPU()

◆ ~AtomicSimpleCPU()

Member Function Documentation

◆ activateContext()

◆ amoMem()

◆ drain()

◆ drainResume()

◆ fetchInstMem()

◆ genMemFragmentRequest()

◆ getDataPort()

◆ getInstPort()

◆ htmSendAbortSignal()

◆ init()

◆ initiateMemMgmtCmd()

◆ isCpuDrained()

◆ printAddr()

◆ readMem()

◆ regProbePoints()

◆ sendPacket()

◆ suspendContext()

◆ switchOut()

◆ takeOverFrom()

◆ threadSnoop()

◆ tick()

◆ tryCompleteDrain()

◆ verifyMemoryMode()

◆ writeMem()

Member Data Documentation

◆ data_amo_req

◆ data_read_req

◆ data_write_req

◆ dcache_access

◆ dcache_latency

◆ dcachePort

◆ icachePort

◆ ifetch_req

◆ locked

◆ ppCommit

◆ simulate_data_stalls

◆ simulate_inst_stalls

◆ tickEvent

◆ width