gem5  v21.1.0.2
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gem5::BaseCPU Class Referenceabstract

#include <base.hh>

Inheritance diagram for gem5::BaseCPU:
gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named gem5::BaseKvmCPU gem5::BaseSimpleCPU gem5::CheckerCPU gem5::Iris::BaseCPU gem5::MinorCPU gem5::o3::CPU gem5::TraceCPU gem5::ArmKvmCPU gem5::BaseArmKvmCPU gem5::X86KvmCPU gem5::AtomicSimpleCPU gem5::TimingSimpleCPU gem5::Checker< gem5::RefCountingPtr > gem5::Checker< DynInstPtr > gem5::DummyChecker gem5::Iris::CPU< CortexA76TC > gem5::Iris::CPU< CortexR52TC > gem5::Iris::CPU< TC >

Classes

struct  BaseCPUStats
 
struct  GlobalStats
 Global CPU statistics that are merged into the Root object. More...
 

Public Member Functions

virtual PortgetDataPort ()=0
 Purely virtual method that returns a reference to the data port. More...
 
virtual PortgetInstPort ()=0
 Purely virtual method that returns a reference to the instruction port. More...
 
int cpuId () const
 Reads this CPU's ID. More...
 
uint32_t socketId () const
 Reads this CPU's Socket ID. More...
 
RequestorID dataRequestorId () const
 Reads this CPU's unique data requestor ID. More...
 
RequestorID instRequestorId () const
 Reads this CPU's unique instruction requestor ID. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port on this CPU. More...
 
uint32_t taskId () const
 Get cpu task id. More...
 
void taskId (uint32_t id)
 Set cpu task id. More...
 
uint32_t getPid () const
 
void setPid (uint32_t pid)
 
void workItemBegin ()
 
void workItemEnd ()
 
Tick instCount ()
 
BaseInterruptsgetInterruptController (ThreadID tid)
 
virtual void wakeup (ThreadID tid)=0
 
void postInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupt (ThreadID tid, int int_num, int index)
 
void clearInterrupts (ThreadID tid)
 
bool checkInterrupts (ThreadID tid) const
 
Trace::InstTracergetTracer ()
 Provide access to the tracer pointer. More...
 
virtual void activateContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now active. More...
 
virtual void suspendContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now suspended. More...
 
virtual void haltContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now halted. More...
 
int findContext (ThreadContext *tc)
 Given a Thread Context pointer return the thread num. More...
 
virtual ThreadContextgetContext (int tn)
 Given a thread num get tho thread context for it. More...
 
unsigned numContexts ()
 Get the number of thread contexts available. More...
 
ThreadID contextToThread (ContextID cid)
 Convert ContextID to threadID. More...
 
 PARAMS (BaseCPU)
 
 BaseCPU (const Params &params, bool is_checker=false)
 
virtual ~BaseCPU ()
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
void startup () override
 startup() is the final initialization call before simulation. More...
 
void regStats () override
 Callback to set stat parameters. More...
 
void regProbePoints () override
 Register probe points for this object. More...
 
void registerThreadContexts ()
 
void deschedulePowerGatingEvent ()
 
void schedulePowerGatingEvent ()
 
virtual void switchOut ()
 Prepare for another CPU to take over execution. More...
 
virtual void takeOverFrom (BaseCPU *cpu)
 Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...
 
void flushTLBs ()
 Flush all TLBs in the CPU. More...
 
bool switchedOut () const
 Determine if the CPU is switched out. More...
 
virtual void verifyMemoryMode () const
 Verify that the system is in a memory mode supported by the CPU. More...
 
unsigned int cacheLineSize () const
 Get the cache line size of the system. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize this object to the given output stream. More...
 
void unserialize (CheckpointIn &cp) override
 Reconstruct the state of this object from a checkpoint. More...
 
virtual void serializeThread (CheckpointOut &cp, ThreadID tid) const
 Serialize a single thread. More...
 
virtual void unserializeThread (CheckpointIn &cp, ThreadID tid)
 Unserialize one thread. More...
 
virtual Counter totalInsts () const =0
 
virtual Counter totalOps () const =0
 
void scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
 Schedule an event that exits the simulation loops after a predefined number of instructions. More...
 
uint64_t getCurrentInstCount (ThreadID tid)
 Get the number of instructions executed by the specified thread on this CPU. More...
 
void traceFunctions (Addr pc)
 
void armMonitor (ThreadID tid, Addr address)
 
bool mwait (ThreadID tid, PacketPtr pkt)
 
void mwaitAtomic (ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
 
AddressMonitorgetCpuAddrMonitor (ThreadID tid)
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes. More...
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Static Public Member Functions

static int numSimulatedCPUs ()
 
static Counter numSimulatedInsts ()
 
static Counter numSimulatedOps ()
 
- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 

Public Attributes

ThreadID numThreads
 Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...
 
Systemsystem
 
gem5::BaseCPU::BaseCPUStats baseStats
 
Cycles syscallRetryLatency
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 

Static Public Attributes

static const uint32_t invldPid = std::numeric_limits<uint32_t>::max()
 Invalid or unknown Pid. More...
 

Protected Types

enum  CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }
 

Protected Member Functions

void updateCycleCounters (CPUState state)
 base method keeping track of cycle progression More...
 
void enterPwrGating ()
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 

Protected Attributes

Tick instCnt
 Instruction count used for SPARC misc register. More...
 
int _cpuId
 
const uint32_t _socketId
 Each cpu will have a socket ID that corresponds to its physical location in the system. More...
 
RequestorID _instRequestorId
 instruction side request id that must be placed in all requests More...
 
RequestorID _dataRequestorId
 data side request id that must be placed in all requests More...
 
uint32_t _taskId
 An intrenal representation of a task identifier within gem5. More...
 
uint32_t _pid
 The current OS process ID that is executing on this processor. More...
 
bool _switchedOut
 Is the CPU switched out or active? More...
 
const unsigned int _cacheLineSize
 Cache the cache line size that we get from the system. More...
 
std::vector< BaseInterrupts * > interrupts
 
std::vector< ThreadContext * > threadContexts
 
Trace::InstTracertracer
 
Cycles previousCycle
 
CPUState previousState
 
const Cycles pwrGatingLatency
 
const bool powerGatingOnIdle
 
EventFunctionWrapper enterPwrGatingEvent
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Static Protected Attributes

static std::unique_ptr< GlobalStatsglobalStats
 Pointer to the global stat structure. More...
 

Private Member Functions

void enableFunctionTrace ()
 
void traceFunctionsInternal (Addr pc)
 

Private Attributes

bool functionTracingEnabled
 
std::ostream * functionTraceStream
 
Addr currentFunctionStart
 
Addr currentFunctionEnd
 
Tick functionEntryTick
 
std::vector< AddressMonitoraddressMonitor
 

Static Private Attributes

static std::vector< BaseCPU * > cpuList
 Static global cpu list. More...
 

PMU Probe points.

probing::PMUUPtr ppRetiredInsts
 Instruction commit probe point. More...
 
probing::PMUUPtr ppRetiredInstsPC
 
probing::PMUUPtr ppRetiredLoads
 Retired load instructions. More...
 
probing::PMUUPtr ppRetiredStores
 Retired store instructions. More...
 
probing::PMUUPtr ppRetiredBranches
 Retired branches (any type) More...
 
probing::PMUUPtr ppAllCycles
 CPU cycle counter even if any thread Context is suspended. More...
 
probing::PMUUPtr ppActiveCycles
 CPU cycle counter, only counts if any thread contexts is active. More...
 
ProbePointArg< bool > * ppSleeping
 ProbePoint that signals transitions of threadContexts sets. More...
 
virtual void probeInstCommit (const StaticInstPtr &inst, Addr pc)
 Helper method to trigger PMU probes for a committed instruction. More...
 
probing::PMUUPtr pmuProbePoint (const char *name)
 Helper method to instantiate probe points belonging to this object. More...
 

Additional Inherited Members

- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 

Detailed Description

Definition at line 107 of file base.hh.

Member Enumeration Documentation

◆ CPUState

enum gem5::BaseCPU::CPUState
protected
Enumerator
CPU_STATE_ON 
CPU_STATE_SLEEP 
CPU_STATE_WAKEUP 

Definition at line 512 of file base.hh.

Constructor & Destructor Documentation

◆ BaseCPU()

gem5::BaseCPU::BaseCPU ( const Params params,
bool  is_checker = false 
)

Definition at line 127 of file base.cc.

References enterPwrGating().

◆ ~BaseCPU()

gem5::BaseCPU::~BaseCPU ( )
virtual

Reimplemented in gem5::Iris::BaseCPU.

Definition at line 189 of file base.cc.

Member Function Documentation

◆ activateContext()

void gem5::BaseCPU::activateContext ( ThreadID  thread_num)
virtual

◆ armMonitor()

void gem5::BaseCPU::armMonitor ( ThreadID  tid,
Addr  address 
)

◆ cacheLineSize()

unsigned int gem5::BaseCPU::cacheLineSize ( ) const
inline

◆ checkInterrupts()

bool gem5::BaseCPU::checkInterrupts ( ThreadID  tid) const
inline

◆ clearInterrupt()

void gem5::BaseCPU::clearInterrupt ( ThreadID  tid,
int  int_num,
int  index 
)
inline

◆ clearInterrupts()

void gem5::BaseCPU::clearInterrupts ( ThreadID  tid)
inline

Definition at line 250 of file base.hh.

References interrupts.

Referenced by gem5::o3::Commit::commitInsts(), and gem5::ArmISA::Reset::invoke().

◆ contextToThread()

ThreadID gem5::BaseCPU::contextToThread ( ContextID  cid)
inline

◆ cpuId()

int gem5::BaseCPU::cpuId ( ) const
inline

◆ dataRequestorId()

RequestorID gem5::BaseCPU::dataRequestorId ( ) const
inline

◆ deschedulePowerGatingEvent()

void gem5::BaseCPU::deschedulePowerGatingEvent ( )

◆ enableFunctionTrace()

void gem5::BaseCPU::enableFunctionTrace ( )
private

Definition at line 184 of file base.cc.

References functionTracingEnabled.

◆ enterPwrGating()

void gem5::BaseCPU::enterPwrGating ( )
protected

Definition at line 534 of file base.cc.

References gem5::RiscvISA::OFF, gem5::ClockedObject::powerState, and gem5::PowerState::set().

Referenced by BaseCPU().

◆ findContext()

int gem5::BaseCPU::findContext ( ThreadContext tc)

Given a Thread Context pointer return the thread num.

Definition at line 477 of file base.cc.

References threadContexts.

◆ flushTLBs()

void gem5::BaseCPU::flushTLBs ( )

Flush all TLBs in the CPU.

This method is mainly used to flush stale translations when switching CPUs. It is also exported to the Python world to allow it to request a TLB flush after draining the CPU to make it easier to compare traces when debugging handover/checkpointing.

Definition at line 616 of file base.cc.

References gem5::BaseMMU::flushAll(), gem5::ThreadContext::getCheckerCpuPtr(), gem5::ThreadContext::getMMUPtr(), gem5::CheckerCPU::getMMUPtr(), gem5::ArmISA::i, and threadContexts.

Referenced by switchOut().

◆ getContext()

virtual ThreadContext* gem5::BaseCPU::getContext ( int  tn)
inlinevirtual

◆ getCpuAddrMonitor()

AddressMonitor* gem5::BaseCPU::getCpuAddrMonitor ( ThreadID  tid)
inline

◆ getCurrentInstCount()

Tick gem5::BaseCPU::getCurrentInstCount ( ThreadID  tid)

Get the number of instructions executed by the specified thread on this CPU.

Used by Python to control simulation.

Parameters
tidThread monitor
Returns
Number of instructions executed

Definition at line 677 of file base.cc.

References threadContexts.

Referenced by scheduleInstStop().

◆ getDataPort()

virtual Port& gem5::BaseCPU::getDataPort ( )
pure virtual

Purely virtual method that returns a reference to the data port.

All subclasses must implement this method.

Returns
a reference to the data port

Implemented in gem5::o3::CPU, gem5::TimingSimpleCPU, gem5::AtomicSimpleCPU, gem5::MinorCPU, gem5::BaseKvmCPU, gem5::CheckerCPU, gem5::Iris::BaseCPU, and gem5::TraceCPU.

Referenced by getPort(), gem5::ThreadContext::sendFunctional(), gem5::TraceCPU::takeOverFrom(), and takeOverFrom().

◆ getInstPort()

virtual Port& gem5::BaseCPU::getInstPort ( )
pure virtual

Purely virtual method that returns a reference to the instruction port.

All subclasses must implement this method.

Returns
a reference to the instruction port

Implemented in gem5::o3::CPU, gem5::TimingSimpleCPU, gem5::AtomicSimpleCPU, gem5::MinorCPU, gem5::CheckerCPU, gem5::BaseKvmCPU, gem5::Iris::BaseCPU, and gem5::TraceCPU.

Referenced by getPort(), gem5::TraceCPU::takeOverFrom(), and takeOverFrom().

◆ getInterruptController()

BaseInterrupts* gem5::BaseCPU::getInterruptController ( ThreadID  tid)
inline

◆ getPid()

uint32_t gem5::BaseCPU::getPid ( ) const
inline

Definition at line 216 of file base.hh.

References _pid.

Referenced by takeOverFrom().

◆ getPort()

Port & gem5::BaseCPU::getPort ( const std::string &  if_name,
PortID  idx = InvalidPortID 
)
overridevirtual

Get a port on this CPU.

All CPUs have a data and instruction port, and this method uses getDataPort and getInstPort of the subclasses to resolve the two ports.

Parameters
if_namethe port name
idxignored index
Returns
a reference to the port with the given name

Reimplemented from gem5::SimObject.

Definition at line 410 of file base.cc.

References getDataPort(), getInstPort(), and gem5::SimObject::getPort().

Referenced by gem5::fastmodel::CortexA76::getPort().

◆ getTracer()

Trace::InstTracer* gem5::BaseCPU::getTracer ( )
inline

Provide access to the tracer pointer.

Definition at line 274 of file base.hh.

References tracer.

Referenced by gem5::o3::Fetch::buildInst().

◆ haltContext()

void gem5::BaseCPU::haltContext ( ThreadID  thread_num)
virtual

Notify the CPU that the indicated context is now halted.

Reimplemented in gem5::o3::CPU, gem5::BaseSimpleCPU, and gem5::BaseKvmCPU.

Definition at line 528 of file base.cc.

References CPU_STATE_SLEEP, and updateCycleCounters().

Referenced by gem5::SimpleThread::halt().

◆ init()

void gem5::BaseCPU::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Reimplemented in gem5::o3::CPU, gem5::MinorCPU, gem5::BaseSimpleCPU, gem5::CheckerCPU, gem5::BaseKvmCPU, gem5::AtomicSimpleCPU, gem5::TimingSimpleCPU, and gem5::TraceCPU.

Definition at line 272 of file base.cc.

References gem5::MipsISA::event, gem5::ArmISA::i, numThreads, gem5::SimObject::params(), registerThreadContexts(), scheduleInstStop(), threadContexts, and verifyMemoryMode().

Referenced by gem5::BaseKvmCPU::init(), gem5::BaseSimpleCPU::init(), gem5::Iris::BaseCPU::init(), gem5::MinorCPU::init(), gem5::TraceCPU::init(), and gem5::o3::CPU::init().

◆ instCount()

Tick gem5::BaseCPU::instCount ( )
inline

◆ instRequestorId()

RequestorID gem5::BaseCPU::instRequestorId ( ) const
inline

Reads this CPU's unique instruction requestor ID.

Definition at line 196 of file base.hh.

References _instRequestorId.

Referenced by gem5::o3::Fetch::fetchCacheLine(), gem5::minor::Fetch1::fetchLine(), and gem5::BaseSimpleCPU::setupFetchRequest().

◆ mwait()

bool gem5::BaseCPU::mwait ( ThreadID  tid,
PacketPtr  pkt 
)

◆ mwaitAtomic()

void gem5::BaseCPU::mwaitAtomic ( ThreadID  tid,
ThreadContext tc,
BaseMMU mmu 
)

◆ numContexts()

unsigned gem5::BaseCPU::numContexts ( )
inline

Get the number of thread contexts available.

Definition at line 293 of file base.hh.

References threadContexts.

Referenced by gem5::o3::LSQUnit::checkSnoop().

◆ numSimulatedCPUs()

static int gem5::BaseCPU::numSimulatedCPUs ( )
inlinestatic

Definition at line 569 of file base.hh.

References cpuList.

◆ numSimulatedInsts()

static Counter gem5::BaseCPU::numSimulatedInsts ( )
inlinestatic

◆ numSimulatedOps()

static Counter gem5::BaseCPU::numSimulatedOps ( )
inlinestatic

◆ PARAMS()

gem5::BaseCPU::PARAMS ( BaseCPU  )

◆ pmuProbePoint()

probing::PMUUPtr gem5::BaseCPU::pmuProbePoint ( const char *  name)
protected

Helper method to instantiate probe points belonging to this object.

Parameters
nameName of the probe point.
Returns
A unique_ptr to the new probe point.

Definition at line 331 of file base.cc.

References gem5::SimObject::getProbeManager(), and gem5::Named::name().

Referenced by regProbePoints().

◆ postInterrupt()

void gem5::BaseCPU::postInterrupt ( ThreadID  tid,
int  int_num,
int  index 
)

◆ probeInstCommit()

void gem5::BaseCPU::probeInstCommit ( const StaticInstPtr inst,
Addr  pc 
)
virtual

◆ registerThreadContexts()

void gem5::BaseCPU::registerThreadContexts ( )

◆ regProbePoints()

void gem5::BaseCPU::regProbePoints ( )
overridevirtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented from gem5::SimObject.

Reimplemented in gem5::AtomicSimpleCPU, and gem5::o3::CPU.

Definition at line 340 of file base.cc.

References gem5::SimObject::getProbeManager(), pmuProbePoint(), ppActiveCycles, ppAllCycles, ppRetiredBranches, ppRetiredInsts, ppRetiredInstsPC, ppRetiredLoads, ppRetiredStores, and ppSleeping.

Referenced by gem5::o3::CPU::regProbePoints(), and gem5::AtomicSimpleCPU::regProbePoints().

◆ regStats()

void gem5::BaseCPU::regStats ( )
overridevirtual

Callback to set stat parameters.

This callback is typically used for complex stats (e.g., distributions) that need parameters in addition to a name and a description. Stat names and descriptions should typically be set from the constructor usingo from the constructor using the ADD_STAT macro.

Reimplemented from gem5::statistics::Group.

Reimplemented in gem5::MinorCPU.

Definition at line 386 of file base.cc.

References gem5::ccprintf(), globalStats, gem5::ArmISA::i, gem5::Named::name(), gem5::statistics::Group::regStats(), gem5::Root::root(), and threadContexts.

Referenced by gem5::MinorCPU::regStats().

◆ scheduleInstStop()

void gem5::BaseCPU::scheduleInstStop ( ThreadID  tid,
Counter  insts,
const char *  cause 
)

Schedule an event that exits the simulation loops after a predefined number of instructions.

This method is usually called from the configuration script to get an exit event some time in the future. It is typically used when the script wants to simulate for a specific number of instructions rather than ticks.

Parameters
tidThread monitor.
instsNumber of instructions into the future.
causeCause to signal in the exit event.

Definition at line 668 of file base.cc.

References gem5::MipsISA::event, getCurrentInstCount(), and threadContexts.

Referenced by init().

◆ schedulePowerGatingEvent()

void gem5::BaseCPU::schedulePowerGatingEvent ( )

◆ serialize()

void gem5::BaseCPU::serialize ( CheckpointOut cp) const
overridevirtual

Serialize this object to the given output stream.

Note
CPU models should normally overload the serializeThread() method instead of the serialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.
Parameters
cpThe stream to serialize to.

Implements gem5::Serializable.

Reimplemented in gem5::CheckerCPU, and gem5::MinorCPU.

Definition at line 630 of file base.cc.

References _pid, _switchedOut, gem5::csprintf(), gem5::ArmISA::i, instCnt, interrupts, numThreads, SERIALIZE_SCALAR, and serializeThread().

Referenced by gem5::MinorCPU::serialize().

◆ serializeThread()

virtual void gem5::BaseCPU::serializeThread ( CheckpointOut cp,
ThreadID  tid 
) const
inlinevirtual

Serialize a single thread.

Parameters
cpThe stream to serialize to.
tidID of the current thread.

Reimplemented in gem5::o3::CPU, gem5::BaseSimpleCPU, gem5::MinorCPU, gem5::Iris::BaseCPU, and gem5::BaseKvmCPU.

Definition at line 413 of file base.hh.

Referenced by serialize().

◆ setPid()

void gem5::BaseCPU::setPid ( uint32_t  pid)
inline

Definition at line 217 of file base.hh.

References _pid.

Referenced by gem5::ArmISA::DumpStats::process().

◆ socketId()

uint32_t gem5::BaseCPU::socketId ( ) const
inline

◆ startup()

void gem5::BaseCPU::startup ( )
overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Reimplemented in gem5::o3::CPU, gem5::MinorCPU, gem5::BaseKvmCPU, and gem5::X86KvmCPU.

Definition at line 315 of file base.cc.

References _switchedOut, gem5::PowerState::get(), gem5::RiscvISA::OFF, gem5::SimObject::params(), gem5::ClockedObject::powerState, and gem5::PowerState::set().

Referenced by gem5::BaseKvmCPU::startup(), gem5::MinorCPU::startup(), and gem5::o3::CPU::startup().

◆ suspendContext()

void gem5::BaseCPU::suspendContext ( ThreadID  thread_num)
virtual

◆ switchedOut()

bool gem5::BaseCPU::switchedOut ( ) const
inline

◆ switchOut()

void gem5::BaseCPU::switchOut ( )
virtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented in gem5::TimingSimpleCPU, gem5::o3::CPU, gem5::AtomicSimpleCPU, gem5::MinorCPU, gem5::BaseKvmCPU, gem5::Checker< DynInstPtr >, and gem5::Checker< gem5::RefCountingPtr >.

Definition at line 540 of file base.cc.

References _switchedOut, flushTLBs(), gem5::RiscvISA::OFF, gem5::ClockedObject::powerState, and gem5::PowerState::set().

Referenced by gem5::BaseKvmCPU::switchOut(), gem5::MinorCPU::switchOut(), gem5::AtomicSimpleCPU::switchOut(), gem5::o3::CPU::switchOut(), and gem5::TimingSimpleCPU::switchOut().

◆ takeOverFrom()

void gem5::BaseCPU::takeOverFrom ( BaseCPU cpu)
virtual

◆ taskId() [1/2]

uint32_t gem5::BaseCPU::taskId ( ) const
inline

◆ taskId() [2/2]

void gem5::BaseCPU::taskId ( uint32_t  id)
inline

Set cpu task id.

Definition at line 214 of file base.hh.

References _taskId, and gem5::ArmISA::id.

◆ totalInsts()

virtual Counter gem5::BaseCPU::totalInsts ( ) const
pure virtual

◆ totalOps()

virtual Counter gem5::BaseCPU::totalOps ( ) const
pure virtual

◆ traceFunctions()

void gem5::BaseCPU::traceFunctions ( Addr  pc)
inline

◆ traceFunctionsInternal()

void gem5::BaseCPU::traceFunctionsInternal ( Addr  pc)
private

◆ unserialize()

void gem5::BaseCPU::unserialize ( CheckpointIn cp)
overridevirtual

Reconstruct the state of this object from a checkpoint.

Note
CPU models should normally overload the unserializeThread() method instead of the unserialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.
Parameters
cpThe checkpoint use.

Implements gem5::Serializable.

Reimplemented in gem5::CheckerCPU, and gem5::MinorCPU.

Definition at line 651 of file base.cc.

References _pid, _switchedOut, gem5::csprintf(), gem5::ArmISA::i, instCnt, interrupts, numThreads, UNSERIALIZE_SCALAR, and unserializeThread().

Referenced by gem5::MinorCPU::unserialize().

◆ unserializeThread()

virtual void gem5::BaseCPU::unserializeThread ( CheckpointIn cp,
ThreadID  tid 
)
inlinevirtual

Unserialize one thread.

Parameters
cpThe checkpoint use.
tidID of the current thread.

Reimplemented in gem5::o3::CPU, gem5::BaseSimpleCPU, gem5::MinorCPU, and gem5::BaseKvmCPU.

Definition at line 421 of file base.hh.

Referenced by unserialize().

◆ updateCycleCounters()

void gem5::BaseCPU::updateCycleCounters ( CPUState  state)
inlineprotected

◆ verifyMemoryMode()

virtual void gem5::BaseCPU::verifyMemoryMode ( ) const
inlinevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented in gem5::TimingSimpleCPU, gem5::o3::CPU, gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, and gem5::NonCachingSimpleCPU.

Definition at line 368 of file base.hh.

Referenced by init().

◆ wakeup()

virtual void gem5::BaseCPU::wakeup ( ThreadID  tid)
pure virtual

◆ workItemBegin()

void gem5::BaseCPU::workItemBegin ( )
inline

Definition at line 219 of file base.hh.

References baseStats, and gem5::BaseCPU::BaseCPUStats::numWorkItemsStarted.

Referenced by gem5::pseudo_inst::workbegin().

◆ workItemEnd()

void gem5::BaseCPU::workItemEnd ( )
inline

Definition at line 220 of file base.hh.

References baseStats, and gem5::BaseCPU::BaseCPUStats::numWorkItemsCompleted.

Referenced by gem5::pseudo_inst::workend().

Member Data Documentation

◆ _cacheLineSize

const unsigned int gem5::BaseCPU::_cacheLineSize
protected

Cache the cache line size that we get from the system.

Definition at line 149 of file base.hh.

Referenced by cacheLineSize().

◆ _cpuId

int gem5::BaseCPU::_cpuId
protected

Definition at line 119 of file base.hh.

Referenced by cpuId(), registerThreadContexts(), and takeOverFrom().

◆ _dataRequestorId

RequestorID gem5::BaseCPU::_dataRequestorId
protected

data side request id that must be placed in all requests

Definition at line 132 of file base.hh.

Referenced by dataRequestorId(), and gem5::o3::CPU::htmSendAbortSignal().

◆ _instRequestorId

RequestorID gem5::BaseCPU::_instRequestorId
protected

instruction side request id that must be placed in all requests

Definition at line 129 of file base.hh.

Referenced by instRequestorId().

◆ _pid

uint32_t gem5::BaseCPU::_pid
protected

The current OS process ID that is executing on this processor.

This is used to generate a taskId

Definition at line 143 of file base.hh.

Referenced by getPid(), serialize(), setPid(), takeOverFrom(), and unserialize().

◆ _socketId

const uint32_t gem5::BaseCPU::_socketId
protected

Each cpu will have a socket ID that corresponds to its physical location in the system.

This is usually used to bucket cpu cores under single DVFS domain. This information may also be required by the OS to identify the cpu core grouping (as in the case of ARM via MPIDR register)

Definition at line 126 of file base.hh.

Referenced by socketId().

◆ _switchedOut

bool gem5::BaseCPU::_switchedOut
protected

Is the CPU switched out or active?

Definition at line 146 of file base.hh.

Referenced by serialize(), startup(), switchedOut(), switchOut(), takeOverFrom(), and unserialize().

◆ _taskId

uint32_t gem5::BaseCPU::_taskId
protected

An intrenal representation of a task identifier within gem5.

This is used so the CPU can add which taskId (which is an internal representation of the OS process ID) to each request so components in the memory system can track which process IDs are ultimately interacting with them

Definition at line 139 of file base.hh.

Referenced by takeOverFrom(), and taskId().

◆ addressMonitor

std::vector<AddressMonitor> gem5::BaseCPU::addressMonitor
private

Definition at line 603 of file base.hh.

Referenced by armMonitor(), getCpuAddrMonitor(), mwait(), and mwaitAtomic().

◆ baseStats

gem5::BaseCPU::BaseCPUStats gem5::BaseCPU::baseStats

◆ cpuList

std::vector< BaseCPU * > gem5::BaseCPU::cpuList
staticprivate

Static global cpu list.

Definition at line 560 of file base.hh.

Referenced by numSimulatedCPUs(), numSimulatedInsts(), and numSimulatedOps().

◆ currentFunctionEnd

Addr gem5::BaseCPU::currentFunctionEnd
private

Definition at line 554 of file base.hh.

Referenced by traceFunctionsInternal().

◆ currentFunctionStart

Addr gem5::BaseCPU::currentFunctionStart
private

Definition at line 553 of file base.hh.

Referenced by traceFunctionsInternal().

◆ enterPwrGatingEvent

EventFunctionWrapper gem5::BaseCPU::enterPwrGatingEvent
protected

◆ functionEntryTick

Tick gem5::BaseCPU::functionEntryTick
private

Definition at line 555 of file base.hh.

Referenced by traceFunctionsInternal().

◆ functionTraceStream

std::ostream* gem5::BaseCPU::functionTraceStream
private

Definition at line 552 of file base.hh.

Referenced by traceFunctionsInternal().

◆ functionTracingEnabled

bool gem5::BaseCPU::functionTracingEnabled
private

Definition at line 551 of file base.hh.

Referenced by enableFunctionTrace(), and traceFunctions().

◆ globalStats

std::unique_ptr< BaseCPU::GlobalStats > gem5::BaseCPU::globalStats
staticprotected

Pointer to the global stat structure.

This needs to be constructed from regStats since we merge it into the root group.

Definition at line 167 of file base.hh.

Referenced by regStats().

◆ instCnt

Tick gem5::BaseCPU::instCnt
protected

Instruction count used for SPARC misc register.

Todo:
unify this with the counters that cpus individually keep

Definition at line 113 of file base.hh.

Referenced by gem5::TimingSimpleCPU::completeIfetch(), instCount(), serialize(), gem5::AtomicSimpleCPU::tick(), and unserialize().

◆ interrupts

std::vector<BaseInterrupts*> gem5::BaseCPU::interrupts
protected

◆ invldPid

const uint32_t gem5::BaseCPU::invldPid = std::numeric_limits<uint32_t>::max()
static

Invalid or unknown Pid.

Possible when operating system is not present or has not assigned a pid yet

Definition at line 271 of file base.hh.

Referenced by gem5::ArmISA::FsLinux::startup().

◆ numThreads

ThreadID gem5::BaseCPU::numThreads

Number of threads we're actually simulating (<= SMT_MAX_THREADS).

This is a constant for the duration of the simulation.

Definition at line 368 of file base.hh.

Referenced by gem5::AtomicSimpleCPU::activateContext(), gem5::TimingSimpleCPU::activateContext(), armMonitor(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::minor::Execute::checkInterrupts(), gem5::o3::Commit::CommitStats::CommitStats(), gem5::o3::CPU::CPUStats::CPUStats(), gem5::minor::Execute::drain(), gem5::minor::Pipeline::drainResume(), gem5::MinorCPU::drainResume(), gem5::AtomicSimpleCPU::drainResume(), gem5::TimingSimpleCPU::drainResume(), gem5::minor::Execute::drainResume(), gem5::minor::Decode::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::minor::Execute::evaluate(), gem5::minor::Fetch1::evaluate(), gem5::o3::IEW::IEWStats::ExecutedInstStats::ExecutedInstStats(), getCpuAddrMonitor(), gem5::o3::CPU::getFreeTid(), gem5::o3::IEW::IEWStats::IEWStats(), gem5::BaseKvmCPU::init(), gem5::o3::CPU::init(), init(), gem5::o3::InstructionQueue::IQStats::IQStats(), gem5::minor::Execute::isDrained(), gem5::minor::Fetch1::isDrained(), gem5::MinorCPU::MinorCPU(), gem5::minor::MinorStats::MinorStats(), mwait(), mwaitAtomic(), gem5::MinorCPU::randomPriority(), gem5::AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), gem5::AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), gem5::TimingSimpleCPU::DcachePort::recvFunctionalSnoop(), gem5::o3::LSQ::DcachePort::recvTimingSnoopReq(), gem5::TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), gem5::minor::LSQ::recvTimingSnoopReq(), registerThreadContexts(), gem5::MinorCPU::roundRobinPriority(), serialize(), gem5::MinorCPU::startup(), gem5::AtomicSimpleCPU::suspendContext(), gem5::TimingSimpleCPU::suspendContext(), gem5::BaseSimpleCPU::swapActiveThread(), takeOverFrom(), gem5::TimingSimpleCPU::threadSnoop(), gem5::AtomicSimpleCPU::threadSnoop(), gem5::minor::LSQ::threadSnoop(), gem5::AtomicSimpleCPU::tick(), unserialize(), gem5::MinorCPU::wakeup(), and gem5::minor::Execute::~Execute().

◆ powerGatingOnIdle

const bool gem5::BaseCPU::powerGatingOnIdle
protected

Definition at line 622 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ ppActiveCycles

probing::PMUUPtr gem5::BaseCPU::ppActiveCycles
protected

CPU cycle counter, only counts if any thread contexts is active.

Definition at line 499 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ ppAllCycles

probing::PMUUPtr gem5::BaseCPU::ppAllCycles
protected

CPU cycle counter even if any thread Context is suspended.

Definition at line 496 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ ppRetiredBranches

probing::PMUUPtr gem5::BaseCPU::ppRetiredBranches
protected

Retired branches (any type)

Definition at line 493 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInsts

probing::PMUUPtr gem5::BaseCPU::ppRetiredInsts
protected

Instruction commit probe point.

This probe point is triggered whenever one or more instructions are committed. It is normally triggered once for every instruction. However, CPU models committing bundles of instructions may call notify once for the entire bundle.

Definition at line 484 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInstsPC

probing::PMUUPtr gem5::BaseCPU::ppRetiredInstsPC
protected

Definition at line 485 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredLoads

probing::PMUUPtr gem5::BaseCPU::ppRetiredLoads
protected

Retired load instructions.

Definition at line 488 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredStores

probing::PMUUPtr gem5::BaseCPU::ppRetiredStores
protected

Retired store instructions.

Definition at line 490 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppSleeping

ProbePointArg<bool>* gem5::BaseCPU::ppSleeping
protected

ProbePoint that signals transitions of threadContexts sets.

The ProbePoint reports information through it bool parameter.

  • If the parameter is true then the last enabled threadContext of the CPU object was disabled.
  • If the parameter is false then a threadContext was enabled, all the remaining threadContexts are disabled.

Definition at line 509 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ previousCycle

Cycles gem5::BaseCPU::previousCycle
protected

Definition at line 519 of file base.hh.

Referenced by takeOverFrom(), and updateCycleCounters().

◆ previousState

CPUState gem5::BaseCPU::previousState
protected

Definition at line 520 of file base.hh.

Referenced by takeOverFrom(), and updateCycleCounters().

◆ pwrGatingLatency

const Cycles gem5::BaseCPU::pwrGatingLatency
protected

Definition at line 621 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ syscallRetryLatency

Cycles gem5::BaseCPU::syscallRetryLatency

◆ system

System* gem5::BaseCPU::system

◆ threadContexts

std::vector<ThreadContext *> gem5::BaseCPU::threadContexts
protected

◆ tracer

Trace::InstTracer* gem5::BaseCPU::tracer
protected

Definition at line 264 of file base.hh.

Referenced by getTracer(), and gem5::BaseSimpleCPU::preExecute().


The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:27:19 for gem5 by doxygen 1.8.17