#include <base.hh>

Inheritance diagram for gem5::BaseCPU:

Classes
struct	BaseCPUStats

struct	CommitCPUStats

struct	ExecuteCPUStats

struct	FetchCPUStats

struct	GlobalStats
	Global CPU statistics that are merged into the Root object. More...

Public Member Functions
virtual Port &	getDataPort ()=0
	Purely virtual method that returns a reference to the data port.

virtual Port &	getInstPort ()=0
	Purely virtual method that returns a reference to the instruction port.

int	cpuId () const
	Reads this CPU's ID.

uint32_t	socketId () const
	Reads this CPU's Socket ID.

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID.

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID.

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU.

uint32_t	taskId () const
	Get cpu task id.

void	taskId (uint32_t id)
	Set cpu task id.

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

virtual void	wakeup (ThreadID tid)=0

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer.

virtual void	activateContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now active.

virtual void	suspendContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now suspended.

virtual void	haltContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now halted.

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num.

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it.

unsigned	numContexts ()
	Get the number of thread contexts available.

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID.

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected.

void	startup () override
	startup() is the final initialization call before simulation.

void	regStats () override
	Callback to set stat parameters.

void	regProbePoints () override
	Register probe points for this object.

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	switchOut ()
	Prepare for another CPU to take over execution.

virtual void	takeOverFrom (BaseCPU *cpu)
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

virtual void	setReset (bool state)
	Set the reset of the CPU to be either asserted or deasserted.

void	flushTLBs ()
	Flush all TLBs in the CPU.

bool	switchedOut () const
	Determine if the CPU is switched out.

virtual void	verifyMemoryMode () const
	Verify that the system is in a memory mode supported by the CPU.

Addr	cacheLineSize () const
	Get the cache line size of the system.

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream.

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint.

virtual void	serializeThread (CheckpointOut &cp, ThreadID tid) const
	Serialize a single thread.

virtual void	unserializeThread (CheckpointIn &cp, ThreadID tid)
	Unserialize one thread.

virtual Counter	totalInsts () const =0

virtual Counter	totalOps () const =0

void	scheduleInstStop (ThreadID tid, Counter insts, std::string cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions.

void	scheduleSimpointsInstStop (std::vector< Counter > inst_starts)
	Schedule simpoint events using the scheduleInstStop function.

void	scheduleInstStopAnyThread (Counter max_insts)
	Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function.

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU.

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Static Public Member Functions
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS).

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

std::vector< std::unique_ptr< FetchCPUStats > >	fetchStats

std::vector< std::unique_ptr< ExecuteCPUStats > >	executeStats

std::vector< std::unique_ptr< CommitCPUStats > >	commitStats

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Static Public Attributes
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid.

Protected Types
enum	CPUState { CPU_STATE_ON , CPU_STATE_SLEEP , CPU_STATE_WAKEUP }

Protected Member Functions
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression

void	enterPwrGating ()

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain.

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Protected Attributes
Tick	instCnt
	Instruction count used for SPARC misc register.

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system.

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5.

uint32_t	_pid
	The current OS process ID that is executing on this processor.

bool	_switchedOut
	Is the CPU switched out or active?

const Addr	_cacheLineSize
	Cache the cache line size that we get from the system.

SignalSinkPort< bool >	modelResetPort

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Static Protected Attributes
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure.

Private Member Functions
void	enableFunctionTrace ()

void	traceFunctionsInternal (Addr pc)

Private Attributes
bool	functionTracingEnabled

std::ostream *	functionTraceStream

Addr	currentFunctionStart

Addr	currentFunctionEnd

Tick	functionEntryTick

std::vector< AddressMonitor >	addressMonitor

Static Private Attributes
static std::vector< BaseCPU * >	cpuList
	Static global cpu list.

PMU Probe points.
probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point.

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions.

probing::PMUUPtr	ppRetiredStores
	Retired store instructions.

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type)

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended.

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active.

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets.

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction.

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object.

Additional Inherited Members
Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Detailed Description

Definition at line 104 of file base.hh.

Member Enumeration Documentation

◆ CPUState

enum gem5::BaseCPU::CPUState

protected

Enumerator
CPU_STATE_ON
CPU_STATE_SLEEP
CPU_STATE_WAKEUP

Definition at line 549 of file base.hh.

Constructor & Destructor Documentation

◆ BaseCPU()

gem5::BaseCPU::BaseCPU	(	const Params &	params,
		bool	is_checker = false )

Definition at line 129 of file base.cc.

References enterPwrGating().

◆ ~BaseCPU()

gem5::BaseCPU::~BaseCPU ( )

virtual

Reimplemented in gem5::Iris::BaseCPU.

Definition at line 226 of file base.cc.

Member Function Documentation

◆ activateContext()

void gem5::BaseCPU::activateContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now active.

Reimplemented in gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, gem5::MinorCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Definition at line 530 of file base.cc.

References CPU_STATE_WAKEUP, gem5::EventManager::deschedule(), DPRINTF, enterPwrGatingEvent, modelResetPort, gem5::ClockedObject::powerState, gem5::Event::scheduled(), gem5::PowerState::set(), gem5::SignalSinkPort< State >::state(), threadContexts, and updateCycleCounters().

Referenced by gem5::SimpleThread::activate(), gem5::AtomicSimpleCPU::activateContext(), gem5::MinorCPU::activateContext(), gem5::o3::CPU::activateContext(), and gem5::TimingSimpleCPU::activateContext().

◆ armMonitor()

void gem5::BaseCPU::armMonitor	(	ThreadID	tid,
		Addr	address )

Definition at line 242 of file base.cc.

References addressMonitor, gem5::AddressMonitor::armed, DPRINTF, numThreads, gem5::AddressMonitor::pAddr, and gem5::AddressMonitor::vAddr.

Referenced by gem5::CheckerCPU::armMonitor(), gem5::minor::ExecContext::armMonitor(), gem5::o3::DynInst::armMonitor(), and gem5::SimpleExecContext::armMonitor().

◆ cacheLineSize()

Addr gem5::BaseCPU::cacheLineSize ( ) const

inline

Get the cache line size of the system.

Definition at line 397 of file base.hh.

References _cacheLineSize.

Referenced by gem5::AtomicSimpleCPU::amoMem(), gem5::AtomicSimpleCPU::AtomicCPUDPort::AtomicCPUDPort(), gem5::o3::LSQUnit::cacheLineSize(), gem5::TimingSimpleCPU::DcachePort::DcachePort(), gem5::minor::Fetch1::Fetch1(), gem5::AtomicSimpleCPU::genMemFragmentRequest(), gem5::CheckerCPU::genMemFragmentRequest(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), mwait(), mwaitAtomic(), gem5::o3::LSQ::pushRequest(), gem5::o3::LSQUnit::resetState(), and gem5::TimingSimpleCPU::writeMem().

◆ checkInterrupts()

bool gem5::BaseCPU::checkInterrupts ( ThreadID tid ) const

inline

Definition at line 254 of file base.hh.

References gem5::FullSystem, and interrupts.

Referenced by gem5::BaseSimpleCPU::checkForInterrupts(), gem5::o3::Commit::commit(), gem5::o3::Commit::commitInsts(), gem5::o3::Commit::handleInterrupt(), and gem5::minor::Execute::isInterrupted().

◆ clearInterrupt()

void gem5::BaseCPU::clearInterrupt	(	ThreadID	tid,
		int	int_num,
		int	index )

inline

Definition at line 242 of file base.hh.

References gem5::MipsISA::index, and interrupts.

Referenced by gem5::SparcISA::ISA::checkSoftInt(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::ArmISA::AbortFault< T >::invoke(), gem5::ArmISA::ArmSev::invoke(), gem5::ArmISA::SystemError::invoke(), gem5::SparcISA::ISA::setFSReg(), and gem5::SparcISA::ISA::setMiscReg().

◆ clearInterrupts()

void gem5::BaseCPU::clearInterrupts ( ThreadID tid )

inline

Definition at line 248 of file base.hh.

References interrupts.

Referenced by gem5::o3::Commit::commitInsts(), and gem5::ArmISA::Reset::invoke().

◆ contextToThread()

ThreadID gem5::BaseCPU::contextToThread ( ContextID cid )

inline

Convert ContextID to threadID.

Definition at line 299 of file base.hh.

References threadContexts.

Referenced by gem5::o3::LSQ::completeDataAccess(), gem5::o3::Fetch::finishTranslation(), gem5::o3::Fetch::processCacheCompletion(), gem5::o3::LSQ::pushRequest(), gem5::o3::LSQ::read(), gem5::o3::LSQ::recvTimingResp(), gem5::minor::LSQ::tryToSend(), and gem5::o3::LSQ::write().

◆ cpuId()

int gem5::BaseCPU::cpuId ( ) const

inline

Reads this CPU's ID.

Definition at line 187 of file base.hh.

References _cpuId.

Referenced by gem5::Iris::ThreadContext::cpuId(), gem5::o3::DynInst::cpuId(), gem5::o3::ThreadContext::cpuId(), gem5::ThreadState::cpuId(), takeOverFrom(), gem5::trace::TarmacContext::tarmacCpuName(), gem5::pseudo_inst::workbegin(), and gem5::pseudo_inst::workend().

◆ dataRequestorId()

RequestorID gem5::BaseCPU::dataRequestorId ( ) const

inline

Reads this CPU's unique data requestor ID.

Definition at line 193 of file base.hh.

References _dataRequestorId.

Referenced by gem5::AtomicSimpleCPU::amoMem(), gem5::o3::LSQ::checkStaleTranslations(), gem5::BaseKvmCPU::doMMIOAccess(), gem5::AtomicSimpleCPU::genMemFragmentRequest(), gem5::X86KvmCPU::handleKvmExitIO(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), gem5::TimingSimpleCPU::initiateMemRead(), mwaitAtomic(), gem5::minor::LSQ::pushRequest(), gem5::TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), gem5::o3::DynInst::requestorId(), and gem5::TimingSimpleCPU::writeMem().

◆ deschedulePowerGatingEvent()

void gem5::BaseCPU::deschedulePowerGatingEvent ( )

Definition at line 494 of file base.cc.

References gem5::EventManager::deschedule(), enterPwrGatingEvent, and gem5::Event::scheduled().

Referenced by gem5::AtomicSimpleCPU::drain(), gem5::MinorCPU::drain(), gem5::o3::CPU::drain(), and gem5::TimingSimpleCPU::drain().

◆ enableFunctionTrace()

void gem5::BaseCPU::enableFunctionTrace ( )

private

Definition at line 221 of file base.cc.

References functionTracingEnabled.

◆ enterPwrGating()

void gem5::BaseCPU::enterPwrGating ( void )

protected

Definition at line 582 of file base.cc.

References gem5::ClockedObject::powerState, and gem5::PowerState::set().

Referenced by BaseCPU().

◆ findContext()

int gem5::BaseCPU::findContext ( ThreadContext * tc )

Given a Thread Context pointer return the thread num.

Definition at line 519 of file base.cc.

References threadContexts.

◆ flushTLBs()

void gem5::BaseCPU::flushTLBs ( )

Flush all TLBs in the CPU.

This method is mainly used to flush stale translations when switching CPUs. It is also exported to the Python world to allow it to request a TLB flush after draining the CPU to make it easier to compare traces when debugging handover/checkpointing.

Definition at line 690 of file base.cc.

References gem5::BaseMMU::flushAll(), gem5::ThreadContext::getCheckerCpuPtr(), gem5::CheckerCPU::getMMUPtr(), gem5::ThreadContext::getMMUPtr(), gem5::ArmISA::i, and threadContexts.

Referenced by switchOut().

◆ getContext()

virtual ThreadContext * gem5::BaseCPU::getContext ( int tn )

inlinevirtual

Given a thread num get tho thread context for it.

Reimplemented in gem5::BaseKvmCPU.

Definition at line 288 of file base.hh.

References threadContexts.

◆ getCpuAddrMonitor()

AddressMonitor * gem5::BaseCPU::getCpuAddrMonitor ( ThreadID tid )

inline

Definition at line 656 of file base.hh.

References addressMonitor, and numThreads.

Referenced by gem5::CheckerCPU::getAddrMonitor(), gem5::minor::ExecContext::getAddrMonitor(), gem5::o3::DynInst::getAddrMonitor(), gem5::SimpleExecContext::getAddrMonitor(), gem5::AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), gem5::TimingSimpleCPU::DcachePort::recvFunctionalSnoop(), gem5::minor::LSQ::recvTimingSnoopReq(), gem5::o3::LSQ::DcachePort::recvTimingSnoopReq(), gem5::TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), gem5::AtomicSimpleCPU::threadSnoop(), gem5::minor::LSQ::threadSnoop(), gem5::TimingSimpleCPU::threadSnoop(), and gem5::BaseSimpleCPU::wakeup().

◆ getCurrentInstCount()

Tick gem5::BaseCPU::getCurrentInstCount ( ThreadID tid )

Get the number of instructions executed by the specified thread on this CPU.

Used by Python to control simulation.

Parameters

tid	Thread monitor

Returns: Number of instructions executed

Definition at line 751 of file base.cc.

References threadContexts.

Referenced by scheduleInstStop().

◆ getDataPort()

virtual Port & gem5::BaseCPU::getDataPort ( )

pure virtual

Purely virtual method that returns a reference to the data port.

All subclasses must implement this method.

Returns: a reference to the data port

Implemented in gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, gem5::CheckerCPU, gem5::Iris::BaseCPU, gem5::MinorCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Referenced by getPort(), gem5::ThreadContext::sendFunctional(), and takeOverFrom().

◆ getInstPort()

virtual Port & gem5::BaseCPU::getInstPort ( )

pure virtual

Purely virtual method that returns a reference to the instruction port.

All subclasses must implement this method.

Returns: a reference to the instruction port

Implemented in gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, gem5::CheckerCPU, gem5::Iris::BaseCPU, gem5::MinorCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Referenced by getPort(), and takeOverFrom().

◆ getInterruptController()

BaseInterrupts * gem5::BaseCPU::getInterruptController ( ThreadID tid )

inline

Definition at line 228 of file base.hh.

References interrupts.

Referenced by gem5::minor::Execute::checkInterrupts(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::minor::Execute::hasInterrupt(), gem5::ArmISA::ISA::readMiscReg(), gem5::RiscvISA::ISA::readMiscReg(), gem5::RiscvISA::ISA::setMiscReg(), and gem5::minor::Execute::takeInterrupt().

◆ getPid()

uint32_t gem5::BaseCPU::getPid ( ) const

inline

Definition at line 215 of file base.hh.

References _pid.

Referenced by takeOverFrom().

◆ getPort()

Port & gem5::BaseCPU::getPort	(	const std::string &	if_name,
		PortID	idx = InvalidPortID )

overridevirtual

Get a port on this CPU.

All CPUs have a data and instruction port, and this method uses getDataPort and getInstPort of the subclasses to resolve the two ports.

Parameters

if_name	the port name
idx	ignored index

Returns: a reference to the port with the given name

Reimplemented from gem5::SimObject.

Reimplemented in gem5::fastmodel::CortexA76, and gem5::fastmodel::CortexR52.

Definition at line 455 of file base.cc.

References getDataPort(), getInstPort(), gem5::SimObject::getPort(), and modelResetPort.

Referenced by gem5::fastmodel::CortexA76::getPort().

◆ getTracer()

trace::InstTracer * gem5::BaseCPU::getTracer ( )

inline

Provide access to the tracer pointer.

Definition at line 272 of file base.hh.

References tracer.

Referenced by gem5::o3::Fetch::buildInst().

◆ haltContext()

void gem5::BaseCPU::haltContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now halted.

Reimplemented in gem5::BaseKvmCPU, gem5::BaseSimpleCPU, and gem5::o3::CPU.

Definition at line 576 of file base.cc.

References CPU_STATE_SLEEP, and updateCycleCounters().

Referenced by gem5::SimpleThread::halt().

◆ htmSendAbortSignal()

virtual void gem5::BaseCPU::htmSendAbortSignal	(	ThreadID	tid,
		uint64_t	htm_uid,
		HtmFailureFaultCause	cause )

inlinevirtual

This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away.

This is called in the transaction's very last breath in the core. Afterwards, the core throws away its speculative state and resumes execution at the point the transaction started, i.e. reverses time. When instruction execution resumes, the core expects the memory subsystem to be in a stable, i.e. pre-speculative, state as well.

Reimplemented in gem5::AtomicSimpleCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Definition at line 673 of file base.hh.

References panic.

Referenced by gem5::SimpleThread::htmAbortTransaction().

◆ init()

void gem5::BaseCPU::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Reimplemented in gem5::BaseKvmCPU, gem5::CheckerCPU, gem5::MinorCPU, gem5::o3::CPU, gem5::TimingSimpleCPU, and gem5::X86KvmCPU.

Definition at line 310 of file base.cc.

References gem5::MipsISA::event, numThreads, gem5::SimObject::params(), registerThreadContexts(), scheduleInstStopAnyThread(), scheduleSimpointsInstStop(), threadContexts, and verifyMemoryMode().

Referenced by gem5::AtomicSimpleCPU::init(), gem5::BaseKvmCPU::init(), gem5::MinorCPU::init(), gem5::o3::CPU::init(), and gem5::TimingSimpleCPU::init().

◆ instCount()

Tick gem5::BaseCPU::instCount ( )

inline

Definition at line 221 of file base.hh.

References instCnt.

Referenced by gem5::SparcISA::ISA::processHSTickCompare(), gem5::SparcISA::ISA::processSTickCompare(), gem5::SparcISA::ISA::readMiscReg(), gem5::SparcISA::ISA::setFSReg(), and gem5::SparcISA::ISA::setMiscReg().

◆ instRequestorId()

RequestorID gem5::BaseCPU::instRequestorId ( ) const

inline

Reads this CPU's unique instruction requestor ID.

Definition at line 195 of file base.hh.

References _instRequestorId.

Referenced by gem5::o3::Fetch::fetchCacheLine(), gem5::minor::Fetch1::fetchLine(), and gem5::BaseSimpleCPU::setupFetchRequest().

◆ mwait()

bool gem5::BaseCPU::mwait	(	ThreadID	tid,
		PacketPtr	pkt )

Definition at line 254 of file base.cc.

References addressMonitor, cacheLineSize(), DPRINTF, gem5::Packet::getAddr(), gem5::AddressMonitor::gotWakeup, gem5::ArmISA::mask, numThreads, gem5::AddressMonitor::pAddr, gem5::Packet::req, gem5::AddressMonitor::vAddr, and gem5::AddressMonitor::waiting.

Referenced by gem5::CheckerCPU::mwait(), gem5::minor::ExecContext::mwait(), gem5::o3::DynInst::mwait(), and gem5::SimpleExecContext::mwait().

◆ mwaitAtomic()

void gem5::BaseCPU::mwaitAtomic	(	ThreadID	tid,
		ThreadContext *	tc,
		BaseMMU *	mmu )

◆ numContexts()

unsigned gem5::BaseCPU::numContexts ( )

inline

Get the number of thread contexts available.

Definition at line 292 of file base.hh.

References threadContexts.

Referenced by gem5::o3::LSQUnit::checkSnoop().

◆ numSimulatedCPUs()

static int gem5::BaseCPU::numSimulatedCPUs ( )

inlinestatic

Definition at line 607 of file base.hh.

References cpuList.

◆ numSimulatedInsts()

static Counter gem5::BaseCPU::numSimulatedInsts ( )

inlinestatic

Definition at line 609 of file base.hh.

References cpuList, gem5::ArmISA::i, gem5::statistics::total, and totalInsts().

Referenced by gem5::BaseCPU::GlobalStats::GlobalStats(), and gem5::o3::ElasticTrace::regEtraceListeners().

◆ numSimulatedOps()

static Counter gem5::BaseCPU::numSimulatedOps ( )

inlinestatic

Definition at line 621 of file base.hh.

References cpuList, gem5::ArmISA::i, gem5::statistics::total, and totalOps().

Referenced by gem5::BaseCPU::GlobalStats::GlobalStats().

◆ PARAMS()

gem5::BaseCPU::PARAMS ( BaseCPU )

◆ pmuProbePoint()

probing::PMUUPtr gem5::BaseCPU::pmuProbePoint ( const char * name )

protected

Helper method to instantiate probe points belonging to this object.

Parameters

name	Name of the probe point.

Returns: A unique_ptr to the new probe point.

Definition at line 365 of file base.cc.

References gem5::SimObject::getProbeManager(), and gem5::Named::name().

Referenced by regProbePoints().

◆ postInterrupt()

void gem5::BaseCPU::postInterrupt	(	ThreadID	tid,
		int	int_num,
		int	index )

Definition at line 231 of file base.cc.

References gem5::FullSystem, gem5::System::futexMap, gem5::MipsISA::index, interrupts, gem5::FutexMap::is_waiting(), system, threadContexts, and wakeup().

Referenced by gem5::SparcISA::ISA::checkSoftInt(), gem5::RiscvISA::Interrupts::raiseInterruptPin(), gem5::ArmISA::sendEvent(), gem5::SparcISA::ISA::setFSReg(), and gem5::SparcISA::ISA::setMiscReg().

◆ probeInstCommit()

void gem5::BaseCPU::probeInstCommit	(	const StaticInstPtr &	inst,
		Addr	pc )

virtual

Helper method to trigger PMU probes for a committed instruction.

Parameters

inst	Instruction that just committed
pc	PC of the instruction that just committed

Definition at line 390 of file base.cc.

References gem5::StaticInst::isAtomic(), gem5::StaticInst::isControl(), gem5::StaticInst::isLastMicroop(), gem5::StaticInst::isLoad(), gem5::StaticInst::isMicroop(), gem5::StaticInst::isStore(), gem5::MipsISA::pc, ppRetiredBranches, ppRetiredInsts, ppRetiredInstsPC, ppRetiredLoads, and ppRetiredStores.

Referenced by gem5::minor::Execute::doInstCommitAccounting(), gem5::o3::CPU::instDone(), and gem5::BaseSimpleCPU::postExecute().

◆ registerThreadContexts()

void gem5::BaseCPU::registerThreadContexts ( )

Definition at line 471 of file base.cc.

References gem5::Process::assignThreadContext(), gem5::ThreadContext::contextId(), fatal_if, gem5::FullSystem, gem5::ThreadContext::getIsaPtr(), gem5::ThreadContext::getProcessPtr(), interrupts, gem5::System::multiThread, gem5::Named::name(), numThreads, gem5::System::registerThreadContext(), gem5::BaseISA::setThreadContext(), system, and threadContexts.

Referenced by init().

◆ regProbePoints()

void gem5::BaseCPU::regProbePoints ( )

overridevirtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented from gem5::SimObject.

Reimplemented in gem5::o3::CPU.

Definition at line 374 of file base.cc.

References gem5::SimObject::getProbeManager(), pmuProbePoint(), ppActiveCycles, ppAllCycles, ppRetiredBranches, ppRetiredInsts, ppRetiredInstsPC, ppRetiredLoads, ppRetiredStores, and ppSleeping.

Referenced by gem5::AtomicSimpleCPU::regProbePoints(), and gem5::o3::CPU::regProbePoints().

◆ regStats()

void gem5::BaseCPU::regStats ( )

overridevirtual

Callback to set stat parameters.

This callback is typically used for complex stats (e.g., distributions) that need parameters in addition to a name and a description. Stat names and descriptions should typically be set from the constructor usingo from the constructor using the ADD_STAT macro.

Reimplemented from gem5::statistics::Group.

Reimplemented in gem5::MinorCPU.

Definition at line 431 of file base.cc.

References gem5::ccprintf(), globalStats, gem5::ArmISA::i, gem5::Named::name(), gem5::statistics::Group::regStats(), gem5::Root::root(), and threadContexts.

Referenced by gem5::MinorCPU::regStats().

◆ scheduleInstStop()

void gem5::BaseCPU::scheduleInstStop	(	ThreadID	tid,
		Counter	insts,
		std::string	cause )

Schedule an event that exits the simulation loops after a predefined number of instructions.

This method is usually called from the configuration script to get an exit event some time in the future. It is typically used when the script wants to simulate for a specific number of instructions rather than ticks.

Parameters

tid	Thread monitor.
insts	Number of instructions into the future.
cause	Cause to signal in the exit event.

Definition at line 742 of file base.cc.

References gem5::MipsISA::event, getCurrentInstCount(), and threadContexts.

Referenced by scheduleInstStopAnyThread(), and scheduleSimpointsInstStop().

◆ scheduleInstStopAnyThread()

void gem5::BaseCPU::scheduleInstStopAnyThread ( Counter max_insts )

Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function.

This is used to raise a MAX_INSTS exit event in thegem5 standard library

Parameters

max_insts Number of instructions into the future.

Definition at line 818 of file base.cc.

References numThreads, and scheduleInstStop().

Referenced by init().

◆ schedulePowerGatingEvent()

void gem5::BaseCPU::schedulePowerGatingEvent ( )

Definition at line 502 of file base.cc.

References gem5::ThreadContext::Active, gem5::Clocked::clockEdge(), enterPwrGatingEvent, gem5::PowerState::get(), powerGatingOnIdle, gem5::ClockedObject::powerState, pwrGatingLatency, gem5::EventManager::schedule(), gem5::Event::scheduled(), and threadContexts.

Referenced by gem5::AtomicSimpleCPU::drainResume(), gem5::MinorCPU::drainResume(), gem5::o3::CPU::drainResume(), and gem5::TimingSimpleCPU::drainResume().

◆ scheduleSimpointsInstStop()

void gem5::BaseCPU::scheduleSimpointsInstStop ( std::vector< Counter > inst_starts )

Schedule simpoint events using the scheduleInstStop function.

This is used to raise a SIMPOINT_BEGIN exit event in the gem5 standard library.

Parameters

inst_starts A vector of number of instructions to start simpoints

Definition at line 809 of file base.cc.

References gem5::ArmISA::i, and scheduleInstStop().

Referenced by init().

◆ serialize()

void gem5::BaseCPU::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize this object to the given output stream.

Note: CPU models should normally overload the serializeThread() method instead of the serialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The stream to serialize to.

Implements gem5::Serializable.

Reimplemented in gem5::CheckerCPU, and gem5::MinorCPU.

Definition at line 704 of file base.cc.

References _pid, _switchedOut, gem5::csprintf(), gem5::ArmISA::i, instCnt, interrupts, numThreads, SERIALIZE_SCALAR, and serializeThread().

Referenced by gem5::MinorCPU::serialize().

◆ serializeThread()

virtual void gem5::BaseCPU::serializeThread	(	CheckpointOut &	cp,
		ThreadID	tid ) const

inlinevirtual

Serialize a single thread.

Parameters

cp	The stream to serialize to.
tid	ID of the current thread.

Reimplemented in gem5::BaseKvmCPU, gem5::BaseSimpleCPU, gem5::Iris::BaseCPU, gem5::MinorCPU, and gem5::o3::CPU.

Definition at line 429 of file base.hh.

Referenced by serialize().

◆ setPid()

void gem5::BaseCPU::setPid ( uint32_t pid )

inline

Definition at line 216 of file base.hh.

References _pid.

Referenced by gem5::ArmISA::DumpStats::process().

◆ setReset()

void gem5::BaseCPU::setReset ( bool state )

virtual

Set the reset of the CPU to be either asserted or deasserted.

When asserted, the CPU should be stopped and waiting. When deasserted, the CPU should start running again, unless some other condition would also prevent it. At the point the reset is deasserted, it should be reinitialized as defined by the ISA it's running and any other relevant part of its configuration (reset address, etc).

Parameters

state The new state of the reset signal to this CPU.

Definition at line 668 of file base.cc.

References interrupts, state, and threadContexts.

◆ socketId()

uint32_t gem5::BaseCPU::socketId ( ) const

inline

Reads this CPU's Socket ID.

Definition at line 190 of file base.hh.

References _socketId.

Referenced by gem5::Iris::ThreadContext::socketId(), gem5::o3::DynInst::socketId(), gem5::o3::ThreadContext::socketId(), and gem5::ThreadState::socketId().

◆ startup()

void gem5::BaseCPU::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Reimplemented in gem5::BaseKvmCPU, gem5::MinorCPU, gem5::o3::CPU, and gem5::X86KvmCPU.

Definition at line 349 of file base.cc.

References _switchedOut, gem5::PowerState::get(), gem5::SimObject::params(), gem5::ClockedObject::powerState, and gem5::PowerState::set().

Referenced by gem5::BaseKvmCPU::startup(), gem5::MinorCPU::startup(), and gem5::o3::CPU::startup().

◆ suspendContext()

void gem5::BaseCPU::suspendContext ( ThreadID thread_num )

virtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented in gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, gem5::MinorCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Definition at line 550 of file base.cc.

References gem5::Clocked::clockEdge(), CPU_STATE_SLEEP, DPRINTF, enterPwrGatingEvent, powerGatingOnIdle, gem5::ClockedObject::powerState, pwrGatingLatency, gem5::EventManager::schedule(), gem5::PowerState::set(), gem5::ThreadContext::Suspended, gem5::ArmISA::t, threadContexts, and updateCycleCounters().

Referenced by gem5::BaseSimpleCPU::haltContext(), gem5::SimpleThread::suspend(), gem5::AtomicSimpleCPU::suspendContext(), gem5::MinorCPU::suspendContext(), gem5::o3::CPU::suspendContext(), and gem5::TimingSimpleCPU::suspendContext().

◆ switchedOut()

bool gem5::BaseCPU::switchedOut ( ) const

inline

Determine if the CPU is switched out.

Returns: True if the CPU is switched out, false otherwise.

Definition at line 373 of file base.hh.

References _switchedOut.

Referenced by gem5::o3::CPU::activateContext(), gem5::o3::CPU::activateThread(), gem5::o3::LSQUnit::completeDataAccess(), gem5::o3::CPU::deactivateThread(), gem5::AtomicSimpleCPU::drain(), gem5::BaseKvmCPU::drain(), gem5::MinorCPU::drain(), gem5::o3::CPU::drain(), gem5::TimingSimpleCPU::drain(), gem5::AtomicSimpleCPU::drainResume(), gem5::BaseKvmCPU::drainResume(), gem5::MinorCPU::drainResume(), gem5::o3::CPU::drainResume(), gem5::TimingSimpleCPU::drainResume(), gem5::o3::Fetch::fetch(), gem5::o3::Fetch::fetchCacheLine(), gem5::o3::Fetch::finishTranslation(), gem5::o3::CPU::haltContext(), gem5::CPUProgressEvent::process(), gem5::o3::Fetch::processCacheCompletion(), gem5::o3::InstructionQueue::processFUCompletion(), gem5::o3::CPU::suspendContext(), gem5::MinorCPU::switchOut(), and gem5::o3::CPU::tick().

◆ switchOut()

void gem5::BaseCPU::switchOut ( )

virtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented in gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, gem5::Checker< class >, gem5::Checker< DynInstPtr >, gem5::Checker< gem5::RefCountingPtr >, gem5::MinorCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Definition at line 588 of file base.cc.

References _switchedOut, flushTLBs(), gem5::ClockedObject::powerState, and gem5::PowerState::set().

Referenced by gem5::AtomicSimpleCPU::switchOut(), gem5::BaseKvmCPU::switchOut(), gem5::MinorCPU::switchOut(), gem5::o3::CPU::switchOut(), and gem5::TimingSimpleCPU::switchOut().

◆ takeOverFrom()

void gem5::BaseCPU::takeOverFrom ( BaseCPU * cpu )

virtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented in gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, gem5::Checker< class >, gem5::Checker< DynInstPtr >, gem5::Checker< gem5::RefCountingPtr >, gem5::MinorCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Definition at line 602 of file base.cc.

References _cpuId, _pid, _switchedOut, _taskId, gem5::ThreadContext::contextId(), cpuId(), gem5::PowerState::get(), gem5::ThreadContext::getCheckerCpuPtr(), getDataPort(), getInstPort(), gem5::ThreadContext::getIsaPtr(), gem5::CheckerCPU::getMMUPtr(), gem5::ThreadContext::getMMUPtr(), getPid(), gem5::ArmISA::i, interrupts, gem5::Port::isConnected(), modelResetPort, numThreads, gem5::ClockedObject::powerState, previousCycle, previousState, gem5::System::replaceThreadContext(), gem5::PowerState::set(), gem5::BaseISA::setThreadContext(), system, gem5::BaseMMU::takeOverFrom(), gem5::Port::takeOverFrom(), gem5::ThreadContext::takeOverFrom(), taskId(), threadContexts, and gem5::ThreadContext::threadId().

Referenced by gem5::AtomicSimpleCPU::takeOverFrom(), gem5::BaseKvmCPU::takeOverFrom(), gem5::MinorCPU::takeOverFrom(), gem5::o3::CPU::takeOverFrom(), and gem5::TimingSimpleCPU::takeOverFrom().

◆ taskId() [1/2]

uint32_t gem5::BaseCPU::taskId ( ) const

inline

Get cpu task id.

Definition at line 211 of file base.hh.

References _taskId.

Referenced by gem5::AtomicSimpleCPU::amoMem(), gem5::TimingSimpleCPU::fetch(), gem5::o3::Fetch::fetchCacheLine(), gem5::o3::CPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::ArmISA::DumpStats::process(), gem5::o3::LSQ::pushRequest(), gem5::AtomicSimpleCPU::readMem(), takeOverFrom(), gem5::AtomicSimpleCPU::tick(), gem5::AtomicSimpleCPU::writeMem(), and gem5::TimingSimpleCPU::writeMem().

◆ taskId() [2/2]

void gem5::BaseCPU::taskId ( uint32_t id )

inline

Set cpu task id.

Definition at line 213 of file base.hh.

References _taskId, and gem5::ArmISA::id.

◆ totalInsts()

virtual Counter gem5::BaseCPU::totalInsts ( ) const

pure virtual

Implemented in gem5::BaseKvmCPU, gem5::BaseSimpleCPU, gem5::CheckerCPU, gem5::Iris::BaseCPU, gem5::MinorCPU, and gem5::o3::CPU.

Referenced by numSimulatedInsts(), and gem5::RiscvISA::ISA::readMiscReg().

◆ totalOps()

virtual Counter gem5::BaseCPU::totalOps ( ) const

pure virtual

Implemented in gem5::BaseKvmCPU, gem5::BaseSimpleCPU, gem5::CheckerCPU, gem5::Iris::BaseCPU, gem5::MinorCPU, and gem5::o3::CPU.

Referenced by numSimulatedOps(), and gem5::CPUProgressEvent::process().

◆ traceFunctions()

void gem5::BaseCPU::traceFunctions ( Addr pc )

inline

Definition at line 601 of file base.hh.

References functionTracingEnabled, gem5::MipsISA::pc, and traceFunctionsInternal().

Referenced by gem5::o3::Commit::commitInsts(), and gem5::BaseSimpleCPU::postExecute().

◆ traceFunctionsInternal()

void gem5::BaseCPU::traceFunctionsInternal ( Addr pc )

private

Definition at line 780 of file base.cc.

References gem5::ccprintf(), gem5::csprintf(), currentFunctionEnd, currentFunctionStart, gem5::curTick(), gem5::loader::debugSymbolTable, gem5::loader::SymbolTable::findNearest(), functionEntryTick, functionTraceStream, and gem5::MipsISA::pc.

Referenced by traceFunctions().

◆ unserialize()

void gem5::BaseCPU::unserialize ( CheckpointIn & cp )

overridevirtual

Reconstruct the state of this object from a checkpoint.

Note: CPU models should normally overload the unserializeThread() method instead of the unserialize() method as this provides a uniform data format for all CPU models and promotes better code reuse.

Parameters

cp	The checkpoint use.

Implements gem5::Serializable.

Reimplemented in gem5::CheckerCPU, and gem5::MinorCPU.

Definition at line 725 of file base.cc.

References _pid, _switchedOut, gem5::csprintf(), gem5::ArmISA::i, instCnt, interrupts, numThreads, UNSERIALIZE_SCALAR, and unserializeThread().

Referenced by gem5::MinorCPU::unserialize().

◆ unserializeThread()

virtual void gem5::BaseCPU::unserializeThread	(	CheckpointIn &	cp,
		ThreadID	tid )

inlinevirtual

Unserialize one thread.

Parameters

cp	The checkpoint use.
tid	ID of the current thread.

Reimplemented in gem5::BaseKvmCPU, gem5::BaseSimpleCPU, gem5::MinorCPU, and gem5::o3::CPU.

Definition at line 437 of file base.hh.

Referenced by unserialize().

◆ updateCycleCounters()

void gem5::BaseCPU::updateCycleCounters ( CPUState state )

inlineprotected

base method keeping track of cycle progression

Definition at line 561 of file base.hh.

References CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP, gem5::Clocked::curCycle(), gem5::ProbePointArg< Arg >::notify(), ppActiveCycles, ppAllCycles, ppSleeping, previousCycle, previousState, and state.

Referenced by activateContext(), gem5::TimingSimpleCPU::completeDataAccess(), gem5::TimingSimpleCPU::completeIfetch(), gem5::TimingSimpleCPU::fetch(), haltContext(), gem5::BaseKvmCPU::haltContext(), gem5::BaseSimpleCPU::haltContext(), gem5::o3::CPU::haltContext(), gem5::TimingSimpleCPU::sendFetch(), suspendContext(), gem5::TimingSimpleCPU::switchOut(), gem5::AtomicSimpleCPU::tick(), gem5::MinorCPU::tick(), gem5::o3::CPU::tick(), and gem5::TimingSimpleCPU::translationFault().

◆ verifyMemoryMode()

virtual void gem5::BaseCPU::verifyMemoryMode ( ) const

inlinevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented in gem5::AtomicSimpleCPU, gem5::BaseKvmCPU, gem5::NonCachingSimpleCPU, gem5::o3::CPU, and gem5::TimingSimpleCPU.

Definition at line 384 of file base.hh.

Referenced by init().

◆ wakeup()

virtual void gem5::BaseCPU::wakeup ( ThreadID tid )

pure virtual

Implemented in gem5::BaseKvmCPU, gem5::BaseSimpleCPU, gem5::CheckerCPU, gem5::Iris::BaseCPU, gem5::MinorCPU, and gem5::o3::CPU.

Referenced by gem5::RiscvISA::ISA::globalClearExclusive(), and postInterrupt().

◆ workItemBegin()

void gem5::BaseCPU::workItemBegin ( )

inline

Definition at line 218 of file base.hh.

References baseStats, and gem5::BaseCPU::BaseCPUStats::numWorkItemsStarted.

Referenced by gem5::pseudo_inst::workbegin().

◆ workItemEnd()

void gem5::BaseCPU::workItemEnd ( )

inline

Definition at line 219 of file base.hh.

References baseStats, and gem5::BaseCPU::BaseCPUStats::numWorkItemsCompleted.

Referenced by gem5::pseudo_inst::workend().

Member Data Documentation

◆ _cacheLineSize

const Addr gem5::BaseCPU::_cacheLineSize

protected

Cache the cache line size that we get from the system.

Definition at line 146 of file base.hh.

Referenced by cacheLineSize().

◆ _cpuId

int gem5::BaseCPU::_cpuId

protected

Definition at line 116 of file base.hh.

Referenced by cpuId(), and takeOverFrom().

◆ _dataRequestorId

RequestorID gem5::BaseCPU::_dataRequestorId

protected

data side request id that must be placed in all requests

Definition at line 129 of file base.hh.

Referenced by dataRequestorId(), and gem5::o3::CPU::htmSendAbortSignal().

◆ _instRequestorId

RequestorID gem5::BaseCPU::_instRequestorId

protected

instruction side request id that must be placed in all requests

Definition at line 126 of file base.hh.

Referenced by instRequestorId().

◆ _pid

uint32_t gem5::BaseCPU::_pid

protected

The current OS process ID that is executing on this processor.

This is used to generate a taskId

Definition at line 140 of file base.hh.

Referenced by getPid(), serialize(), setPid(), takeOverFrom(), and unserialize().

◆ _socketId

const uint32_t gem5::BaseCPU::_socketId

protected

Each cpu will have a socket ID that corresponds to its physical location in the system.

This is usually used to bucket cpu cores under single DVFS domain. This information may also be required by the OS to identify the cpu core grouping (as in the case of ARM via MPIDR register)

Definition at line 123 of file base.hh.

Referenced by socketId().

◆ _switchedOut

bool gem5::BaseCPU::_switchedOut

protected

Is the CPU switched out or active?

Definition at line 143 of file base.hh.

Referenced by serialize(), startup(), switchedOut(), switchOut(), takeOverFrom(), and unserialize().

◆ _taskId

uint32_t gem5::BaseCPU::_taskId

protected

An intrenal representation of a task identifier within gem5.

This is used so the CPU can add which taskId (which is an internal representation of the OS process ID) to each request so components in the memory system can track which process IDs are ultimately interacting with them

Definition at line 136 of file base.hh.

Referenced by takeOverFrom(), taskId(), and taskId().

◆ addressMonitor

std::vector<AddressMonitor> gem5::BaseCPU::addressMonitor

private

Definition at line 649 of file base.hh.

Referenced by armMonitor(), getCpuAddrMonitor(), mwait(), and mwaitAtomic().

◆ baseStats

gem5::BaseCPU::BaseCPUStats gem5::BaseCPU::baseStats

Referenced by gem5::AtomicSimpleCPU::activateContext(), gem5::BaseKvmCPU::activateContext(), gem5::BaseSimpleCPU::countCommitInst(), gem5::minor::Execute::doInstCommitAccounting(), gem5::SimpleExecContext::ExecContextStats::ExecContextStats(), gem5::o3::IEW::IEWStats::IEWStats(), gem5::BaseKvmCPU::kvmRun(), gem5::AtomicSimpleCPU::tick(), gem5::o3::CPU::tick(), gem5::o3::Commit::updateComInstStats(), gem5::TimingSimpleCPU::updateCycleCounts(), gem5::o3::CPU::wakeCPU(), workItemBegin(), and workItemEnd().

◆ commitStats

std::vector<std::unique_ptr<CommitCPUStats> > gem5::BaseCPU::commitStats

Definition at line 821 of file base.hh.

Referenced by gem5::o3::Commit::commitInsts(), gem5::BaseSimpleCPU::countCommitInst(), gem5::minor::Execute::doInstCommitAccounting(), gem5::o3::CPU::instDone(), gem5::BaseKvmCPU::kvmRun(), gem5::BaseSimpleCPU::postExecute(), and gem5::o3::Commit::updateComInstStats().

◆ cpuList

std::vector< BaseCPU * > gem5::BaseCPU::cpuList

staticprivate

Static global cpu list.

Definition at line 597 of file base.hh.

Referenced by numSimulatedCPUs(), numSimulatedInsts(), and numSimulatedOps().

◆ currentFunctionEnd

Addr gem5::BaseCPU::currentFunctionEnd

private

Definition at line 591 of file base.hh.

Referenced by traceFunctionsInternal().

◆ currentFunctionStart

Addr gem5::BaseCPU::currentFunctionStart

private

Definition at line 590 of file base.hh.

Referenced by traceFunctionsInternal().

◆ enterPwrGatingEvent

EventFunctionWrapper gem5::BaseCPU::enterPwrGatingEvent

protected

Definition at line 685 of file base.hh.

Referenced by activateContext(), deschedulePowerGatingEvent(), schedulePowerGatingEvent(), and suspendContext().

◆ executeStats

std::vector<std::unique_ptr<ExecuteCPUStats> > gem5::BaseCPU::executeStats

Definition at line 820 of file base.hh.

Referenced by gem5::minor::Execute::commit(), gem5::o3::IEW::dispatchInsts(), gem5::o3::CPU::getReg(), gem5::o3::CPU::getReg(), gem5::o3::CPU::getWritableReg(), gem5::BaseSimpleCPU::postExecute(), gem5::o3::CPU::readMiscReg(), gem5::SimpleExecContext::readMiscReg(), gem5::SimpleExecContext::readMiscRegOperand(), gem5::o3::CPU::setMiscReg(), gem5::SimpleExecContext::setMiscReg(), gem5::SimpleExecContext::setMiscRegOperand(), gem5::o3::CPU::setReg(), gem5::o3::CPU::setReg(), and gem5::o3::IEW::updateExeInstStats().

◆ fetchStats

std::vector<std::unique_ptr<FetchCPUStats> > gem5::BaseCPU::fetchStats

Definition at line 819 of file base.hh.

Referenced by gem5::minor::Execute::commitInst(), gem5::BaseSimpleCPU::countFetchInst(), gem5::o3::Fetch::fetch(), gem5::o3::Fetch::lookupAndUpdateNextPC(), gem5::BaseSimpleCPU::postExecute(), and gem5::o3::Fetch::profileStall().

◆ functionEntryTick

Tick gem5::BaseCPU::functionEntryTick

private

Definition at line 592 of file base.hh.

Referenced by traceFunctionsInternal().

◆ functionTraceStream

std::ostream* gem5::BaseCPU::functionTraceStream

private

Definition at line 589 of file base.hh.

Referenced by traceFunctionsInternal().

◆ functionTracingEnabled

bool gem5::BaseCPU::functionTracingEnabled

private

Definition at line 588 of file base.hh.

Referenced by enableFunctionTrace(), and traceFunctions().

◆ globalStats

std::unique_ptr< BaseCPU::GlobalStats > gem5::BaseCPU::globalStats

staticprotected

Pointer to the global stat structure.

This needs to be constructed from regStats since we merge it into the root group.

Definition at line 164 of file base.hh.

Referenced by regStats().

◆ instCnt

Tick gem5::BaseCPU::instCnt

protected

Instruction count used for SPARC misc register.

Todo: unify this with the counters that cpus individually keep

Definition at line 110 of file base.hh.

Referenced by gem5::TimingSimpleCPU::completeIfetch(), instCount(), serialize(), gem5::AtomicSimpleCPU::tick(), and unserialize().

◆ interrupts

std::vector<BaseInterrupts*> gem5::BaseCPU::interrupts

protected

Definition at line 224 of file base.hh.

Referenced by gem5::BaseSimpleCPU::checkForInterrupts(), checkInterrupts(), clearInterrupt(), clearInterrupts(), gem5::X86KvmCPU::deliverInterrupts(), getInterruptController(), gem5::o3::CPU::getInterrupts(), gem5::ArmKvmCPU::kvmRun(), gem5::BaseArmKvmCPU::kvmRun(), gem5::X86KvmCPU::kvmRun(), postInterrupt(), gem5::o3::CPU::processInterrupts(), registerThreadContexts(), serialize(), setReset(), takeOverFrom(), and unserialize().

◆ invldPid

const uint32_t gem5::BaseCPU::invldPid = std::numeric_limits<uint32_t>::max()

static

Invalid or unknown Pid.

Possible when operating system is not present or has not assigned a pid yet

Definition at line 269 of file base.hh.

Referenced by gem5::ArmISA::FsLinux::startup().

◆ modelResetPort

SignalSinkPort<bool> gem5::BaseCPU::modelResetPort

protected

Definition at line 166 of file base.hh.

Referenced by activateContext(), getPort(), and takeOverFrom().

◆ numThreads

ThreadID gem5::BaseCPU::numThreads

Number of threads we're actually simulating (<= SMT_MAX_THREADS).

This is a constant for the duration of the simulation.

Definition at line 390 of file base.hh.

Referenced by gem5::AtomicSimpleCPU::activateContext(), gem5::TimingSimpleCPU::activateContext(), armMonitor(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::minor::Execute::checkInterrupts(), gem5::o3::Commit::CommitStats::CommitStats(), gem5::minor::Execute::drain(), gem5::AtomicSimpleCPU::drainResume(), gem5::minor::Execute::drainResume(), gem5::minor::Pipeline::drainResume(), gem5::MinorCPU::drainResume(), gem5::TimingSimpleCPU::drainResume(), gem5::minor::Decode::evaluate(), gem5::minor::Execute::evaluate(), gem5::minor::Fetch1::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::o3::IEW::IEWStats::ExecutedInstStats::ExecutedInstStats(), getCpuAddrMonitor(), gem5::o3::CPU::getFreeTid(), gem5::o3::IEW::IEWStats::IEWStats(), init(), gem5::BaseKvmCPU::init(), gem5::o3::CPU::init(), gem5::o3::InstructionQueue::IQStats::IQStats(), gem5::minor::Execute::isDrained(), gem5::minor::Fetch1::isDrained(), gem5::MinorCPU::MinorCPU(), mwait(), mwaitAtomic(), gem5::MinorCPU::randomPriority(), gem5::AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), gem5::TimingSimpleCPU::DcachePort::recvFunctionalSnoop(), gem5::minor::LSQ::recvTimingSnoopReq(), gem5::o3::LSQ::DcachePort::recvTimingSnoopReq(), gem5::TimingSimpleCPU::DcachePort::recvTimingSnoopReq(), registerThreadContexts(), gem5::MinorCPU::roundRobinPriority(), scheduleInstStopAnyThread(), serialize(), gem5::MinorCPU::startup(), gem5::AtomicSimpleCPU::suspendContext(), gem5::TimingSimpleCPU::suspendContext(), gem5::BaseSimpleCPU::swapActiveThread(), takeOverFrom(), gem5::AtomicSimpleCPU::threadSnoop(), gem5::minor::LSQ::threadSnoop(), gem5::TimingSimpleCPU::threadSnoop(), gem5::AtomicSimpleCPU::tick(), unserialize(), gem5::MinorCPU::wakeup(), and gem5::minor::Execute::~Execute().

◆ powerGatingOnIdle

const bool gem5::BaseCPU::powerGatingOnIdle

protected

Definition at line 684 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ ppActiveCycles

probing::PMUUPtr gem5::BaseCPU::ppActiveCycles

protected

CPU cycle counter, only counts if any thread contexts is active.

Definition at line 536 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ ppAllCycles

probing::PMUUPtr gem5::BaseCPU::ppAllCycles

protected

CPU cycle counter even if any thread Context is suspended.

Definition at line 533 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ ppRetiredBranches

probing::PMUUPtr gem5::BaseCPU::ppRetiredBranches

protected

Retired branches (any type)

Definition at line 530 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInsts

probing::PMUUPtr gem5::BaseCPU::ppRetiredInsts

protected

Instruction commit probe point.

This probe point is triggered whenever one or more instructions are committed. It is normally triggered once for every instruction. However, CPU models committing bundles of instructions may call notify once for the entire bundle.

Definition at line 521 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredInstsPC

probing::PMUUPtr gem5::BaseCPU::ppRetiredInstsPC

protected

Definition at line 522 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredLoads

probing::PMUUPtr gem5::BaseCPU::ppRetiredLoads

protected

Retired load instructions.

Definition at line 525 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppRetiredStores

probing::PMUUPtr gem5::BaseCPU::ppRetiredStores

protected

Retired store instructions.

Definition at line 527 of file base.hh.

Referenced by probeInstCommit(), and regProbePoints().

◆ ppSleeping

ProbePointArg<bool>* gem5::BaseCPU::ppSleeping

protected

ProbePoint that signals transitions of threadContexts sets.

The ProbePoint reports information through it bool parameter.

If the parameter is true then the last enabled threadContext of the CPU object was disabled.
If the parameter is false then a threadContext was enabled, all the remaining threadContexts are disabled.

Definition at line 546 of file base.hh.

Referenced by regProbePoints(), and updateCycleCounters().

◆ previousCycle

Cycles gem5::BaseCPU::previousCycle

protected

Definition at line 556 of file base.hh.

Referenced by takeOverFrom(), and updateCycleCounters().

◆ previousState

CPUState gem5::BaseCPU::previousState

protected

Definition at line 557 of file base.hh.

Referenced by takeOverFrom(), and updateCycleCounters().

◆ pwrGatingLatency

const Cycles gem5::BaseCPU::pwrGatingLatency

protected

Definition at line 683 of file base.hh.

Referenced by schedulePowerGatingEvent(), and suspendContext().

◆ syscallRetryLatency

Cycles gem5::BaseCPU::syscallRetryLatency

Definition at line 662 of file base.hh.

Referenced by gem5::TimingSimpleCPU::advanceInst(), gem5::o3::Commit::generateTrapEvent(), and gem5::AtomicSimpleCPU::tick().

◆ system

System* gem5::BaseCPU::system

Definition at line 392 of file base.hh.

Referenced by gem5::MinorCPU::drainResume(), gem5::Iris::ThreadContext::getSystemPtr(), gem5::BaseKvmCPU::init(), gem5::MinorCPU::init(), gem5::pseudo_inst::initParam(), gem5::pseudo_inst::loadsymbol(), postInterrupt(), registerThreadContexts(), gem5::CheckerCPU::setSystem(), takeOverFrom(), and gem5::BaseKvmCPU::verifyMemoryMode().

◆ threadContexts

std::vector<ThreadContext *> gem5::BaseCPU::threadContexts

protected

Definition at line 260 of file base.hh.

Referenced by activateContext(), gem5::BaseSimpleCPU::advancePC(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::BaseSimpleCPU::checkPcEventQueue(), contextToThread(), gem5::Iris::CPU< TC >::CPU(), gem5::o3::CPU::drain(), gem5::AtomicSimpleCPU::drainResume(), gem5::TimingSimpleCPU::drainResume(), findContext(), flushTLBs(), getContext(), getCurrentInstCount(), gem5::AtomicSimpleCPU::init(), init(), gem5::fastmodel::CortexA76::initState(), gem5::MinorCPU::MinorCPU(), numContexts(), gem5::BaseSimpleCPU::postExecute(), postInterrupt(), registerThreadContexts(), regStats(), scheduleInstStop(), schedulePowerGatingEvent(), gem5::Iris::BaseCPU::serializeThread(), setReset(), gem5::CheckerCPU::setSystem(), suspendContext(), takeOverFrom(), gem5::BaseKvmCPU::takeOverFrom(), gem5::AtomicSimpleCPU::tick(), gem5::Iris::BaseCPU::totalInsts(), gem5::o3::CPU::trap(), gem5::Iris::BaseCPU::wakeup(), gem5::o3::CPU::wakeup(), and gem5::Iris::BaseCPU::~BaseCPU().

◆ tracer

trace::InstTracer* gem5::BaseCPU::tracer

protected

Definition at line 262 of file base.hh.

Referenced by getTracer(), and gem5::BaseSimpleCPU::preExecute().

The documentation for this class was generated from the following files:

cpu/base.hh
cpu/base.cc

Classes

Public Member Functions

Static Public Member Functions

Public Attributes

Static Public Attributes

Protected Types

Protected Member Functions

Protected Attributes

Static Protected Attributes

Private Member Functions

Private Attributes

Static Private Attributes

PMU Probe points.

Additional Inherited Members

Detailed Description

Member Enumeration Documentation

◆ CPUState

Constructor & Destructor Documentation

◆ BaseCPU()

◆ ~BaseCPU()

Member Function Documentation

◆ activateContext()

◆ armMonitor()

◆ cacheLineSize()

◆ checkInterrupts()

◆ clearInterrupt()

◆ clearInterrupts()

◆ contextToThread()

◆ cpuId()

◆ dataRequestorId()

◆ deschedulePowerGatingEvent()

◆ enableFunctionTrace()

◆ enterPwrGating()

◆ findContext()

◆ flushTLBs()

◆ getContext()

◆ getCpuAddrMonitor()

◆ getCurrentInstCount()

◆ getDataPort()

◆ getInstPort()

◆ getInterruptController()

◆ getPid()

◆ getPort()

◆ getTracer()

◆ haltContext()

◆ htmSendAbortSignal()

◆ init()

◆ instCount()

◆ instRequestorId()

◆ mwait()

◆ mwaitAtomic()

◆ numContexts()

◆ numSimulatedCPUs()

◆ numSimulatedInsts()

◆ numSimulatedOps()

◆ PARAMS()

◆ pmuProbePoint()

◆ postInterrupt()

◆ probeInstCommit()

◆ registerThreadContexts()

◆ regProbePoints()

◆ regStats()

◆ scheduleInstStop()

◆ scheduleInstStopAnyThread()

◆ schedulePowerGatingEvent()

◆ scheduleSimpointsInstStop()

◆ serialize()

◆ serializeThread()

◆ setPid()

◆ setReset()

◆ socketId()

◆ startup()

◆ suspendContext()

◆ switchedOut()

◆ switchOut()

◆ takeOverFrom()

◆ taskId() [1/2]

◆ taskId() [2/2]

◆ totalInsts()

◆ totalOps()