gem5::TraceCPU::IcachePort Class Reference

IcachePort class that interfaces with L1 Instruction Cache. More...

#include <trace_cpu.hh>

Inheritance diagram for gem5::TraceCPU::IcachePort:

Public Member Functions
	IcachePort (TraceCPU *_cpu)
	Default constructor.
bool	recvTimingResp (PacketPtr pkt)
	Receive the timing reponse and simply delete the packet since instruction fetch requests are issued as per the timing in the trace and responses are ignored.
void	recvTimingSnoopReq (PacketPtr pkt)
	Required functionally but do nothing.
void	recvReqRetry ()
	Handle a retry signalled by the cache if instruction read failed in the first attempt.
Public Member Functions inherited from gem5::RequestPort
	RequestPort (const std::string &name, SimObject *_owner, PortID id=InvalidPortID)
	Request port.
	RequestPort (const std::string &name, PortID id=InvalidPortID)
virtual	~RequestPort ()
void	bind (Port &peer) override
	Bind this request port to a response port.
void	unbind () override
	Unbind this request port and the associated response port.
virtual bool	isSnooping () const
	Determine if this request port is snooping or not.
AddrRangeList	getAddrRanges () const
	Get the address ranges of the connected responder port.
void	printAddr (Addr a)
	Inject a PrintReq for the given address to print the state of that address throughout the memory system.
Tick	sendAtomic (PacketPtr pkt)
	Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses.
Tick	sendAtomicBackdoor (PacketPtr pkt, MemBackdoorPtr &backdoor)
	Send an atomic request packet like above, but also request a backdoor to the data being accessed.
void	sendFunctional (PacketPtr pkt) const
	Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block.
void	sendMemBackdoorReq (const MemBackdoorReq &req, MemBackdoorPtr &backdoor)
	Send a request for a back door to a range of memory.
bool	sendTimingReq (PacketPtr pkt)
	Attempt to send a timing request to the responder port by calling its corresponding receive function.
bool	tryTiming (PacketPtr pkt) const
	Check if the responder can handle a timing request.
bool	sendTimingSnoopResp (PacketPtr pkt)
	Attempt to send a timing snoop response packet to the response port by calling its corresponding receive function.
virtual void	sendRetryResp ()
	Send a retry to the response port that previously attempted a sendTimingResp to this request port and failed.
Public Member Functions inherited from gem5::Port
virtual	~Port ()
	Virtual destructor due to inheritance.
Port &	getPeer ()
	Return a reference to this port's peer.
const std::string	name () const
	Return port name (for DPRINTF).
PortID	getId () const
	Get the port id.
bool	isConnected () const
	Is this port currently connected to a peer?
void	takeOverFrom (Port *old)
	A utility function to make it easier to swap out ports.

Private Attributes
TraceCPU *	owner

Additional Inherited Members
Protected Member Functions inherited from gem5::RequestPort
virtual void	recvRangeChange ()
	Called to receive an address range change from the peer response port.
Tick	recvAtomicSnoop (PacketPtr pkt) override
	Default implementations.
void	recvFunctionalSnoop (PacketPtr pkt) override
	Receive a functional snoop request packet from the peer.
void	recvTimingSnoopReq (PacketPtr pkt) override
	Receive a timing snoop request from the peer.
void	recvRetrySnoopResp () override
	Called by the peer if sendTimingSnoopResp was called on this protocol (causing recvTimingSnoopResp to be called on the peer) and was unsuccessful.
Protected Member Functions inherited from gem5::Port
void	reportUnbound () const
	Port (const std::string &_name, PortID _id)
	Abstract base class for ports.
Protected Member Functions inherited from gem5::AtomicRequestProtocol
Tick	send (AtomicResponseProtocol *peer, PacketPtr pkt)
	Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses.
Tick	sendBackdoor (AtomicResponseProtocol *peer, PacketPtr pkt, MemBackdoorPtr &backdoor)
	Send an atomic request packet like above, but also request a backdoor to the data being accessed.
Protected Member Functions inherited from gem5::TimingRequestProtocol
bool	sendReq (TimingResponseProtocol *peer, PacketPtr pkt)
	Attempt to send a timing request to the peer by calling its corresponding receive function.
bool	trySend (TimingResponseProtocol *peer, PacketPtr pkt) const
	Check if the peer can handle a timing request.
bool	sendSnoopResp (TimingResponseProtocol *peer, PacketPtr pkt)
	Attempt to send a timing snoop response packet to it's peer by calling its corresponding receive function.
void	sendRetryResp (TimingResponseProtocol *peer)
	Send a retry to the peer that previously attempted a sendTimingResp to this protocol and failed.
Protected Member Functions inherited from gem5::FunctionalRequestProtocol
void	send (FunctionalResponseProtocol *peer, PacketPtr pkt) const
	Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block.
void	sendMemBackdoorReq (FunctionalResponseProtocol *peer, const MemBackdoorReq &req, MemBackdoorPtr &backdoor)
	Send a request for a back door to a range of memory.
Protected Attributes inherited from gem5::RequestPort
SimObject &	owner
Protected Attributes inherited from gem5::Port
const PortID	id
	A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector.
Port *	_peer
	A pointer to this port's peer.
bool	_connected
	Whether this port is currently connected to a peer port.

Detailed Description

IcachePort class that interfaces with L1 Instruction Cache.

Definition at line 198 of file trace_cpu.hh.

Constructor & Destructor Documentation

IcachePort()

gem5::TraceCPU::IcachePort::IcachePort ( TraceCPU * _cpu )

inline

Default constructor.

Definition at line 202 of file trace_cpu.hh.

Member Function Documentation

recvReqRetry()

void gem5::TraceCPU::IcachePort::recvReqRetry ( )

virtual

Handle a retry signalled by the cache if instruction read failed in the first attempt.

Implements gem5::TimingRequestProtocol.

Definition at line 1174 of file trace_cpu.cc.

References gem5::TraceCPU::icacheRetryRecvd(), and gem5::TraceCPU::FixedRetryGen::owner.

recvTimingResp()

bool gem5::TraceCPU::IcachePort::recvTimingResp ( PacketPtr pkt )

virtual

Receive the timing reponse and simply delete the packet since instruction fetch requests are issued as per the timing in the trace and responses are ignored.

Parameters

pkt	Pointer to packet received

Returns

true

Implements gem5::TimingRequestProtocol.

Definition at line 1164 of file trace_cpu.cc.

recvTimingSnoopReq()

void gem5::TraceCPU::IcachePort::recvTimingSnoopReq ( PacketPtr pkt )

inlinevirtual

Required functionally but do nothing.

Parameters

pkt	Pointer to packet received

Implements gem5::TimingRequestProtocol.

Definition at line 222 of file trace_cpu.hh.

Member Data Documentation

owner

TraceCPU* gem5::TraceCPU::IcachePort::owner

private

Definition at line 231 of file trace_cpu.hh.

---

The documentation for this class was generated from the following files:

• cpu/trace/trace_cpu.hh
• cpu/trace/trace_cpu.cc