gem5  v21.2.0.0
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gem5::TraceCPU Class Reference

The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model. More...

#include <trace_cpu.hh>

Inheritance diagram for gem5::TraceCPU:

Classes

class  DcachePort
 DcachePort class that interfaces with L1 Data Cache. More...
 
class  ElasticDataGen
 The elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies. More...
 
class  FixedRetryGen
 Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests. More...
 
class  IcachePort
 IcachePort class that interfaces with L1 Instruction Cache. More...
 
struct  TraceStats
 

Public Member Functions

 TraceCPU (const TraceCPUParams &params)
 
void init ()
 
Counter totalInsts () const
 This is a pure virtual function in BaseCPU. More...
 
Counter totalOps () const
 Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are modelled in the TraceCPU replay. More...
 
void updateNumOps (uint64_t rob_num)
 
void wakeup (ThreadID tid=0)
 
void takeOverFrom (BaseCPU *oldCPU)
 
void icacheRetryRecvd ()
 When instruction cache port receives a retry, schedule event icacheNextEvent. More...
 
void dcacheRetryRecvd ()
 When data cache port receives a retry, schedule event dcacheNextEvent. More...
 
void dcacheRecvTimingResp (PacketPtr pkt)
 When data cache port receives a response, this calls the dcache generator method handle to complete the load writeback. More...
 
void schedDcacheNextEvent (Tick when)
 Schedule event dcacheNextEvent at the given tick. More...
 
PortgetInstPort ()
 Used to get a reference to the icache port. More...
 
PortgetDataPort ()
 Used to get a reference to the dcache port. More...
 

Protected Member Functions

void schedIcacheNext ()
 This is the control flow that uses the functionality of the icacheGen to replay the trace. More...
 
void schedDcacheNext ()
 This is the control flow that uses the functionality of the dcacheGen to replay the trace. More...
 
void checkAndSchedExitEvent ()
 This is called when either generator finishes executing from the trace. More...
 

Protected Attributes

IcachePort icachePort
 Port to connect to L1 instruction cache. More...
 
DcachePort dcachePort
 Port to connect to L1 data cache. More...
 
const RequestorID instRequestorID
 Requestor id for instruction read requests. More...
 
const RequestorID dataRequestorID
 Requestor id for data read and write requests. More...
 
std::string instTraceFile
 File names for input instruction and data traces. More...
 
std::string dataTraceFile
 
FixedRetryGen icacheGen
 Instance of FixedRetryGen to replay instruction read requests. More...
 
ElasticDataGen dcacheGen
 Instance of ElasticDataGen to replay data read and write requests. More...
 
EventFunctionWrapper icacheNextEvent
 Event for the control flow method schedIcacheNext() More...
 
EventFunctionWrapper dcacheNextEvent
 Event for the control flow method schedDcacheNext() More...
 
bool oneTraceComplete
 Set to true when one of the generators finishes replaying its trace. More...
 
Tick traceOffset
 This stores the time offset in the trace, which is taken away from the ready times of requests. More...
 
CountedExitEventexecCompleteEvent
 A CountedExitEvent which when serviced decrements the counter. More...
 
const bool enableEarlyExit
 Exit when any one Trace CPU completes its execution. More...
 
const uint64_t progressMsgInterval
 Interval of committed instructions specified by the user at which a progress info message is printed. More...
 
uint64_t progressMsgThreshold
 
gem5::TraceCPU::TraceStats traceStats
 

Static Protected Attributes

static int numTraceCPUs = 0
 Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event used for counting down exit events. More...
 

Detailed Description

The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model.

The elastic trace is an execution trace with register data dependencies and ordering dependencies annotated to it. The trace cpu also replays a fixed timestamp fetch trace that is also generated by the elastic trace probe. This trace cpu model aims at achieving faster simulation compared to the detailed cpu model and good correlation when the same trace is used for playback on different memory sub-systems.

The TraceCPU inherits from BaseCPU so some virtual methods need to be defined. It has two port subclasses inherited from RequestPort for instruction and data ports. It issues the memory requests deducing the timing from the trace and without performing real execution of micro-ops. As soon as the last dependency for an instruction is complete, its computational delay, also provided in the input trace is added. The dependency-free nodes are maintained in a list, called 'ReadyList', ordered by ready time. Instructions which depend on load stall until the responses for read requests are received thus achieving elastic replay. If the dependency is not found when adding a new node, it is assumed complete. Thus, if this node is found to be completely dependency-free its issue time is calculated and it is added to the ready list immediately. This is encapsulated in the subclass ElasticDataGen.

If ready nodes are issued in an unconstrained way there can be more nodes outstanding which results in divergence in timing compared to the O3CPU. Therefore, the Trace CPU also models hardware resources. A sub-class to model hardware resources contains the maximum sizes of load buffer, store buffer and ROB. If resources are not available, the node is not issued. Such nodes that are pending issue are held in the 'depFreeQueue' structure.

Modeling the ROB size in the Trace CPU as a resource limitation is arguably the most important parameter of all resources. The ROB occupancy is estimated using the newly added field 'robNum'. We need to use ROB number as sequence number is at times much higher due to squashing and trace replay is focused on correct path modeling.

A map called 'inFlightNodes' is added to track nodes that are not only in the readyList but also load nodes that are executed (and thus removed from readyList) but are not complete. ReadyList handles what and when to execute next node while the inFlightNodes is used for resource modelling. The oldest ROB number is updated when any node occupies the ROB or when an entry in the ROB is released. The ROB occupancy is equal to the difference in the ROB number of the newly dependency-free node and the oldest ROB number in flight.

If no node depends on a non load/store node then there is no reason to track it in the dependency graph. We filter out such nodes but count them and add a weight field to the subsequent node that we do include in the trace. The weight field is used to model ROB occupancy during replay.

The depFreeQueue is chosen to be FIFO so that child nodes which are in program order get pushed into it in that order and thus issued in program order, like in the O3CPU. This is also why the dependents is made a sequential container, std::set to std::vector. We only check head of the depFreeQueue as nodes are issued in order and blocking on head models that better than looping the entire queue. An alternative choice would be to inspect top N pending nodes where N is the issue-width. This is left for future as the timing correlation looks good as it is.

At the start of an execution event, first we attempt to issue such pending nodes by checking if appropriate resources have become available. If yes, we compute the execute tick with respect to the time then. Then we proceed to complete nodes from the readyList.

When a read response is received, sometimes a dependency on it that was supposed to be released when it was issued is still not released. This occurs because the dependent gets added to the graph after the read was sent. So the check is made less strict and the dependency is marked complete on read response instead of insisting that it should have been removed on read sent.

There is a check for requests spanning two cache lines as this condition triggers an assert fail in the L1 cache. If it does then truncate the size to access only until the end of that line and ignore the remainder. Strictly-ordered requests are skipped and the dependencies on such requests are handled by simply marking them complete immediately.

A CountedExitEvent that contains a static int belonging to the Trace CPU class as a down counter is used to implement multi Trace CPU simulation exit.

Definition at line 142 of file trace_cpu.hh.

Constructor & Destructor Documentation

◆ TraceCPU()

gem5::TraceCPU::TraceCPU ( const TraceCPUParams &  params)

Definition at line 49 of file trace_cpu.cc.

References schedIcacheNext().

Member Function Documentation

◆ checkAndSchedExitEvent()

void gem5::TraceCPU::checkAndSchedExitEvent ( )
protected

This is called when either generator finishes executing from the trace.

Definition at line 188 of file trace_cpu.cc.

References gem5::curTick(), enableEarlyExit, execCompleteEvent, gem5::exitSimLoop(), inform, name(), and oneTraceComplete.

Referenced by schedDcacheNext(), and schedIcacheNext().

◆ dcacheRecvTimingResp()

void gem5::TraceCPU::dcacheRecvTimingResp ( PacketPtr  pkt)

When data cache port receives a response, this calls the dcache generator method handle to complete the load writeback.

Parameters
pktPointer to packet received

Definition at line 1172 of file trace_cpu.cc.

References gem5::TraceCPU::ElasticDataGen::completeMemAccess(), dcacheGen, and DPRINTF.

Referenced by gem5::TraceCPU::DcachePort::recvTimingResp().

◆ dcacheRetryRecvd()

void gem5::TraceCPU::dcacheRetryRecvd ( )

When data cache port receives a retry, schedule event dcacheNextEvent.

Definition at line 1130 of file trace_cpu.cc.

References gem5::curTick(), dcacheNextEvent, and DPRINTF.

Referenced by gem5::TraceCPU::DcachePort::recvReqRetry().

◆ getDataPort()

Port& gem5::TraceCPU::getDataPort ( )
inline

Used to get a reference to the dcache port.

Definition at line 1126 of file trace_cpu.hh.

References dcachePort.

Referenced by takeOverFrom().

◆ getInstPort()

Port& gem5::TraceCPU::getInstPort ( )
inline

Used to get a reference to the icache port.

Definition at line 1123 of file trace_cpu.hh.

References icachePort.

Referenced by takeOverFrom().

◆ icacheRetryRecvd()

void gem5::TraceCPU::icacheRetryRecvd ( )

When instruction cache port receives a retry, schedule event icacheNextEvent.

Definition at line 1120 of file trace_cpu.cc.

References gem5::curTick(), DPRINTF, and icacheNextEvent.

Referenced by gem5::TraceCPU::IcachePort::recvReqRetry().

◆ init()

void gem5::TraceCPU::init ( )

◆ schedDcacheNext()

void gem5::TraceCPU::schedDcacheNext ( )
protected

This is the control flow that uses the functionality of the dcacheGen to replay the trace.

It calls execute(). It checks if execution is complete and schedules an event to exit simulation accordingly.

Definition at line 174 of file trace_cpu.cc.

References checkAndSchedExitEvent(), dcacheGen, DPRINTF, gem5::TraceCPU::ElasticDataGen::execute(), and gem5::TraceCPU::ElasticDataGen::isExecComplete().

◆ schedDcacheNextEvent()

void gem5::TraceCPU::schedDcacheNextEvent ( Tick  when)

Schedule event dcacheNextEvent at the given tick.

Parameters
whenTick at which to schedule event

Definition at line 1140 of file trace_cpu.cc.

References dcacheNextEvent, DPRINTF, gem5::TraceCPU::TraceStats::numSchedDcacheEvent, gem5::Event::scheduled(), traceStats, and gem5::Event::when().

Referenced by gem5::TraceCPU::ElasticDataGen::completeMemAccess(), and gem5::TraceCPU::ElasticDataGen::execute().

◆ schedIcacheNext()

void gem5::TraceCPU::schedIcacheNext ( )
protected

This is the control flow that uses the functionality of the icacheGen to replay the trace.

It calls tryNext(). If it returns true then next event is scheduled at curTick() plus delta. If it returns false then delta is ignored and control is brought back via recvRetry().

Definition at line 148 of file trace_cpu.cc.

References checkAndSchedExitEvent(), gem5::curTick(), DPRINTF, icacheGen, icacheNextEvent, gem5::TraceCPU::FixedRetryGen::isTraceComplete(), gem5::TraceCPU::TraceStats::numSchedIcacheEvent, gem5::TraceCPU::FixedRetryGen::tickDelta(), traceStats, and gem5::TraceCPU::FixedRetryGen::tryNext().

Referenced by TraceCPU().

◆ takeOverFrom()

void gem5::TraceCPU::takeOverFrom ( BaseCPU *  oldCPU)

Definition at line 97 of file trace_cpu.cc.

References getDataPort(), getInstPort(), and gem5::Port::takeOverFrom().

◆ totalInsts()

Counter gem5::TraceCPU::totalInsts ( ) const
inline

This is a pure virtual function in BaseCPU.

As we don't know how many insts are in the trace but only know how how many micro-ops are we cannot count this stat.

Returns
0

Definition at line 157 of file trace_cpu.hh.

◆ totalOps()

Counter gem5::TraceCPU::totalOps ( ) const
inline

Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are modelled in the TraceCPU replay.

Returns
number of micro-ops i.e. nodes in the elastic data generator

Definition at line 165 of file trace_cpu.hh.

References gem5::TraceCPU::TraceStats::numOps, traceStats, and gem5::statistics::ScalarBase< Derived, Stor >::value().

◆ updateNumOps()

void gem5::TraceCPU::updateNumOps ( uint64_t  rob_num)

◆ wakeup()

void gem5::TraceCPU::wakeup ( ThreadID  tid = 0)
inline

Definition at line 174 of file trace_cpu.hh.

Member Data Documentation

◆ dataRequestorID

const RequestorID gem5::TraceCPU::dataRequestorID
protected

Requestor id for data read and write requests.

Definition at line 316 of file trace_cpu.hh.

◆ dataTraceFile

std::string gem5::TraceCPU::dataTraceFile
protected

Definition at line 319 of file trace_cpu.hh.

Referenced by init().

◆ dcacheGen

ElasticDataGen gem5::TraceCPU::dcacheGen
protected

Instance of ElasticDataGen to replay data read and write requests.

Definition at line 1034 of file trace_cpu.hh.

Referenced by dcacheRecvTimingResp(), init(), and schedDcacheNext().

◆ dcacheNextEvent

EventFunctionWrapper gem5::TraceCPU::dcacheNextEvent
protected

Event for the control flow method schedDcacheNext()

Definition at line 1055 of file trace_cpu.hh.

Referenced by dcacheRetryRecvd(), init(), and schedDcacheNextEvent().

◆ dcachePort

DcachePort gem5::TraceCPU::dcachePort
protected

Port to connect to L1 data cache.

Definition at line 310 of file trace_cpu.hh.

Referenced by getDataPort().

◆ enableEarlyExit

const bool gem5::TraceCPU::enableEarlyExit
protected

Exit when any one Trace CPU completes its execution.

If this is configured true then the execCompleteEvent is not scheduled.

Definition at line 1093 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent(), and init().

◆ execCompleteEvent

CountedExitEvent* gem5::TraceCPU::execCompleteEvent
protected

A CountedExitEvent which when serviced decrements the counter.

A sim exit event is scheduled when the counter equals zero, that is all instances of Trace CPU have had their execCompleteEvent serviced.

Definition at line 1087 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent(), and init().

◆ icacheGen

FixedRetryGen gem5::TraceCPU::icacheGen
protected

Instance of FixedRetryGen to replay instruction read requests.

Definition at line 1031 of file trace_cpu.hh.

Referenced by init(), and schedIcacheNext().

◆ icacheNextEvent

EventFunctionWrapper gem5::TraceCPU::icacheNextEvent
protected

Event for the control flow method schedIcacheNext()

Definition at line 1052 of file trace_cpu.hh.

Referenced by icacheRetryRecvd(), init(), and schedIcacheNext().

◆ icachePort

IcachePort gem5::TraceCPU::icachePort
protected

Port to connect to L1 instruction cache.

Definition at line 307 of file trace_cpu.hh.

Referenced by getInstPort().

◆ instRequestorID

const RequestorID gem5::TraceCPU::instRequestorID
protected

Requestor id for instruction read requests.

Definition at line 313 of file trace_cpu.hh.

◆ instTraceFile

std::string gem5::TraceCPU::instTraceFile
protected

File names for input instruction and data traces.

Definition at line 319 of file trace_cpu.hh.

Referenced by init().

◆ numTraceCPUs

int gem5::TraceCPU::numTraceCPUs = 0
staticprotected

Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event used for counting down exit events.

It is incremented in the constructor call so that the total is arrived at automatically.

Definition at line 1080 of file trace_cpu.hh.

Referenced by init().

◆ oneTraceComplete

bool gem5::TraceCPU::oneTraceComplete
protected

Set to true when one of the generators finishes replaying its trace.

Definition at line 1064 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent().

◆ progressMsgInterval

const uint64_t gem5::TraceCPU::progressMsgInterval
protected

Interval of committed instructions specified by the user at which a progress info message is printed.

Definition at line 1099 of file trace_cpu.hh.

Referenced by updateNumOps().

◆ progressMsgThreshold

uint64_t gem5::TraceCPU::progressMsgThreshold
protected

Definition at line 1106 of file trace_cpu.hh.

Referenced by updateNumOps().

◆ traceOffset

Tick gem5::TraceCPU::traceOffset
protected

This stores the time offset in the trace, which is taken away from the ready times of requests.

This is specially useful because the time offset can be very large if the traces are generated from the middle of a program.

Definition at line 1072 of file trace_cpu.hh.

Referenced by init().

◆ traceStats

gem5::TraceCPU::TraceStats gem5::TraceCPU::traceStats
protected

The documentation for this class was generated from the following files:

Generated on Tue Dec 21 2021 11:35:15 for gem5 by doxygen 1.8.17