The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model. More...

#include <trace_cpu.hh>

Inheritance diagram for gem5::TraceCPU:

Classes
class	DcachePort
	DcachePort class that interfaces with L1 Data Cache. More...

class	ElasticDataGen
	The elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies. More...

class	FixedRetryGen
	Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests. More...

class	IcachePort
	IcachePort class that interfaces with L1 Instruction Cache. More...

struct	TraceStats

Public Member Functions
	TraceCPU (const TraceCPUParams &params)

void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

Counter	totalInsts () const
	This is a pure virtual function in BaseCPU. More...

Counter	totalOps () const
	Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are modelled in the TraceCPU replay. More...

void	updateNumOps (uint64_t rob_num)

void	wakeup (ThreadID tid=0)

void	takeOverFrom (BaseCPU *oldCPU)
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	icacheRetryRecvd ()
	When instruction cache port receives a retry, schedule event icacheNextEvent. More...

void	dcacheRetryRecvd ()
	When data cache port receives a retry, schedule event dcacheNextEvent. More...

void	dcacheRecvTimingResp (PacketPtr pkt)
	When data cache port receives a response, this calls the dcache generator method handle to complete the load writeback. More...

void	schedDcacheNextEvent (Tick when)
	Schedule event dcacheNextEvent at the given tick. More...

Port &	getInstPort ()
	Used to get a reference to the icache port. More...

Port &	getDataPort ()
	Used to get a reference to the dcache port. More...

Public Member Functions inherited from gem5::BaseCPU
int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

RequestorID	dataRequestorId () const
	Reads this CPU's unique data requestor ID. More...

RequestorID	instRequestorId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadID tid) const

trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

virtual void	activateContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now active. More...

virtual void	suspendContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now suspended. More...

virtual void	haltContext (ThreadID thread_num)
	Notify the CPU that the indicated context is now halted. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

	PARAMS (BaseCPU)

	BaseCPU (const Params &params, bool is_checker=false)

virtual	~BaseCPU ()

void	startup () override
	startup() is the final initialization call before simulation. More...

void	regStats () override
	Callback to set stat parameters. More...

void	regProbePoints () override
	Register probe points for this object. More...

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

virtual void	switchOut ()
	Prepare for another CPU to take over execution. More...

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

virtual void	verifyMemoryMode () const
	Verify that the system is in a memory mode supported by the CPU. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

virtual void	serializeThread (CheckpointOut &cp, ThreadID tid) const
	Serialize a single thread. More...

virtual void	unserializeThread (CheckpointIn &cp, ThreadID tid)
	Unserialize one thread. More...

void	scheduleInstStop (ThreadID tid, Counter insts, std::string cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

void	scheduleSimpointsInstStop (std::vector< Counter > inst_starts)
	Schedule simpoint events using the scheduleInstStop function. More...

void	scheduleInstStopAnyThread (Counter max_insts)
	Schedule an exit event when any threads in the core reach the max_insts instructions using the scheduleInstStop function. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseMMU mmu)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

virtual void	htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
	This function is used to instruct the memory subsystem that a transaction should be aborted and the speculative state should be thrown away. More...

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
void	schedIcacheNext ()
	This is the control flow that uses the functionality of the icacheGen to replay the trace. More...

void	schedDcacheNext ()
	This is the control flow that uses the functionality of the dcacheGen to replay the trace. More...

void	checkAndSchedExitEvent ()
	This is called when either generator finishes executing from the trace. More...

Protected Member Functions inherited from gem5::BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

probing::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes
IcachePort	icachePort
	Port to connect to L1 instruction cache. More...

DcachePort	dcachePort
	Port to connect to L1 data cache. More...

const RequestorID	instRequestorID
	Requestor id for instruction read requests. More...

const RequestorID	dataRequestorID
	Requestor id for data read and write requests. More...

std::string	instTraceFile
	File names for input instruction and data traces. More...

std::string	dataTraceFile

FixedRetryGen	icacheGen
	Instance of FixedRetryGen to replay instruction read requests. More...

ElasticDataGen	dcacheGen
	Instance of ElasticDataGen to replay data read and write requests. More...

EventFunctionWrapper	icacheNextEvent
	Event for the control flow method schedIcacheNext() More...

EventFunctionWrapper	dcacheNextEvent
	Event for the control flow method schedDcacheNext() More...

bool	oneTraceComplete
	Set to true when one of the generators finishes replaying its trace. More...

Tick	traceOffset
	This stores the time offset in the trace, which is taken away from the ready times of requests. More...

CountedExitEvent *	execCompleteEvent
	A CountedExitEvent which when serviced decrements the counter. More...

const bool	enableEarlyExit
	Exit when any one Trace CPU completes its execution. More...

const uint64_t	progressMsgInterval
	Interval of committed instructions specified by the user at which a progress info message is printed. More...

uint64_t	progressMsgThreshold

gem5::TraceCPU::TraceStats	traceStats

Protected Attributes inherited from gem5::BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

RequestorID	_instRequestorId
	instruction side request id that must be placed in all requests More...

RequestorID	_dataRequestorId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

probing::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

probing::PMUUPtr	ppRetiredInstsPC

probing::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

probing::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

probing::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

probing::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

probing::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Static Protected Attributes
static int	numTraceCPUs = 0
	Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event used for counting down exit events. More...

Static Protected Attributes inherited from gem5::BaseCPU
static std::unique_ptr< GlobalStats >	globalStats
	Pointer to the global stat structure. More...

Additional Inherited Members
Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::BaseCPU
static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Public Attributes inherited from gem5::BaseCPU
ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

gem5::BaseCPU::BaseCPUStats	baseStats

Cycles	syscallRetryLatency

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Static Public Attributes inherited from gem5::BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

Protected Types inherited from gem5::BaseCPU
enum	CPUState { CPU_STATE_ON , CPU_STATE_SLEEP , CPU_STATE_WAKEUP }

Detailed Description

The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model.

The elastic trace is an execution trace with register data dependencies and ordering dependencies annotated to it. The trace cpu also replays a fixed timestamp fetch trace that is also generated by the elastic trace probe. This trace cpu model aims at achieving faster simulation compared to the detailed cpu model and good correlation when the same trace is used for playback on different memory sub-systems.

The TraceCPU inherits from BaseCPU so some virtual methods need to be defined. It has two port subclasses inherited from RequestPort for instruction and data ports. It issues the memory requests deducing the timing from the trace and without performing real execution of micro-ops. As soon as the last dependency for an instruction is complete, its computational delay, also provided in the input trace is added. The dependency-free nodes are maintained in a list, called 'ReadyList', ordered by ready time. Instructions which depend on load stall until the responses for read requests are received thus achieving elastic replay. If the dependency is not found when adding a new node, it is assumed complete. Thus, if this node is found to be completely dependency-free its issue time is calculated and it is added to the ready list immediately. This is encapsulated in the subclass ElasticDataGen.

If ready nodes are issued in an unconstrained way there can be more nodes outstanding which results in divergence in timing compared to the O3CPU. Therefore, the Trace CPU also models hardware resources. A sub-class to model hardware resources contains the maximum sizes of load buffer, store buffer and ROB. If resources are not available, the node is not issued. Such nodes that are pending issue are held in the 'depFreeQueue' structure.

Modeling the ROB size in the Trace CPU as a resource limitation is arguably the most important parameter of all resources. The ROB occupancy is estimated using the newly added field 'robNum'. We need to use ROB number as sequence number is at times much higher due to squashing and trace replay is focused on correct path modeling.

A map called 'inFlightNodes' is added to track nodes that are not only in the readyList but also load nodes that are executed (and thus removed from readyList) but are not complete. ReadyList handles what and when to execute next node while the inFlightNodes is used for resource modelling. The oldest ROB number is updated when any node occupies the ROB or when an entry in the ROB is released. The ROB occupancy is equal to the difference in the ROB number of the newly dependency-free node and the oldest ROB number in flight.

If no node depends on a non load/store node then there is no reason to track it in the dependency graph. We filter out such nodes but count them and add a weight field to the subsequent node that we do include in the trace. The weight field is used to model ROB occupancy during replay.

The depFreeQueue is chosen to be FIFO so that child nodes which are in program order get pushed into it in that order and thus issued in program order, like in the O3CPU. This is also why the dependents is made a sequential container, std::set to std::vector. We only check head of the depFreeQueue as nodes are issued in order and blocking on head models that better than looping the entire queue. An alternative choice would be to inspect top N pending nodes where N is the issue-width. This is left for future as the timing correlation looks good as it is.

At the start of an execution event, first we attempt to issue such pending nodes by checking if appropriate resources have become available. If yes, we compute the execute tick with respect to the time then. Then we proceed to complete nodes from the readyList.

When a read response is received, sometimes a dependency on it that was supposed to be released when it was issued is still not released. This occurs because the dependent gets added to the graph after the read was sent. So the check is made less strict and the dependency is marked complete on read response instead of insisting that it should have been removed on read sent.

There is a check for requests spanning two cache lines as this condition triggers an assert fail in the L1 cache. If it does then truncate the size to access only until the end of that line and ignore the remainder. Strictly-ordered requests are skipped and the dependencies on such requests are handled by simply marking them complete immediately.

A CountedExitEvent that contains a static int belonging to the Trace CPU class as a down counter is used to implement multi Trace CPU simulation exit.

Definition at line 142 of file trace_cpu.hh.

Constructor & Destructor Documentation

◆ TraceCPU()

gem5::TraceCPU::TraceCPU ( const TraceCPUParams & params )

Definition at line 49 of file trace_cpu.cc.

References schedIcacheNext().

Member Function Documentation

◆ checkAndSchedExitEvent()

void gem5::TraceCPU::checkAndSchedExitEvent ( )

protected

This is called when either generator finishes executing from the trace.

Definition at line 188 of file trace_cpu.cc.

References gem5::curTick(), enableEarlyExit, execCompleteEvent, gem5::exitSimLoop(), inform, gem5::Named::name(), oneTraceComplete, and gem5::EventManager::schedule().

Referenced by schedDcacheNext(), and schedIcacheNext().

◆ dcacheRecvTimingResp()

void gem5::TraceCPU::dcacheRecvTimingResp ( PacketPtr pkt )

When data cache port receives a response, this calls the dcache generator method handle to complete the load writeback.

Parameters

pkt	Pointer to packet received

Definition at line 1172 of file trace_cpu.cc.

References gem5::TraceCPU::ElasticDataGen::completeMemAccess(), dcacheGen, and DPRINTF.

Referenced by gem5::TraceCPU::DcachePort::recvTimingResp().

◆ dcacheRetryRecvd()

void gem5::TraceCPU::dcacheRetryRecvd ( )

When data cache port receives a retry, schedule event dcacheNextEvent.

Definition at line 1130 of file trace_cpu.cc.

References gem5::curTick(), dcacheNextEvent, DPRINTF, and gem5::EventManager::schedule().

Referenced by gem5::TraceCPU::DcachePort::recvReqRetry().

◆ getDataPort()

Port& gem5::TraceCPU::getDataPort ( )

inlinevirtual

Used to get a reference to the dcache port.

Implements gem5::BaseCPU.

Definition at line 1126 of file trace_cpu.hh.

References dcachePort.

Referenced by takeOverFrom().

◆ getInstPort()

Port& gem5::TraceCPU::getInstPort ( )

inlinevirtual

Used to get a reference to the icache port.

Implements gem5::BaseCPU.

Definition at line 1123 of file trace_cpu.hh.

References icachePort.

Referenced by takeOverFrom().

◆ icacheRetryRecvd()

void gem5::TraceCPU::icacheRetryRecvd ( )

When instruction cache port receives a retry, schedule event icacheNextEvent.

Definition at line 1120 of file trace_cpu.cc.

References gem5::curTick(), DPRINTF, icacheNextEvent, and gem5::EventManager::schedule().

Referenced by gem5::TraceCPU::IcachePort::recvReqRetry().

◆ init()

void gem5::TraceCPU::init ( )

virtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::BaseCPU.

Definition at line 105 of file trace_cpu.cc.

References gem5::TraceCPU::ElasticDataGen::adjustInitTraceOffset(), dataTraceFile, dcacheGen, dcacheNextEvent, DPRINTF, enableEarlyExit, execCompleteEvent, icacheGen, icacheNextEvent, inform, gem5::TraceCPU::FixedRetryGen::init(), gem5::TraceCPU::ElasticDataGen::init(), gem5::BaseCPU::init(), instTraceFile, gem5::Named::name(), numTraceCPUs, gem5::EventManager::schedule(), and traceOffset.

◆ schedDcacheNext()

void gem5::TraceCPU::schedDcacheNext ( )

protected

This is the control flow that uses the functionality of the dcacheGen to replay the trace.

It calls execute(). It checks if execution is complete and schedules an event to exit simulation accordingly.

Definition at line 174 of file trace_cpu.cc.

References gem5::BaseCPU::baseStats, checkAndSchedExitEvent(), gem5::Clocked::clockEdge(), gem5::Clocked::clockPeriod(), dcacheGen, DPRINTF, gem5::TraceCPU::ElasticDataGen::execute(), gem5::TraceCPU::ElasticDataGen::isExecComplete(), and gem5::BaseCPU::BaseCPUStats::numCycles.

◆ schedDcacheNextEvent()

void gem5::TraceCPU::schedDcacheNextEvent ( Tick when )

Schedule event dcacheNextEvent at the given tick.

Parameters

when	Tick at which to schedule event

Definition at line 1140 of file trace_cpu.cc.

References dcacheNextEvent, DPRINTF, gem5::TraceCPU::TraceStats::numSchedDcacheEvent, gem5::EventManager::reschedule(), gem5::EventManager::schedule(), gem5::Event::scheduled(), traceStats, and gem5::Event::when().

Referenced by gem5::TraceCPU::ElasticDataGen::completeMemAccess(), and gem5::TraceCPU::ElasticDataGen::execute().

◆ schedIcacheNext()

void gem5::TraceCPU::schedIcacheNext ( )

protected

This is the control flow that uses the functionality of the icacheGen to replay the trace.

It calls tryNext(). If it returns true then next event is scheduled at curTick() plus delta. If it returns false then delta is ignored and control is brought back via recvRetry().

Definition at line 148 of file trace_cpu.cc.

References checkAndSchedExitEvent(), gem5::curTick(), DPRINTF, icacheGen, icacheNextEvent, gem5::TraceCPU::FixedRetryGen::isTraceComplete(), gem5::TraceCPU::TraceStats::numSchedIcacheEvent, gem5::EventManager::schedule(), gem5::TraceCPU::FixedRetryGen::tickDelta(), traceStats, and gem5::TraceCPU::FixedRetryGen::tryNext().

Referenced by TraceCPU().

◆ takeOverFrom()

void gem5::TraceCPU::takeOverFrom ( BaseCPU * cpu )

virtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented from gem5::BaseCPU.

Definition at line 97 of file trace_cpu.cc.

References getDataPort(), gem5::BaseCPU::getDataPort(), getInstPort(), gem5::BaseCPU::getInstPort(), and gem5::Port::takeOverFrom().

◆ totalInsts()

Counter gem5::TraceCPU::totalInsts ( ) const

inlinevirtual

This is a pure virtual function in BaseCPU.

As we don't know how many insts are in the trace but only know how how many micro-ops are we cannot count this stat.

Returns: 0

Implements gem5::BaseCPU.

Definition at line 157 of file trace_cpu.hh.

◆ totalOps()

Counter gem5::TraceCPU::totalOps ( ) const

inlinevirtual

Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are modelled in the TraceCPU replay.

Returns: number of micro-ops i.e. nodes in the elastic data generator

Implements gem5::BaseCPU.

Definition at line 165 of file trace_cpu.hh.

References gem5::TraceCPU::TraceStats::numOps, traceStats, and gem5::statistics::ScalarBase< Derived, Stor >::value().

◆ updateNumOps()

void gem5::TraceCPU::updateNumOps ( uint64_t rob_num )

Definition at line 86 of file trace_cpu.cc.

References inform, gem5::Named::name(), gem5::TraceCPU::TraceStats::numOps, progressMsgInterval, progressMsgThreshold, traceStats, and gem5::statistics::ScalarBase< Derived, Stor >::value().

Referenced by gem5::TraceCPU::ElasticDataGen::completeMemAccess(), and gem5::TraceCPU::ElasticDataGen::execute().

◆ wakeup()

void gem5::TraceCPU::wakeup ( ThreadID tid = 0 )

inlinevirtual

Implements gem5::BaseCPU.

Definition at line 174 of file trace_cpu.hh.

Member Data Documentation

◆ dataRequestorID

const RequestorID gem5::TraceCPU::dataRequestorID

protected

Requestor id for data read and write requests.

Definition at line 316 of file trace_cpu.hh.

◆ dataTraceFile

std::string gem5::TraceCPU::dataTraceFile

protected

Definition at line 319 of file trace_cpu.hh.

Referenced by init().

◆ dcacheGen

ElasticDataGen gem5::TraceCPU::dcacheGen

protected

Instance of ElasticDataGen to replay data read and write requests.

Definition at line 1034 of file trace_cpu.hh.

Referenced by dcacheRecvTimingResp(), init(), and schedDcacheNext().

◆ dcacheNextEvent

EventFunctionWrapper gem5::TraceCPU::dcacheNextEvent

protected

Event for the control flow method schedDcacheNext()

Definition at line 1055 of file trace_cpu.hh.

Referenced by dcacheRetryRecvd(), init(), and schedDcacheNextEvent().

◆ dcachePort

DcachePort gem5::TraceCPU::dcachePort

protected

Port to connect to L1 data cache.

Definition at line 310 of file trace_cpu.hh.

Referenced by getDataPort().

◆ enableEarlyExit

const bool gem5::TraceCPU::enableEarlyExit

protected

Exit when any one Trace CPU completes its execution.

If this is configured true then the execCompleteEvent is not scheduled.

Definition at line 1093 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent(), and init().

◆ execCompleteEvent

CountedExitEvent* gem5::TraceCPU::execCompleteEvent

protected

A CountedExitEvent which when serviced decrements the counter.

A sim exit event is scheduled when the counter equals zero, that is all instances of Trace CPU have had their execCompleteEvent serviced.

Definition at line 1087 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent(), and init().

◆ icacheGen

FixedRetryGen gem5::TraceCPU::icacheGen

protected

Instance of FixedRetryGen to replay instruction read requests.

Definition at line 1031 of file trace_cpu.hh.

Referenced by init(), and schedIcacheNext().

◆ icacheNextEvent

EventFunctionWrapper gem5::TraceCPU::icacheNextEvent

protected

Event for the control flow method schedIcacheNext()

Definition at line 1052 of file trace_cpu.hh.

Referenced by icacheRetryRecvd(), init(), and schedIcacheNext().

◆ icachePort

IcachePort gem5::TraceCPU::icachePort

protected

Port to connect to L1 instruction cache.

Definition at line 307 of file trace_cpu.hh.

Referenced by getInstPort().

◆ instRequestorID

const RequestorID gem5::TraceCPU::instRequestorID

protected

Requestor id for instruction read requests.

Definition at line 313 of file trace_cpu.hh.

◆ instTraceFile

std::string gem5::TraceCPU::instTraceFile

protected

File names for input instruction and data traces.

Definition at line 319 of file trace_cpu.hh.

Referenced by init().

◆ numTraceCPUs

int gem5::TraceCPU::numTraceCPUs = 0

staticprotected

Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event used for counting down exit events.

It is incremented in the constructor call so that the total is arrived at automatically.

Definition at line 1080 of file trace_cpu.hh.

Referenced by init().

◆ oneTraceComplete

bool gem5::TraceCPU::oneTraceComplete

protected

Set to true when one of the generators finishes replaying its trace.

Definition at line 1064 of file trace_cpu.hh.

Referenced by checkAndSchedExitEvent().

◆ progressMsgInterval

const uint64_t gem5::TraceCPU::progressMsgInterval

protected

Interval of committed instructions specified by the user at which a progress info message is printed.

Definition at line 1099 of file trace_cpu.hh.

Referenced by updateNumOps().

◆ progressMsgThreshold

uint64_t gem5::TraceCPU::progressMsgThreshold

protected

Definition at line 1106 of file trace_cpu.hh.

Referenced by updateNumOps().

◆ traceOffset

Tick gem5::TraceCPU::traceOffset

protected

This stores the time offset in the trace, which is taken away from the ready times of requests.

This is specially useful because the time offset can be very large if the traces are generated from the middle of a program.

Definition at line 1072 of file trace_cpu.hh.

Referenced by init().

◆ traceStats

gem5::TraceCPU::TraceStats gem5::TraceCPU::traceStats

protected

Referenced by schedDcacheNextEvent(), schedIcacheNext(), totalOps(), and updateNumOps().

The documentation for this class was generated from the following files:

cpu/trace/trace_cpu.hh
cpu/trace/trace_cpu.cc

Classes

Public Member Functions

Protected Member Functions

Protected Attributes

Static Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ TraceCPU()

Member Function Documentation

◆ checkAndSchedExitEvent()

◆ dcacheRecvTimingResp()

◆ dcacheRetryRecvd()

◆ getDataPort()

◆ getInstPort()

◆ icacheRetryRecvd()

◆ init()

◆ schedDcacheNext()

◆ schedDcacheNextEvent()

◆ schedIcacheNext()

◆ takeOverFrom()

◆ totalInsts()

◆ totalOps()

◆ updateNumOps()

◆ wakeup()

Member Data Documentation

◆ dataRequestorID

◆ dataTraceFile

◆ dcacheGen

◆ dcacheNextEvent

◆ dcachePort

◆ enableEarlyExit

◆ execCompleteEvent

◆ icacheGen

◆ icacheNextEvent

◆ icachePort

◆ instRequestorID

◆ instTraceFile

◆ numTraceCPUs

◆ oneTraceComplete

◆ progressMsgInterval

◆ progressMsgThreshold

◆ traceOffset

◆ traceStats